1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Kevin Tian <kevin.tian@intel.com> 26 * 27 * Contributors: 28 * Zhi Wang <zhi.a.wang@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Zhenyu Wang <zhenyuw@linux.intel.com> 31 * Tina Zhang <tina.zhang@intel.com> 32 * Bing Niu <bing.niu@intel.com> 33 * 34 */ 35 36 #include "gt/intel_context.h" 37 #include "gt/intel_engine_regs.h" 38 #include "gt/intel_gpu_commands.h" 39 #include "gt/intel_gt_regs.h" 40 #include "gt/intel_ring.h" 41 42 #include "gvt.h" 43 #include "i915_drv.h" 44 #include "i915_reg.h" 45 #include "i915_wait_util.h" 46 #include "trace.h" 47 48 #define GEN9_MOCS_SIZE 64 49 50 struct engine_mmio { 51 enum intel_engine_id id; 52 i915_reg_t reg; 53 u32 mask; 54 bool in_context; 55 u32 value; 56 }; 57 58 /* Raw offset is append to each line for convenience. */ 59 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { 60 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */ 61 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 62 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 63 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 64 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 65 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 66 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 67 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 68 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 69 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 70 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 71 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 72 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 73 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 74 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 75 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 76 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 77 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 78 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 79 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 80 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 81 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 82 83 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 84 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 85 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 86 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 87 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 88 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 89 }; 90 91 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 92 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */ 93 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 94 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 95 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 96 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 97 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 98 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 99 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 100 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 101 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 102 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 103 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 104 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 105 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 106 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 107 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 108 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 109 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 110 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 111 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 112 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 113 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 114 115 {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ 116 {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ 117 {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ 118 {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ 119 {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ 120 {RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */ 121 {RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */ 122 {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */ 123 {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ 124 {RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */ 125 {RCS0, _MMIO(0xe184), 0xffff, true}, /* GEN8_HALF_SLICE_CHICKEN3 */ 126 {RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */ 127 {RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */ 128 {RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */ 129 {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */ 130 {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */ 131 {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */ 132 {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */ 133 {RCS0, TRVADR, 0, true}, /* 0x4df0 */ 134 {RCS0, TRTTE, 0, true}, /* 0x4df4 */ 135 {RCS0, _MMIO(0x4dfc), 0, true}, 136 137 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 138 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 139 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 140 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 141 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 142 143 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */ 144 145 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */ 146 147 {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ 148 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 149 {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ 150 {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ 151 152 {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ 153 {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */ 154 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */ 155 156 {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ 157 {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ 158 {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ 159 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 160 }; 161 162 static struct { 163 bool initialized; 164 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE]; 165 u32 l3cc_table[GEN9_MOCS_SIZE / 2]; 166 } gen9_render_mocs; 167 168 static u32 gen9_mocs_mmio_offset_list[] = { 169 [RCS0] = 0xc800, 170 [VCS0] = 0xc900, 171 [VCS1] = 0xca00, 172 [BCS0] = 0xcc00, 173 [VECS0] = 0xcb00, 174 }; 175 176 static void load_render_mocs(const struct intel_engine_cs *engine) 177 { 178 struct intel_gvt *gvt = engine->i915->gvt; 179 struct intel_uncore *uncore = engine->uncore; 180 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; 181 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; 182 i915_reg_t offset; 183 int ring_id, i; 184 185 /* Platform doesn't have mocs mmios. */ 186 if (!regs) 187 return; 188 189 for (ring_id = 0; ring_id < cnt; ring_id++) { 190 if (!HAS_ENGINE(engine->gt, ring_id)) 191 continue; 192 193 offset.reg = regs[ring_id]; 194 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 195 gen9_render_mocs.control_table[ring_id][i] = 196 intel_uncore_read_fw(uncore, offset); 197 offset.reg += 4; 198 } 199 } 200 201 offset.reg = 0xb020; 202 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 203 gen9_render_mocs.l3cc_table[i] = 204 intel_uncore_read_fw(uncore, offset); 205 offset.reg += 4; 206 } 207 gen9_render_mocs.initialized = true; 208 } 209 210 static int 211 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu, 212 struct i915_request *req) 213 { 214 u32 *cs; 215 int ret; 216 struct engine_mmio *mmio; 217 struct intel_gvt *gvt = vgpu->gvt; 218 int ring_id = req->engine->id; 219 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; 220 221 if (count == 0) 222 return 0; 223 224 ret = req->engine->emit_flush(req, EMIT_BARRIER); 225 if (ret) 226 return ret; 227 228 cs = intel_ring_begin(req, count * 2 + 2); 229 if (IS_ERR(cs)) 230 return PTR_ERR(cs); 231 232 *cs++ = MI_LOAD_REGISTER_IMM(count); 233 for (mmio = gvt->engine_mmio_list.mmio; 234 i915_mmio_reg_valid(mmio->reg); mmio++) { 235 if (mmio->id != ring_id || !mmio->in_context) 236 continue; 237 238 *cs++ = i915_mmio_reg_offset(mmio->reg); 239 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); 240 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 241 *(cs-2), *(cs-1), vgpu->id, ring_id); 242 } 243 244 *cs++ = MI_NOOP; 245 intel_ring_advance(req, cs); 246 247 ret = req->engine->emit_flush(req, EMIT_BARRIER); 248 if (ret) 249 return ret; 250 251 return 0; 252 } 253 254 static int 255 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu, 256 struct i915_request *req) 257 { 258 unsigned int index; 259 u32 *cs; 260 261 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2); 262 if (IS_ERR(cs)) 263 return PTR_ERR(cs); 264 265 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); 266 267 for (index = 0; index < GEN9_MOCS_SIZE; index++) { 268 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); 269 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); 270 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 271 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 272 273 } 274 275 *cs++ = MI_NOOP; 276 intel_ring_advance(req, cs); 277 278 return 0; 279 } 280 281 static int 282 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu, 283 struct i915_request *req) 284 { 285 unsigned int index; 286 u32 *cs; 287 288 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2); 289 if (IS_ERR(cs)) 290 return PTR_ERR(cs); 291 292 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); 293 294 for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) { 295 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); 296 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); 297 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 298 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 299 300 } 301 302 *cs++ = MI_NOOP; 303 intel_ring_advance(req, cs); 304 305 return 0; 306 } 307 308 /* 309 * Use lri command to initialize the mmio which is in context state image for 310 * inhibit context, it contains tracked engine mmio, render_mocs and 311 * render_mocs_l3cc. 312 */ 313 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 314 struct i915_request *req) 315 { 316 int ret; 317 u32 *cs; 318 319 cs = intel_ring_begin(req, 2); 320 if (IS_ERR(cs)) 321 return PTR_ERR(cs); 322 323 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 324 *cs++ = MI_NOOP; 325 intel_ring_advance(req, cs); 326 327 ret = restore_context_mmio_for_inhibit(vgpu, req); 328 if (ret) 329 goto out; 330 331 /* no MOCS register in context except render engine */ 332 if (req->engine->id != RCS0) 333 goto out; 334 335 ret = restore_render_mocs_control_for_inhibit(vgpu, req); 336 if (ret) 337 goto out; 338 339 ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req); 340 if (ret) 341 goto out; 342 343 out: 344 cs = intel_ring_begin(req, 2); 345 if (IS_ERR(cs)) 346 return PTR_ERR(cs); 347 348 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 349 *cs++ = MI_NOOP; 350 intel_ring_advance(req, cs); 351 352 return ret; 353 } 354 355 static u32 gen8_tlb_mmio_offset_list[] = { 356 [RCS0] = 0x4260, 357 [VCS0] = 0x4264, 358 [VCS1] = 0x4268, 359 [BCS0] = 0x426c, 360 [VECS0] = 0x4270, 361 }; 362 363 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, 364 const struct intel_engine_cs *engine) 365 { 366 struct intel_uncore *uncore = engine->uncore; 367 struct intel_vgpu_submission *s = &vgpu->submission; 368 u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list; 369 u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt; 370 enum forcewake_domains fw; 371 i915_reg_t reg; 372 373 if (!regs) 374 return; 375 376 if (drm_WARN_ON(&engine->i915->drm, engine->id >= cnt)) 377 return; 378 379 if (!test_and_clear_bit(engine->id, (void *)s->tlb_handle_pending)) 380 return; 381 382 reg = _MMIO(regs[engine->id]); 383 384 /* WaForceWakeRenderDuringMmioTLBInvalidate:skl 385 * we need to put a forcewake when invalidating RCS TLB caches, 386 * otherwise device can go to RC6 state and interrupt invalidation 387 * process 388 */ 389 fw = intel_uncore_forcewake_for_reg(uncore, reg, 390 FW_REG_READ | FW_REG_WRITE); 391 if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) >= 9) 392 fw |= FORCEWAKE_RENDER; 393 394 intel_uncore_forcewake_get(uncore, fw); 395 396 intel_uncore_write_fw(uncore, reg, 0x1); 397 398 if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50)) 399 gvt_vgpu_err("timeout in invalidate ring %s tlb\n", 400 engine->name); 401 else 402 vgpu_vreg_t(vgpu, reg) = 0; 403 404 intel_uncore_forcewake_put(uncore, fw); 405 406 gvt_dbg_core("invalidate TLB for ring %s\n", engine->name); 407 } 408 409 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 410 const struct intel_engine_cs *engine) 411 { 412 u32 regs[] = { 413 [RCS0] = 0xc800, 414 [VCS0] = 0xc900, 415 [VCS1] = 0xca00, 416 [BCS0] = 0xcc00, 417 [VECS0] = 0xcb00, 418 }; 419 struct intel_uncore *uncore = engine->uncore; 420 i915_reg_t offset, l3_offset; 421 u32 old_v, new_v; 422 int i; 423 424 if (drm_WARN_ON(&engine->i915->drm, engine->id >= ARRAY_SIZE(regs))) 425 return; 426 427 if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) == 9) 428 return; 429 430 if (!pre && !gen9_render_mocs.initialized) 431 load_render_mocs(engine); 432 433 offset.reg = regs[engine->id]; 434 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 435 if (pre) 436 old_v = vgpu_vreg_t(pre, offset); 437 else 438 old_v = gen9_render_mocs.control_table[engine->id][i]; 439 if (next) 440 new_v = vgpu_vreg_t(next, offset); 441 else 442 new_v = gen9_render_mocs.control_table[engine->id][i]; 443 444 if (old_v != new_v) 445 intel_uncore_write_fw(uncore, offset, new_v); 446 447 offset.reg += 4; 448 } 449 450 if (engine->id == RCS0) { 451 l3_offset.reg = 0xb020; 452 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 453 if (pre) 454 old_v = vgpu_vreg_t(pre, l3_offset); 455 else 456 old_v = gen9_render_mocs.l3cc_table[i]; 457 if (next) 458 new_v = vgpu_vreg_t(next, l3_offset); 459 else 460 new_v = gen9_render_mocs.l3cc_table[i]; 461 462 if (old_v != new_v) 463 intel_uncore_write_fw(uncore, l3_offset, new_v); 464 465 l3_offset.reg += 4; 466 } 467 } 468 } 469 470 #define CTX_CONTEXT_CONTROL_VAL 0x03 471 472 bool is_inhibit_context(struct intel_context *ce) 473 { 474 const u32 *reg_state = ce->lrc_reg_state; 475 u32 inhibit_mask = 476 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 477 478 return inhibit_mask == 479 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); 480 } 481 482 /* Switch ring mmio values (context). */ 483 static void switch_mmio(struct intel_vgpu *pre, 484 struct intel_vgpu *next, 485 const struct intel_engine_cs *engine) 486 { 487 struct intel_uncore *uncore = engine->uncore; 488 struct intel_vgpu_submission *s; 489 struct engine_mmio *mmio; 490 u32 old_v, new_v; 491 492 if (GRAPHICS_VER(engine->i915) >= 9) 493 switch_mocs(pre, next, engine); 494 495 for (mmio = engine->i915->gvt->engine_mmio_list.mmio; 496 i915_mmio_reg_valid(mmio->reg); mmio++) { 497 if (mmio->id != engine->id) 498 continue; 499 /* 500 * No need to do save or restore of the mmio which is in context 501 * state image on gen9, it's initialized by lri command and 502 * save or restore with context together. 503 */ 504 if (GRAPHICS_VER(engine->i915) == 9 && mmio->in_context) 505 continue; 506 507 // save 508 if (pre) { 509 vgpu_vreg_t(pre, mmio->reg) = 510 intel_uncore_read_fw(uncore, mmio->reg); 511 if (mmio->mask) 512 vgpu_vreg_t(pre, mmio->reg) &= 513 ~(mmio->mask << 16); 514 old_v = vgpu_vreg_t(pre, mmio->reg); 515 } else { 516 old_v = mmio->value = 517 intel_uncore_read_fw(uncore, mmio->reg); 518 } 519 520 // restore 521 if (next) { 522 s = &next->submission; 523 /* 524 * No need to restore the mmio which is in context state 525 * image if it's not inhibit context, it will restore 526 * itself. 527 */ 528 if (mmio->in_context && 529 !is_inhibit_context(s->shadow[engine->id])) 530 continue; 531 532 if (mmio->mask) 533 new_v = vgpu_vreg_t(next, mmio->reg) | 534 (mmio->mask << 16); 535 else 536 new_v = vgpu_vreg_t(next, mmio->reg); 537 } else { 538 if (mmio->in_context) 539 continue; 540 if (mmio->mask) 541 new_v = mmio->value | (mmio->mask << 16); 542 else 543 new_v = mmio->value; 544 } 545 546 intel_uncore_write_fw(uncore, mmio->reg, new_v); 547 548 trace_render_mmio(pre ? pre->id : 0, 549 next ? next->id : 0, 550 "switch", 551 i915_mmio_reg_offset(mmio->reg), 552 old_v, new_v); 553 } 554 555 if (next) 556 handle_tlb_pending_event(next, engine); 557 } 558 559 /** 560 * intel_gvt_switch_mmio - switch mmio context of specific engine 561 * @pre: the last vGPU that own the engine 562 * @next: the vGPU to switch to 563 * @engine: the engine 564 * 565 * If pre is null indicates that host own the engine. If next is null 566 * indicates that we are switching to host workload. 567 */ 568 void intel_gvt_switch_mmio(struct intel_vgpu *pre, 569 struct intel_vgpu *next, 570 const struct intel_engine_cs *engine) 571 { 572 if (WARN(!pre && !next, "switch ring %s from host to HOST\n", 573 engine->name)) 574 return; 575 576 gvt_dbg_render("switch ring %s from %s to %s\n", engine->name, 577 pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); 578 579 /** 580 * We are using raw mmio access wrapper to improve the 581 * performance for batch mmio read/write, so we need 582 * handle forcewake manually. 583 */ 584 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); 585 switch_mmio(pre, next, engine); 586 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); 587 } 588 589 /** 590 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list 591 * @gvt: GVT device 592 * 593 */ 594 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) 595 { 596 struct engine_mmio *mmio; 597 598 if (GRAPHICS_VER(gvt->gt->i915) >= 9) { 599 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list; 600 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 601 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 602 gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list; 603 gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list); 604 } else { 605 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list; 606 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 607 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 608 } 609 610 for (mmio = gvt->engine_mmio_list.mmio; 611 i915_mmio_reg_valid(mmio->reg); mmio++) { 612 if (mmio->in_context) { 613 gvt->engine_mmio_list.ctx_mmio_count[mmio->id]++; 614 intel_gvt_mmio_set_sr_in_ctx(gvt, mmio->reg.reg); 615 } 616 } 617 } 618