1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Kevin Tian <kevin.tian@intel.com> 26 * Dexuan Cui 27 * 28 * Contributors: 29 * Tina Zhang <tina.zhang@intel.com> 30 * Min He <min.he@intel.com> 31 * Niu Bing <bing.niu@intel.com> 32 * Zhi Wang <zhi.a.wang@intel.com> 33 * 34 */ 35 36 #include <linux/vmalloc.h> 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "display/intel_display_regs.h" 40 #include "gvt.h" 41 42 #include "display/bxt_dpio_phy_regs.h" 43 #include "display/intel_dpio_phy.h" 44 #include "gt/intel_gt_regs.h" 45 46 /** 47 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset 48 * @vgpu: a vGPU 49 * @gpa: guest physical address 50 * 51 * Returns: 52 * Zero on success, negative error code if failed 53 */ 54 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa) 55 { 56 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 57 return gpa - gttmmio_gpa; 58 } 59 60 #define reg_is_mmio(gvt, reg) \ 61 (reg >= 0 && reg < gvt->device_info.mmio_size) 62 63 #define reg_is_gtt(gvt, reg) \ 64 (reg >= gvt->device_info.gtt_start_offset \ 65 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) 66 67 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa, 68 void *p_data, unsigned int bytes, bool read) 69 { 70 struct intel_gvt *gvt = NULL; 71 void *pt = NULL; 72 unsigned int offset = 0; 73 74 if (!vgpu || !p_data) 75 return; 76 77 gvt = vgpu->gvt; 78 mutex_lock(&vgpu->vgpu_lock); 79 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 80 if (reg_is_mmio(gvt, offset)) { 81 if (read) 82 intel_vgpu_default_mmio_read(vgpu, offset, p_data, 83 bytes); 84 else 85 intel_vgpu_default_mmio_write(vgpu, offset, p_data, 86 bytes); 87 } else if (reg_is_gtt(gvt, offset)) { 88 offset -= gvt->device_info.gtt_start_offset; 89 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset; 90 if (read) 91 memcpy(p_data, pt, bytes); 92 else 93 memcpy(pt, p_data, bytes); 94 95 } 96 mutex_unlock(&vgpu->vgpu_lock); 97 } 98 99 /** 100 * intel_vgpu_emulate_mmio_read - emulate MMIO read 101 * @vgpu: a vGPU 102 * @pa: guest physical address 103 * @p_data: data return buffer 104 * @bytes: access data length 105 * 106 * Returns: 107 * Zero on success, negative error code if failed 108 */ 109 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, 110 void *p_data, unsigned int bytes) 111 { 112 struct intel_gvt *gvt = vgpu->gvt; 113 struct drm_i915_private *i915 = gvt->gt->i915; 114 unsigned int offset = 0; 115 int ret = -EINVAL; 116 117 if (vgpu->failsafe) { 118 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true); 119 return 0; 120 } 121 mutex_lock(&vgpu->vgpu_lock); 122 123 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 124 125 if (drm_WARN_ON(&i915->drm, bytes > 8)) 126 goto err; 127 128 if (reg_is_gtt(gvt, offset)) { 129 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && 130 !IS_ALIGNED(offset, 8))) 131 goto err; 132 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) 133 goto err; 134 if (drm_WARN_ON(&i915->drm, 135 !reg_is_gtt(gvt, offset + bytes - 1))) 136 goto err; 137 138 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset, 139 p_data, bytes); 140 if (ret) 141 goto err; 142 goto out; 143 } 144 145 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { 146 ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes); 147 goto out; 148 } 149 150 if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1))) 151 goto err; 152 153 if (!intel_gvt_mmio_is_unalign(gvt, offset)) { 154 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes))) 155 goto err; 156 } 157 158 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true); 159 if (ret < 0) 160 goto err; 161 162 intel_gvt_mmio_set_accessed(gvt, offset); 163 ret = 0; 164 goto out; 165 166 err: 167 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n", 168 offset, bytes); 169 out: 170 mutex_unlock(&vgpu->vgpu_lock); 171 return ret; 172 } 173 174 /** 175 * intel_vgpu_emulate_mmio_write - emulate MMIO write 176 * @vgpu: a vGPU 177 * @pa: guest physical address 178 * @p_data: write data buffer 179 * @bytes: access data length 180 * 181 * Returns: 182 * Zero on success, negative error code if failed 183 */ 184 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, 185 void *p_data, unsigned int bytes) 186 { 187 struct intel_gvt *gvt = vgpu->gvt; 188 struct drm_i915_private *i915 = gvt->gt->i915; 189 unsigned int offset = 0; 190 int ret = -EINVAL; 191 192 if (vgpu->failsafe) { 193 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false); 194 return 0; 195 } 196 197 mutex_lock(&vgpu->vgpu_lock); 198 199 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 200 201 if (drm_WARN_ON(&i915->drm, bytes > 8)) 202 goto err; 203 204 if (reg_is_gtt(gvt, offset)) { 205 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && 206 !IS_ALIGNED(offset, 8))) 207 goto err; 208 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) 209 goto err; 210 if (drm_WARN_ON(&i915->drm, 211 !reg_is_gtt(gvt, offset + bytes - 1))) 212 goto err; 213 214 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset, 215 p_data, bytes); 216 if (ret) 217 goto err; 218 goto out; 219 } 220 221 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { 222 ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes); 223 goto out; 224 } 225 226 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false); 227 if (ret < 0) 228 goto err; 229 230 intel_gvt_mmio_set_accessed(gvt, offset); 231 ret = 0; 232 goto out; 233 err: 234 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, 235 bytes); 236 out: 237 mutex_unlock(&vgpu->vgpu_lock); 238 return ret; 239 } 240 241 242 /** 243 * intel_vgpu_reset_mmio - reset virtual MMIO space 244 * @vgpu: a vGPU 245 * @dmlr: whether this is device model level reset 246 */ 247 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr) 248 { 249 struct intel_gvt *gvt = vgpu->gvt; 250 const struct intel_gvt_device_info *info = &gvt->device_info; 251 void *mmio = gvt->firmware.mmio; 252 253 if (dmlr) { 254 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size); 255 256 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; 257 258 /* set the bit 0:2(Core C-State ) to C0 */ 259 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; 260 261 /* uc reset hw expect GS_MIA_IN_RESET */ 262 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 263 264 if (IS_BROXTON(vgpu->gvt->gt->i915)) { 265 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= 266 ~(BIT(0) | BIT(1)); 267 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 268 ~PHY_POWER_GOOD; 269 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 270 ~PHY_POWER_GOOD; 271 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= 272 ~BIT(30); 273 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= 274 ~BIT(30); 275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 276 ~BXT_PHY_LANE_ENABLED; 277 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 278 BXT_PHY_CMNLANE_POWERDOWN_ACK | 279 BXT_PHY_LANE_POWERDOWN_ACK; 280 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 281 ~BXT_PHY_LANE_ENABLED; 282 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 283 BXT_PHY_CMNLANE_POWERDOWN_ACK | 284 BXT_PHY_LANE_POWERDOWN_ACK; 285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 286 ~BXT_PHY_LANE_ENABLED; 287 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 288 BXT_PHY_CMNLANE_POWERDOWN_ACK | 289 BXT_PHY_LANE_POWERDOWN_ACK; 290 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 291 SKL_FUSE_DOWNLOAD_STATUS | 292 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 293 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 294 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 295 } 296 } else { 297 #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200) 298 /* only reset the engine related, so starting with 0x44200 299 * interrupt include DE,display mmio related will not be 300 * touched 301 */ 302 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET); 303 } 304 305 } 306 307 /** 308 * intel_vgpu_init_mmio - init MMIO space 309 * @vgpu: a vGPU 310 * 311 * Returns: 312 * Zero on success, negative error code if failed 313 */ 314 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu) 315 { 316 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; 317 318 vgpu->mmio.vreg = vzalloc(info->mmio_size); 319 if (!vgpu->mmio.vreg) 320 return -ENOMEM; 321 322 intel_vgpu_reset_mmio(vgpu, true); 323 324 return 0; 325 } 326 327 /** 328 * intel_vgpu_clean_mmio - clean MMIO space 329 * @vgpu: a vGPU 330 * 331 */ 332 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu) 333 { 334 vfree(vgpu->mmio.vreg); 335 vgpu->mmio.vreg = NULL; 336 } 337