1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Kevin Tian <kevin.tian@intel.com> 26 * Dexuan Cui 27 * 28 * Contributors: 29 * Tina Zhang <tina.zhang@intel.com> 30 * Min He <min.he@intel.com> 31 * Niu Bing <bing.niu@intel.com> 32 * Zhi Wang <zhi.a.wang@intel.com> 33 * 34 */ 35 36 #include <linux/vmalloc.h> 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "gvt.h" 40 41 #include "display/intel_dpio_phy.h" 42 #include "gt/intel_gt_regs.h" 43 44 /** 45 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset 46 * @vgpu: a vGPU 47 * @gpa: guest physical address 48 * 49 * Returns: 50 * Zero on success, negative error code if failed 51 */ 52 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa) 53 { 54 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 55 return gpa - gttmmio_gpa; 56 } 57 58 #define reg_is_mmio(gvt, reg) \ 59 (reg >= 0 && reg < gvt->device_info.mmio_size) 60 61 #define reg_is_gtt(gvt, reg) \ 62 (reg >= gvt->device_info.gtt_start_offset \ 63 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) 64 65 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa, 66 void *p_data, unsigned int bytes, bool read) 67 { 68 struct intel_gvt *gvt = NULL; 69 void *pt = NULL; 70 unsigned int offset = 0; 71 72 if (!vgpu || !p_data) 73 return; 74 75 gvt = vgpu->gvt; 76 mutex_lock(&vgpu->vgpu_lock); 77 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 78 if (reg_is_mmio(gvt, offset)) { 79 if (read) 80 intel_vgpu_default_mmio_read(vgpu, offset, p_data, 81 bytes); 82 else 83 intel_vgpu_default_mmio_write(vgpu, offset, p_data, 84 bytes); 85 } else if (reg_is_gtt(gvt, offset)) { 86 offset -= gvt->device_info.gtt_start_offset; 87 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset; 88 if (read) 89 memcpy(p_data, pt, bytes); 90 else 91 memcpy(pt, p_data, bytes); 92 93 } 94 mutex_unlock(&vgpu->vgpu_lock); 95 } 96 97 /** 98 * intel_vgpu_emulate_mmio_read - emulate MMIO read 99 * @vgpu: a vGPU 100 * @pa: guest physical address 101 * @p_data: data return buffer 102 * @bytes: access data length 103 * 104 * Returns: 105 * Zero on success, negative error code if failed 106 */ 107 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, 108 void *p_data, unsigned int bytes) 109 { 110 struct intel_gvt *gvt = vgpu->gvt; 111 struct drm_i915_private *i915 = gvt->gt->i915; 112 unsigned int offset = 0; 113 int ret = -EINVAL; 114 115 if (vgpu->failsafe) { 116 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true); 117 return 0; 118 } 119 mutex_lock(&vgpu->vgpu_lock); 120 121 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 122 123 if (drm_WARN_ON(&i915->drm, bytes > 8)) 124 goto err; 125 126 if (reg_is_gtt(gvt, offset)) { 127 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && 128 !IS_ALIGNED(offset, 8))) 129 goto err; 130 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) 131 goto err; 132 if (drm_WARN_ON(&i915->drm, 133 !reg_is_gtt(gvt, offset + bytes - 1))) 134 goto err; 135 136 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset, 137 p_data, bytes); 138 if (ret) 139 goto err; 140 goto out; 141 } 142 143 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { 144 ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes); 145 goto out; 146 } 147 148 if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1))) 149 goto err; 150 151 if (!intel_gvt_mmio_is_unalign(gvt, offset)) { 152 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes))) 153 goto err; 154 } 155 156 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true); 157 if (ret < 0) 158 goto err; 159 160 intel_gvt_mmio_set_accessed(gvt, offset); 161 ret = 0; 162 goto out; 163 164 err: 165 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n", 166 offset, bytes); 167 out: 168 mutex_unlock(&vgpu->vgpu_lock); 169 return ret; 170 } 171 172 /** 173 * intel_vgpu_emulate_mmio_write - emulate MMIO write 174 * @vgpu: a vGPU 175 * @pa: guest physical address 176 * @p_data: write data buffer 177 * @bytes: access data length 178 * 179 * Returns: 180 * Zero on success, negative error code if failed 181 */ 182 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, 183 void *p_data, unsigned int bytes) 184 { 185 struct intel_gvt *gvt = vgpu->gvt; 186 struct drm_i915_private *i915 = gvt->gt->i915; 187 unsigned int offset = 0; 188 int ret = -EINVAL; 189 190 if (vgpu->failsafe) { 191 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false); 192 return 0; 193 } 194 195 mutex_lock(&vgpu->vgpu_lock); 196 197 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 198 199 if (drm_WARN_ON(&i915->drm, bytes > 8)) 200 goto err; 201 202 if (reg_is_gtt(gvt, offset)) { 203 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && 204 !IS_ALIGNED(offset, 8))) 205 goto err; 206 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) 207 goto err; 208 if (drm_WARN_ON(&i915->drm, 209 !reg_is_gtt(gvt, offset + bytes - 1))) 210 goto err; 211 212 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset, 213 p_data, bytes); 214 if (ret) 215 goto err; 216 goto out; 217 } 218 219 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { 220 ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes); 221 goto out; 222 } 223 224 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false); 225 if (ret < 0) 226 goto err; 227 228 intel_gvt_mmio_set_accessed(gvt, offset); 229 ret = 0; 230 goto out; 231 err: 232 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, 233 bytes); 234 out: 235 mutex_unlock(&vgpu->vgpu_lock); 236 return ret; 237 } 238 239 240 /** 241 * intel_vgpu_reset_mmio - reset virtual MMIO space 242 * @vgpu: a vGPU 243 * @dmlr: whether this is device model level reset 244 */ 245 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr) 246 { 247 struct intel_gvt *gvt = vgpu->gvt; 248 const struct intel_gvt_device_info *info = &gvt->device_info; 249 void *mmio = gvt->firmware.mmio; 250 251 if (dmlr) { 252 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size); 253 254 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; 255 256 /* set the bit 0:2(Core C-State ) to C0 */ 257 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; 258 259 /* uc reset hw expect GS_MIA_IN_RESET */ 260 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 261 262 if (IS_BROXTON(vgpu->gvt->gt->i915)) { 263 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= 264 ~(BIT(0) | BIT(1)); 265 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 266 ~PHY_POWER_GOOD; 267 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 268 ~PHY_POWER_GOOD; 269 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= 270 ~BIT(30); 271 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= 272 ~BIT(30); 273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 274 ~BXT_PHY_LANE_ENABLED; 275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 276 BXT_PHY_CMNLANE_POWERDOWN_ACK | 277 BXT_PHY_LANE_POWERDOWN_ACK; 278 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 279 ~BXT_PHY_LANE_ENABLED; 280 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 281 BXT_PHY_CMNLANE_POWERDOWN_ACK | 282 BXT_PHY_LANE_POWERDOWN_ACK; 283 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 284 ~BXT_PHY_LANE_ENABLED; 285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 286 BXT_PHY_CMNLANE_POWERDOWN_ACK | 287 BXT_PHY_LANE_POWERDOWN_ACK; 288 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 289 SKL_FUSE_DOWNLOAD_STATUS | 290 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 291 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 292 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 293 } 294 } else { 295 #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200) 296 /* only reset the engine related, so starting with 0x44200 297 * interrupt include DE,display mmio related will not be 298 * touched 299 */ 300 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET); 301 } 302 303 } 304 305 /** 306 * intel_vgpu_init_mmio - init MMIO space 307 * @vgpu: a vGPU 308 * 309 * Returns: 310 * Zero on success, negative error code if failed 311 */ 312 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu) 313 { 314 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; 315 316 vgpu->mmio.vreg = vzalloc(info->mmio_size); 317 if (!vgpu->mmio.vreg) 318 return -ENOMEM; 319 320 intel_vgpu_reset_mmio(vgpu, true); 321 322 return 0; 323 } 324 325 /** 326 * intel_vgpu_clean_mmio - clean MMIO space 327 * @vgpu: a vGPU 328 * 329 */ 330 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu) 331 { 332 vfree(vgpu->mmio.vreg); 333 vgpu->mmio.vreg = NULL; 334 } 335