1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Kevin Tian <kevin.tian@intel.com> 26 * Dexuan Cui 27 * 28 * Contributors: 29 * Tina Zhang <tina.zhang@intel.com> 30 * Min He <min.he@intel.com> 31 * Niu Bing <bing.niu@intel.com> 32 * Zhi Wang <zhi.a.wang@intel.com> 33 * 34 */ 35 36 #include "i915_drv.h" 37 #include "i915_reg.h" 38 #include "gvt.h" 39 40 #include "gt/intel_gt_regs.h" 41 42 /** 43 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset 44 * @vgpu: a vGPU 45 * @gpa: guest physical address 46 * 47 * Returns: 48 * Zero on success, negative error code if failed 49 */ 50 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa) 51 { 52 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 53 return gpa - gttmmio_gpa; 54 } 55 56 #define reg_is_mmio(gvt, reg) \ 57 (reg >= 0 && reg < gvt->device_info.mmio_size) 58 59 #define reg_is_gtt(gvt, reg) \ 60 (reg >= gvt->device_info.gtt_start_offset \ 61 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) 62 63 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa, 64 void *p_data, unsigned int bytes, bool read) 65 { 66 struct intel_gvt *gvt = NULL; 67 void *pt = NULL; 68 unsigned int offset = 0; 69 70 if (!vgpu || !p_data) 71 return; 72 73 gvt = vgpu->gvt; 74 mutex_lock(&vgpu->vgpu_lock); 75 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 76 if (reg_is_mmio(gvt, offset)) { 77 if (read) 78 intel_vgpu_default_mmio_read(vgpu, offset, p_data, 79 bytes); 80 else 81 intel_vgpu_default_mmio_write(vgpu, offset, p_data, 82 bytes); 83 } else if (reg_is_gtt(gvt, offset)) { 84 offset -= gvt->device_info.gtt_start_offset; 85 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset; 86 if (read) 87 memcpy(p_data, pt, bytes); 88 else 89 memcpy(pt, p_data, bytes); 90 91 } 92 mutex_unlock(&vgpu->vgpu_lock); 93 } 94 95 /** 96 * intel_vgpu_emulate_mmio_read - emulate MMIO read 97 * @vgpu: a vGPU 98 * @pa: guest physical address 99 * @p_data: data return buffer 100 * @bytes: access data length 101 * 102 * Returns: 103 * Zero on success, negative error code if failed 104 */ 105 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, 106 void *p_data, unsigned int bytes) 107 { 108 struct intel_gvt *gvt = vgpu->gvt; 109 struct drm_i915_private *i915 = gvt->gt->i915; 110 unsigned int offset = 0; 111 int ret = -EINVAL; 112 113 if (vgpu->failsafe) { 114 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true); 115 return 0; 116 } 117 mutex_lock(&vgpu->vgpu_lock); 118 119 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 120 121 if (drm_WARN_ON(&i915->drm, bytes > 8)) 122 goto err; 123 124 if (reg_is_gtt(gvt, offset)) { 125 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && 126 !IS_ALIGNED(offset, 8))) 127 goto err; 128 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) 129 goto err; 130 if (drm_WARN_ON(&i915->drm, 131 !reg_is_gtt(gvt, offset + bytes - 1))) 132 goto err; 133 134 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset, 135 p_data, bytes); 136 if (ret) 137 goto err; 138 goto out; 139 } 140 141 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { 142 ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes); 143 goto out; 144 } 145 146 if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1))) 147 goto err; 148 149 if (!intel_gvt_mmio_is_unalign(gvt, offset)) { 150 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes))) 151 goto err; 152 } 153 154 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true); 155 if (ret < 0) 156 goto err; 157 158 intel_gvt_mmio_set_accessed(gvt, offset); 159 ret = 0; 160 goto out; 161 162 err: 163 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n", 164 offset, bytes); 165 out: 166 mutex_unlock(&vgpu->vgpu_lock); 167 return ret; 168 } 169 170 /** 171 * intel_vgpu_emulate_mmio_write - emulate MMIO write 172 * @vgpu: a vGPU 173 * @pa: guest physical address 174 * @p_data: write data buffer 175 * @bytes: access data length 176 * 177 * Returns: 178 * Zero on success, negative error code if failed 179 */ 180 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, 181 void *p_data, unsigned int bytes) 182 { 183 struct intel_gvt *gvt = vgpu->gvt; 184 struct drm_i915_private *i915 = gvt->gt->i915; 185 unsigned int offset = 0; 186 int ret = -EINVAL; 187 188 if (vgpu->failsafe) { 189 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false); 190 return 0; 191 } 192 193 mutex_lock(&vgpu->vgpu_lock); 194 195 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa); 196 197 if (drm_WARN_ON(&i915->drm, bytes > 8)) 198 goto err; 199 200 if (reg_is_gtt(gvt, offset)) { 201 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) && 202 !IS_ALIGNED(offset, 8))) 203 goto err; 204 if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8)) 205 goto err; 206 if (drm_WARN_ON(&i915->drm, 207 !reg_is_gtt(gvt, offset + bytes - 1))) 208 goto err; 209 210 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset, 211 p_data, bytes); 212 if (ret) 213 goto err; 214 goto out; 215 } 216 217 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) { 218 ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes); 219 goto out; 220 } 221 222 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false); 223 if (ret < 0) 224 goto err; 225 226 intel_gvt_mmio_set_accessed(gvt, offset); 227 ret = 0; 228 goto out; 229 err: 230 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset, 231 bytes); 232 out: 233 mutex_unlock(&vgpu->vgpu_lock); 234 return ret; 235 } 236 237 238 /** 239 * intel_vgpu_reset_mmio - reset virtual MMIO space 240 * @vgpu: a vGPU 241 * @dmlr: whether this is device model level reset 242 */ 243 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr) 244 { 245 struct intel_gvt *gvt = vgpu->gvt; 246 const struct intel_gvt_device_info *info = &gvt->device_info; 247 void *mmio = gvt->firmware.mmio; 248 249 if (dmlr) { 250 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size); 251 252 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; 253 254 /* set the bit 0:2(Core C-State ) to C0 */ 255 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; 256 257 /* uc reset hw expect GS_MIA_IN_RESET */ 258 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 259 260 if (IS_BROXTON(vgpu->gvt->gt->i915)) { 261 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= 262 ~(BIT(0) | BIT(1)); 263 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 264 ~PHY_POWER_GOOD; 265 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 266 ~PHY_POWER_GOOD; 267 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= 268 ~BIT(30); 269 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= 270 ~BIT(30); 271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 272 ~BXT_PHY_LANE_ENABLED; 273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 274 BXT_PHY_CMNLANE_POWERDOWN_ACK | 275 BXT_PHY_LANE_POWERDOWN_ACK; 276 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 277 ~BXT_PHY_LANE_ENABLED; 278 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 279 BXT_PHY_CMNLANE_POWERDOWN_ACK | 280 BXT_PHY_LANE_POWERDOWN_ACK; 281 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 282 ~BXT_PHY_LANE_ENABLED; 283 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 284 BXT_PHY_CMNLANE_POWERDOWN_ACK | 285 BXT_PHY_LANE_POWERDOWN_ACK; 286 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 287 SKL_FUSE_DOWNLOAD_STATUS | 288 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 289 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 290 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 291 } 292 } else { 293 #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200) 294 /* only reset the engine related, so starting with 0x44200 295 * interrupt include DE,display mmio related will not be 296 * touched 297 */ 298 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET); 299 } 300 301 } 302 303 /** 304 * intel_vgpu_init_mmio - init MMIO space 305 * @vgpu: a vGPU 306 * 307 * Returns: 308 * Zero on success, negative error code if failed 309 */ 310 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu) 311 { 312 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; 313 314 vgpu->mmio.vreg = vzalloc(info->mmio_size); 315 if (!vgpu->mmio.vreg) 316 return -ENOMEM; 317 318 intel_vgpu_reset_mmio(vgpu, true); 319 320 return 0; 321 } 322 323 /** 324 * intel_vgpu_clean_mmio - clean MMIO space 325 * @vgpu: a vGPU 326 * 327 */ 328 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu) 329 { 330 vfree(vgpu->mmio.vreg); 331 vgpu->mmio.vreg = NULL; 332 } 333