1 /* 2 * KVMGT - the implementation of Intel mediated pass-through framework for KVM 3 * 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Kevin Tian <kevin.tian@intel.com> 27 * Jike Song <jike.song@intel.com> 28 * Xiaoguang Chen <xiaoguang.chen@intel.com> 29 * Eddie Dong <eddie.dong@intel.com> 30 * 31 * Contributors: 32 * Niu Bing <bing.niu@intel.com> 33 * Zhi Wang <zhi.a.wang@intel.com> 34 */ 35 36 #include <linux/init.h> 37 #include <linux/mm.h> 38 #include <linux/kthread.h> 39 #include <linux/sched/mm.h> 40 #include <linux/types.h> 41 #include <linux/list.h> 42 #include <linux/rbtree.h> 43 #include <linux/spinlock.h> 44 #include <linux/eventfd.h> 45 #include <linux/mdev.h> 46 #include <linux/debugfs.h> 47 48 #include <linux/nospec.h> 49 50 #include <drm/drm_edid.h> 51 52 #include "i915_drv.h" 53 #include "intel_gvt.h" 54 #include "gvt.h" 55 56 MODULE_IMPORT_NS(DMA_BUF); 57 MODULE_IMPORT_NS(I915_GVT); 58 59 /* helper macros copied from vfio-pci */ 60 #define VFIO_PCI_OFFSET_SHIFT 40 61 #define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) 62 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) 63 #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) 64 65 #define EDID_BLOB_OFFSET (PAGE_SIZE/2) 66 67 #define OPREGION_SIGNATURE "IntelGraphicsMem" 68 69 struct vfio_region; 70 struct intel_vgpu_regops { 71 size_t (*rw)(struct intel_vgpu *vgpu, char *buf, 72 size_t count, loff_t *ppos, bool iswrite); 73 void (*release)(struct intel_vgpu *vgpu, 74 struct vfio_region *region); 75 }; 76 77 struct vfio_region { 78 u32 type; 79 u32 subtype; 80 size_t size; 81 u32 flags; 82 const struct intel_vgpu_regops *ops; 83 void *data; 84 }; 85 86 struct vfio_edid_region { 87 struct vfio_region_gfx_edid vfio_edid_regs; 88 void *edid_blob; 89 }; 90 91 struct kvmgt_pgfn { 92 gfn_t gfn; 93 struct hlist_node hnode; 94 }; 95 96 struct gvt_dma { 97 struct intel_vgpu *vgpu; 98 struct rb_node gfn_node; 99 struct rb_node dma_addr_node; 100 gfn_t gfn; 101 dma_addr_t dma_addr; 102 unsigned long size; 103 struct kref ref; 104 }; 105 106 #define vfio_dev_to_vgpu(vfio_dev) \ 107 container_of((vfio_dev), struct intel_vgpu, vfio_device) 108 109 static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 110 const u8 *val, int len, 111 struct kvm_page_track_notifier_node *node); 112 static void kvmgt_page_track_flush_slot(struct kvm *kvm, 113 struct kvm_memory_slot *slot, 114 struct kvm_page_track_notifier_node *node); 115 116 static ssize_t description_show(struct mdev_type *mtype, 117 struct mdev_type_attribute *attr, char *buf) 118 { 119 struct intel_vgpu_type *type = 120 container_of(mtype, struct intel_vgpu_type, type); 121 122 return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n" 123 "fence: %d\nresolution: %s\n" 124 "weight: %d\n", 125 BYTES_TO_MB(type->conf->low_mm), 126 BYTES_TO_MB(type->conf->high_mm), 127 type->conf->fence, vgpu_edid_str(type->conf->edid), 128 type->conf->weight); 129 } 130 131 static MDEV_TYPE_ATTR_RO(description); 132 133 static const struct attribute *gvt_type_attrs[] = { 134 &mdev_type_attr_description.attr, 135 NULL, 136 }; 137 138 static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 139 unsigned long size) 140 { 141 vfio_unpin_pages(&vgpu->vfio_device, gfn << PAGE_SHIFT, 142 DIV_ROUND_UP(size, PAGE_SIZE)); 143 } 144 145 /* Pin a normal or compound guest page for dma. */ 146 static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 147 unsigned long size, struct page **page) 148 { 149 int total_pages = DIV_ROUND_UP(size, PAGE_SIZE); 150 struct page *base_page = NULL; 151 int npage; 152 int ret; 153 154 /* 155 * We pin the pages one-by-one to avoid allocating a big arrary 156 * on stack to hold pfns. 157 */ 158 for (npage = 0; npage < total_pages; npage++) { 159 dma_addr_t cur_iova = (gfn + npage) << PAGE_SHIFT; 160 struct page *cur_page; 161 162 ret = vfio_pin_pages(&vgpu->vfio_device, cur_iova, 1, 163 IOMMU_READ | IOMMU_WRITE, &cur_page); 164 if (ret != 1) { 165 gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n", 166 &cur_iova, ret); 167 goto err; 168 } 169 170 if (npage == 0) 171 base_page = cur_page; 172 else if (base_page + npage != cur_page) { 173 gvt_vgpu_err("The pages are not continuous\n"); 174 ret = -EINVAL; 175 npage++; 176 goto err; 177 } 178 } 179 180 *page = base_page; 181 return 0; 182 err: 183 gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); 184 return ret; 185 } 186 187 static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, 188 dma_addr_t *dma_addr, unsigned long size) 189 { 190 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 191 struct page *page = NULL; 192 int ret; 193 194 ret = gvt_pin_guest_page(vgpu, gfn, size, &page); 195 if (ret) 196 return ret; 197 198 /* Setup DMA mapping. */ 199 *dma_addr = dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); 200 if (dma_mapping_error(dev, *dma_addr)) { 201 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", 202 page_to_pfn(page), ret); 203 gvt_unpin_guest_page(vgpu, gfn, size); 204 return -ENOMEM; 205 } 206 207 return 0; 208 } 209 210 static void gvt_dma_unmap_page(struct intel_vgpu *vgpu, unsigned long gfn, 211 dma_addr_t dma_addr, unsigned long size) 212 { 213 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 214 215 dma_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL); 216 gvt_unpin_guest_page(vgpu, gfn, size); 217 } 218 219 static struct gvt_dma *__gvt_cache_find_dma_addr(struct intel_vgpu *vgpu, 220 dma_addr_t dma_addr) 221 { 222 struct rb_node *node = vgpu->dma_addr_cache.rb_node; 223 struct gvt_dma *itr; 224 225 while (node) { 226 itr = rb_entry(node, struct gvt_dma, dma_addr_node); 227 228 if (dma_addr < itr->dma_addr) 229 node = node->rb_left; 230 else if (dma_addr > itr->dma_addr) 231 node = node->rb_right; 232 else 233 return itr; 234 } 235 return NULL; 236 } 237 238 static struct gvt_dma *__gvt_cache_find_gfn(struct intel_vgpu *vgpu, gfn_t gfn) 239 { 240 struct rb_node *node = vgpu->gfn_cache.rb_node; 241 struct gvt_dma *itr; 242 243 while (node) { 244 itr = rb_entry(node, struct gvt_dma, gfn_node); 245 246 if (gfn < itr->gfn) 247 node = node->rb_left; 248 else if (gfn > itr->gfn) 249 node = node->rb_right; 250 else 251 return itr; 252 } 253 return NULL; 254 } 255 256 static int __gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, 257 dma_addr_t dma_addr, unsigned long size) 258 { 259 struct gvt_dma *new, *itr; 260 struct rb_node **link, *parent = NULL; 261 262 new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); 263 if (!new) 264 return -ENOMEM; 265 266 new->vgpu = vgpu; 267 new->gfn = gfn; 268 new->dma_addr = dma_addr; 269 new->size = size; 270 kref_init(&new->ref); 271 272 /* gfn_cache maps gfn to struct gvt_dma. */ 273 link = &vgpu->gfn_cache.rb_node; 274 while (*link) { 275 parent = *link; 276 itr = rb_entry(parent, struct gvt_dma, gfn_node); 277 278 if (gfn < itr->gfn) 279 link = &parent->rb_left; 280 else 281 link = &parent->rb_right; 282 } 283 rb_link_node(&new->gfn_node, parent, link); 284 rb_insert_color(&new->gfn_node, &vgpu->gfn_cache); 285 286 /* dma_addr_cache maps dma addr to struct gvt_dma. */ 287 parent = NULL; 288 link = &vgpu->dma_addr_cache.rb_node; 289 while (*link) { 290 parent = *link; 291 itr = rb_entry(parent, struct gvt_dma, dma_addr_node); 292 293 if (dma_addr < itr->dma_addr) 294 link = &parent->rb_left; 295 else 296 link = &parent->rb_right; 297 } 298 rb_link_node(&new->dma_addr_node, parent, link); 299 rb_insert_color(&new->dma_addr_node, &vgpu->dma_addr_cache); 300 301 vgpu->nr_cache_entries++; 302 return 0; 303 } 304 305 static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, 306 struct gvt_dma *entry) 307 { 308 rb_erase(&entry->gfn_node, &vgpu->gfn_cache); 309 rb_erase(&entry->dma_addr_node, &vgpu->dma_addr_cache); 310 kfree(entry); 311 vgpu->nr_cache_entries--; 312 } 313 314 static void gvt_cache_destroy(struct intel_vgpu *vgpu) 315 { 316 struct gvt_dma *dma; 317 struct rb_node *node = NULL; 318 319 for (;;) { 320 mutex_lock(&vgpu->cache_lock); 321 node = rb_first(&vgpu->gfn_cache); 322 if (!node) { 323 mutex_unlock(&vgpu->cache_lock); 324 break; 325 } 326 dma = rb_entry(node, struct gvt_dma, gfn_node); 327 gvt_dma_unmap_page(vgpu, dma->gfn, dma->dma_addr, dma->size); 328 __gvt_cache_remove_entry(vgpu, dma); 329 mutex_unlock(&vgpu->cache_lock); 330 } 331 } 332 333 static void gvt_cache_init(struct intel_vgpu *vgpu) 334 { 335 vgpu->gfn_cache = RB_ROOT; 336 vgpu->dma_addr_cache = RB_ROOT; 337 vgpu->nr_cache_entries = 0; 338 mutex_init(&vgpu->cache_lock); 339 } 340 341 static void kvmgt_protect_table_init(struct intel_vgpu *info) 342 { 343 hash_init(info->ptable); 344 } 345 346 static void kvmgt_protect_table_destroy(struct intel_vgpu *info) 347 { 348 struct kvmgt_pgfn *p; 349 struct hlist_node *tmp; 350 int i; 351 352 hash_for_each_safe(info->ptable, i, tmp, p, hnode) { 353 hash_del(&p->hnode); 354 kfree(p); 355 } 356 } 357 358 static struct kvmgt_pgfn * 359 __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) 360 { 361 struct kvmgt_pgfn *p, *res = NULL; 362 363 hash_for_each_possible(info->ptable, p, hnode, gfn) { 364 if (gfn == p->gfn) { 365 res = p; 366 break; 367 } 368 } 369 370 return res; 371 } 372 373 static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn) 374 { 375 struct kvmgt_pgfn *p; 376 377 p = __kvmgt_protect_table_find(info, gfn); 378 return !!p; 379 } 380 381 static void kvmgt_protect_table_add(struct intel_vgpu *info, gfn_t gfn) 382 { 383 struct kvmgt_pgfn *p; 384 385 if (kvmgt_gfn_is_write_protected(info, gfn)) 386 return; 387 388 p = kzalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); 389 if (WARN(!p, "gfn: 0x%llx\n", gfn)) 390 return; 391 392 p->gfn = gfn; 393 hash_add(info->ptable, &p->hnode, gfn); 394 } 395 396 static void kvmgt_protect_table_del(struct intel_vgpu *info, gfn_t gfn) 397 { 398 struct kvmgt_pgfn *p; 399 400 p = __kvmgt_protect_table_find(info, gfn); 401 if (p) { 402 hash_del(&p->hnode); 403 kfree(p); 404 } 405 } 406 407 static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, 408 size_t count, loff_t *ppos, bool iswrite) 409 { 410 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 411 VFIO_PCI_NUM_REGIONS; 412 void *base = vgpu->region[i].data; 413 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 414 415 416 if (pos >= vgpu->region[i].size || iswrite) { 417 gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); 418 return -EINVAL; 419 } 420 count = min(count, (size_t)(vgpu->region[i].size - pos)); 421 memcpy(buf, base + pos, count); 422 423 return count; 424 } 425 426 static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, 427 struct vfio_region *region) 428 { 429 } 430 431 static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { 432 .rw = intel_vgpu_reg_rw_opregion, 433 .release = intel_vgpu_reg_release_opregion, 434 }; 435 436 static int handle_edid_regs(struct intel_vgpu *vgpu, 437 struct vfio_edid_region *region, char *buf, 438 size_t count, u16 offset, bool is_write) 439 { 440 struct vfio_region_gfx_edid *regs = ®ion->vfio_edid_regs; 441 unsigned int data; 442 443 if (offset + count > sizeof(*regs)) 444 return -EINVAL; 445 446 if (count != 4) 447 return -EINVAL; 448 449 if (is_write) { 450 data = *((unsigned int *)buf); 451 switch (offset) { 452 case offsetof(struct vfio_region_gfx_edid, link_state): 453 if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) { 454 if (!drm_edid_block_valid( 455 (u8 *)region->edid_blob, 456 0, 457 true, 458 NULL)) { 459 gvt_vgpu_err("invalid EDID blob\n"); 460 return -EINVAL; 461 } 462 intel_vgpu_emulate_hotplug(vgpu, true); 463 } else if (data == VFIO_DEVICE_GFX_LINK_STATE_DOWN) 464 intel_vgpu_emulate_hotplug(vgpu, false); 465 else { 466 gvt_vgpu_err("invalid EDID link state %d\n", 467 regs->link_state); 468 return -EINVAL; 469 } 470 regs->link_state = data; 471 break; 472 case offsetof(struct vfio_region_gfx_edid, edid_size): 473 if (data > regs->edid_max_size) { 474 gvt_vgpu_err("EDID size is bigger than %d!\n", 475 regs->edid_max_size); 476 return -EINVAL; 477 } 478 regs->edid_size = data; 479 break; 480 default: 481 /* read-only regs */ 482 gvt_vgpu_err("write read-only EDID region at offset %d\n", 483 offset); 484 return -EPERM; 485 } 486 } else { 487 memcpy(buf, (char *)regs + offset, count); 488 } 489 490 return count; 491 } 492 493 static int handle_edid_blob(struct vfio_edid_region *region, char *buf, 494 size_t count, u16 offset, bool is_write) 495 { 496 if (offset + count > region->vfio_edid_regs.edid_size) 497 return -EINVAL; 498 499 if (is_write) 500 memcpy(region->edid_blob + offset, buf, count); 501 else 502 memcpy(buf, region->edid_blob + offset, count); 503 504 return count; 505 } 506 507 static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, 508 size_t count, loff_t *ppos, bool iswrite) 509 { 510 int ret; 511 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 512 VFIO_PCI_NUM_REGIONS; 513 struct vfio_edid_region *region = vgpu->region[i].data; 514 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 515 516 if (pos < region->vfio_edid_regs.edid_offset) { 517 ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); 518 } else { 519 pos -= EDID_BLOB_OFFSET; 520 ret = handle_edid_blob(region, buf, count, pos, iswrite); 521 } 522 523 if (ret < 0) 524 gvt_vgpu_err("failed to access EDID region\n"); 525 526 return ret; 527 } 528 529 static void intel_vgpu_reg_release_edid(struct intel_vgpu *vgpu, 530 struct vfio_region *region) 531 { 532 kfree(region->data); 533 } 534 535 static const struct intel_vgpu_regops intel_vgpu_regops_edid = { 536 .rw = intel_vgpu_reg_rw_edid, 537 .release = intel_vgpu_reg_release_edid, 538 }; 539 540 static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, 541 unsigned int type, unsigned int subtype, 542 const struct intel_vgpu_regops *ops, 543 size_t size, u32 flags, void *data) 544 { 545 struct vfio_region *region; 546 547 region = krealloc(vgpu->region, 548 (vgpu->num_regions + 1) * sizeof(*region), 549 GFP_KERNEL); 550 if (!region) 551 return -ENOMEM; 552 553 vgpu->region = region; 554 vgpu->region[vgpu->num_regions].type = type; 555 vgpu->region[vgpu->num_regions].subtype = subtype; 556 vgpu->region[vgpu->num_regions].ops = ops; 557 vgpu->region[vgpu->num_regions].size = size; 558 vgpu->region[vgpu->num_regions].flags = flags; 559 vgpu->region[vgpu->num_regions].data = data; 560 vgpu->num_regions++; 561 return 0; 562 } 563 564 int intel_gvt_set_opregion(struct intel_vgpu *vgpu) 565 { 566 void *base; 567 int ret; 568 569 /* Each vgpu has its own opregion, although VFIO would create another 570 * one later. This one is used to expose opregion to VFIO. And the 571 * other one created by VFIO later, is used by guest actually. 572 */ 573 base = vgpu_opregion(vgpu)->va; 574 if (!base) 575 return -ENOMEM; 576 577 if (memcmp(base, OPREGION_SIGNATURE, 16)) { 578 memunmap(base); 579 return -EINVAL; 580 } 581 582 ret = intel_vgpu_register_reg(vgpu, 583 PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, 584 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, 585 &intel_vgpu_regops_opregion, OPREGION_SIZE, 586 VFIO_REGION_INFO_FLAG_READ, base); 587 588 return ret; 589 } 590 591 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num) 592 { 593 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 594 struct vfio_edid_region *base; 595 int ret; 596 597 base = kzalloc(sizeof(*base), GFP_KERNEL); 598 if (!base) 599 return -ENOMEM; 600 601 /* TODO: Add multi-port and EDID extension block support */ 602 base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; 603 base->vfio_edid_regs.edid_max_size = EDID_SIZE; 604 base->vfio_edid_regs.edid_size = EDID_SIZE; 605 base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); 606 base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); 607 base->edid_blob = port->edid->edid_block; 608 609 ret = intel_vgpu_register_reg(vgpu, 610 VFIO_REGION_TYPE_GFX, 611 VFIO_REGION_SUBTYPE_GFX_EDID, 612 &intel_vgpu_regops_edid, EDID_SIZE, 613 VFIO_REGION_INFO_FLAG_READ | 614 VFIO_REGION_INFO_FLAG_WRITE | 615 VFIO_REGION_INFO_FLAG_CAPS, base); 616 617 return ret; 618 } 619 620 static void intel_vgpu_dma_unmap(struct vfio_device *vfio_dev, u64 iova, 621 u64 length) 622 { 623 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 624 struct gvt_dma *entry; 625 u64 iov_pfn = iova >> PAGE_SHIFT; 626 u64 end_iov_pfn = iov_pfn + length / PAGE_SIZE; 627 628 mutex_lock(&vgpu->cache_lock); 629 for (; iov_pfn < end_iov_pfn; iov_pfn++) { 630 entry = __gvt_cache_find_gfn(vgpu, iov_pfn); 631 if (!entry) 632 continue; 633 634 gvt_dma_unmap_page(vgpu, entry->gfn, entry->dma_addr, 635 entry->size); 636 __gvt_cache_remove_entry(vgpu, entry); 637 } 638 mutex_unlock(&vgpu->cache_lock); 639 } 640 641 static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu) 642 { 643 struct intel_vgpu *itr; 644 int id; 645 bool ret = false; 646 647 mutex_lock(&vgpu->gvt->lock); 648 for_each_active_vgpu(vgpu->gvt, itr, id) { 649 if (!itr->attached) 650 continue; 651 652 if (vgpu->vfio_device.kvm == itr->vfio_device.kvm) { 653 ret = true; 654 goto out; 655 } 656 } 657 out: 658 mutex_unlock(&vgpu->gvt->lock); 659 return ret; 660 } 661 662 static int intel_vgpu_open_device(struct vfio_device *vfio_dev) 663 { 664 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 665 666 if (vgpu->attached) 667 return -EEXIST; 668 669 if (!vgpu->vfio_device.kvm || 670 vgpu->vfio_device.kvm->mm != current->mm) { 671 gvt_vgpu_err("KVM is required to use Intel vGPU\n"); 672 return -ESRCH; 673 } 674 675 kvm_get_kvm(vgpu->vfio_device.kvm); 676 677 if (__kvmgt_vgpu_exist(vgpu)) 678 return -EEXIST; 679 680 vgpu->attached = true; 681 682 kvmgt_protect_table_init(vgpu); 683 gvt_cache_init(vgpu); 684 685 vgpu->track_node.track_write = kvmgt_page_track_write; 686 vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot; 687 kvm_page_track_register_notifier(vgpu->vfio_device.kvm, 688 &vgpu->track_node); 689 690 debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs, 691 &vgpu->nr_cache_entries); 692 693 intel_gvt_activate_vgpu(vgpu); 694 695 atomic_set(&vgpu->released, 0); 696 return 0; 697 } 698 699 static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu) 700 { 701 struct eventfd_ctx *trigger; 702 703 trigger = vgpu->msi_trigger; 704 if (trigger) { 705 eventfd_ctx_put(trigger); 706 vgpu->msi_trigger = NULL; 707 } 708 } 709 710 static void intel_vgpu_close_device(struct vfio_device *vfio_dev) 711 { 712 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 713 714 if (!vgpu->attached) 715 return; 716 717 if (atomic_cmpxchg(&vgpu->released, 0, 1)) 718 return; 719 720 intel_gvt_release_vgpu(vgpu); 721 722 debugfs_remove(debugfs_lookup(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs)); 723 724 kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm, 725 &vgpu->track_node); 726 kvmgt_protect_table_destroy(vgpu); 727 gvt_cache_destroy(vgpu); 728 729 intel_vgpu_release_msi_eventfd_ctx(vgpu); 730 731 vgpu->attached = false; 732 733 if (vgpu->vfio_device.kvm) 734 kvm_put_kvm(vgpu->vfio_device.kvm); 735 } 736 737 static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar) 738 { 739 u32 start_lo, start_hi; 740 u32 mem_type; 741 742 start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 743 PCI_BASE_ADDRESS_MEM_MASK; 744 mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 745 PCI_BASE_ADDRESS_MEM_TYPE_MASK; 746 747 switch (mem_type) { 748 case PCI_BASE_ADDRESS_MEM_TYPE_64: 749 start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space 750 + bar + 4)); 751 break; 752 case PCI_BASE_ADDRESS_MEM_TYPE_32: 753 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 754 /* 1M mem BAR treated as 32-bit BAR */ 755 default: 756 /* mem unknown type treated as 32-bit BAR */ 757 start_hi = 0; 758 break; 759 } 760 761 return ((u64)start_hi << 32) | start_lo; 762 } 763 764 static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off, 765 void *buf, unsigned int count, bool is_write) 766 { 767 u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar); 768 int ret; 769 770 if (is_write) 771 ret = intel_vgpu_emulate_mmio_write(vgpu, 772 bar_start + off, buf, count); 773 else 774 ret = intel_vgpu_emulate_mmio_read(vgpu, 775 bar_start + off, buf, count); 776 return ret; 777 } 778 779 static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) 780 { 781 return off >= vgpu_aperture_offset(vgpu) && 782 off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); 783 } 784 785 static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, 786 void *buf, unsigned long count, bool is_write) 787 { 788 void __iomem *aperture_va; 789 790 if (!intel_vgpu_in_aperture(vgpu, off) || 791 !intel_vgpu_in_aperture(vgpu, off + count)) { 792 gvt_vgpu_err("Invalid aperture offset %llu\n", off); 793 return -EINVAL; 794 } 795 796 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, 797 ALIGN_DOWN(off, PAGE_SIZE), 798 count + offset_in_page(off)); 799 if (!aperture_va) 800 return -EIO; 801 802 if (is_write) 803 memcpy_toio(aperture_va + offset_in_page(off), buf, count); 804 else 805 memcpy_fromio(buf, aperture_va + offset_in_page(off), count); 806 807 io_mapping_unmap(aperture_va); 808 809 return 0; 810 } 811 812 static ssize_t intel_vgpu_rw(struct intel_vgpu *vgpu, char *buf, 813 size_t count, loff_t *ppos, bool is_write) 814 { 815 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 816 u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; 817 int ret = -EINVAL; 818 819 820 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) { 821 gvt_vgpu_err("invalid index: %u\n", index); 822 return -EINVAL; 823 } 824 825 switch (index) { 826 case VFIO_PCI_CONFIG_REGION_INDEX: 827 if (is_write) 828 ret = intel_vgpu_emulate_cfg_write(vgpu, pos, 829 buf, count); 830 else 831 ret = intel_vgpu_emulate_cfg_read(vgpu, pos, 832 buf, count); 833 break; 834 case VFIO_PCI_BAR0_REGION_INDEX: 835 ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos, 836 buf, count, is_write); 837 break; 838 case VFIO_PCI_BAR2_REGION_INDEX: 839 ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write); 840 break; 841 case VFIO_PCI_BAR1_REGION_INDEX: 842 case VFIO_PCI_BAR3_REGION_INDEX: 843 case VFIO_PCI_BAR4_REGION_INDEX: 844 case VFIO_PCI_BAR5_REGION_INDEX: 845 case VFIO_PCI_VGA_REGION_INDEX: 846 case VFIO_PCI_ROM_REGION_INDEX: 847 break; 848 default: 849 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) 850 return -EINVAL; 851 852 index -= VFIO_PCI_NUM_REGIONS; 853 return vgpu->region[index].ops->rw(vgpu, buf, count, 854 ppos, is_write); 855 } 856 857 return ret == 0 ? count : ret; 858 } 859 860 static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos) 861 { 862 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 863 struct intel_gvt *gvt = vgpu->gvt; 864 int offset; 865 866 /* Only allow MMIO GGTT entry access */ 867 if (index != PCI_BASE_ADDRESS_0) 868 return false; 869 870 offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - 871 intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 872 873 return (offset >= gvt->device_info.gtt_start_offset && 874 offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? 875 true : false; 876 } 877 878 static ssize_t intel_vgpu_read(struct vfio_device *vfio_dev, char __user *buf, 879 size_t count, loff_t *ppos) 880 { 881 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 882 unsigned int done = 0; 883 int ret; 884 885 while (count) { 886 size_t filled; 887 888 /* Only support GGTT entry 8 bytes read */ 889 if (count >= 8 && !(*ppos % 8) && 890 gtt_entry(vgpu, ppos)) { 891 u64 val; 892 893 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 894 ppos, false); 895 if (ret <= 0) 896 goto read_err; 897 898 if (copy_to_user(buf, &val, sizeof(val))) 899 goto read_err; 900 901 filled = 8; 902 } else if (count >= 4 && !(*ppos % 4)) { 903 u32 val; 904 905 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 906 ppos, false); 907 if (ret <= 0) 908 goto read_err; 909 910 if (copy_to_user(buf, &val, sizeof(val))) 911 goto read_err; 912 913 filled = 4; 914 } else if (count >= 2 && !(*ppos % 2)) { 915 u16 val; 916 917 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 918 ppos, false); 919 if (ret <= 0) 920 goto read_err; 921 922 if (copy_to_user(buf, &val, sizeof(val))) 923 goto read_err; 924 925 filled = 2; 926 } else { 927 u8 val; 928 929 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos, 930 false); 931 if (ret <= 0) 932 goto read_err; 933 934 if (copy_to_user(buf, &val, sizeof(val))) 935 goto read_err; 936 937 filled = 1; 938 } 939 940 count -= filled; 941 done += filled; 942 *ppos += filled; 943 buf += filled; 944 } 945 946 return done; 947 948 read_err: 949 return -EFAULT; 950 } 951 952 static ssize_t intel_vgpu_write(struct vfio_device *vfio_dev, 953 const char __user *buf, 954 size_t count, loff_t *ppos) 955 { 956 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 957 unsigned int done = 0; 958 int ret; 959 960 while (count) { 961 size_t filled; 962 963 /* Only support GGTT entry 8 bytes write */ 964 if (count >= 8 && !(*ppos % 8) && 965 gtt_entry(vgpu, ppos)) { 966 u64 val; 967 968 if (copy_from_user(&val, buf, sizeof(val))) 969 goto write_err; 970 971 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 972 ppos, true); 973 if (ret <= 0) 974 goto write_err; 975 976 filled = 8; 977 } else if (count >= 4 && !(*ppos % 4)) { 978 u32 val; 979 980 if (copy_from_user(&val, buf, sizeof(val))) 981 goto write_err; 982 983 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 984 ppos, true); 985 if (ret <= 0) 986 goto write_err; 987 988 filled = 4; 989 } else if (count >= 2 && !(*ppos % 2)) { 990 u16 val; 991 992 if (copy_from_user(&val, buf, sizeof(val))) 993 goto write_err; 994 995 ret = intel_vgpu_rw(vgpu, (char *)&val, 996 sizeof(val), ppos, true); 997 if (ret <= 0) 998 goto write_err; 999 1000 filled = 2; 1001 } else { 1002 u8 val; 1003 1004 if (copy_from_user(&val, buf, sizeof(val))) 1005 goto write_err; 1006 1007 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), 1008 ppos, true); 1009 if (ret <= 0) 1010 goto write_err; 1011 1012 filled = 1; 1013 } 1014 1015 count -= filled; 1016 done += filled; 1017 *ppos += filled; 1018 buf += filled; 1019 } 1020 1021 return done; 1022 write_err: 1023 return -EFAULT; 1024 } 1025 1026 static int intel_vgpu_mmap(struct vfio_device *vfio_dev, 1027 struct vm_area_struct *vma) 1028 { 1029 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1030 unsigned int index; 1031 u64 virtaddr; 1032 unsigned long req_size, pgoff, req_start; 1033 pgprot_t pg_prot; 1034 1035 index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); 1036 if (index >= VFIO_PCI_ROM_REGION_INDEX) 1037 return -EINVAL; 1038 1039 if (vma->vm_end < vma->vm_start) 1040 return -EINVAL; 1041 if ((vma->vm_flags & VM_SHARED) == 0) 1042 return -EINVAL; 1043 if (index != VFIO_PCI_BAR2_REGION_INDEX) 1044 return -EINVAL; 1045 1046 pg_prot = vma->vm_page_prot; 1047 virtaddr = vma->vm_start; 1048 req_size = vma->vm_end - vma->vm_start; 1049 pgoff = vma->vm_pgoff & 1050 ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); 1051 req_start = pgoff << PAGE_SHIFT; 1052 1053 if (!intel_vgpu_in_aperture(vgpu, req_start)) 1054 return -EINVAL; 1055 if (req_start + req_size > 1056 vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) 1057 return -EINVAL; 1058 1059 pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; 1060 1061 return remap_pfn_range(vma, virtaddr, pgoff, req_size, pg_prot); 1062 } 1063 1064 static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) 1065 { 1066 if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) 1067 return 1; 1068 1069 return 0; 1070 } 1071 1072 static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu, 1073 unsigned int index, unsigned int start, 1074 unsigned int count, u32 flags, 1075 void *data) 1076 { 1077 return 0; 1078 } 1079 1080 static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu, 1081 unsigned int index, unsigned int start, 1082 unsigned int count, u32 flags, void *data) 1083 { 1084 return 0; 1085 } 1086 1087 static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu, 1088 unsigned int index, unsigned int start, unsigned int count, 1089 u32 flags, void *data) 1090 { 1091 return 0; 1092 } 1093 1094 static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, 1095 unsigned int index, unsigned int start, unsigned int count, 1096 u32 flags, void *data) 1097 { 1098 struct eventfd_ctx *trigger; 1099 1100 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { 1101 int fd = *(int *)data; 1102 1103 trigger = eventfd_ctx_fdget(fd); 1104 if (IS_ERR(trigger)) { 1105 gvt_vgpu_err("eventfd_ctx_fdget failed\n"); 1106 return PTR_ERR(trigger); 1107 } 1108 vgpu->msi_trigger = trigger; 1109 } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) 1110 intel_vgpu_release_msi_eventfd_ctx(vgpu); 1111 1112 return 0; 1113 } 1114 1115 static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, 1116 unsigned int index, unsigned int start, unsigned int count, 1117 void *data) 1118 { 1119 int (*func)(struct intel_vgpu *vgpu, unsigned int index, 1120 unsigned int start, unsigned int count, u32 flags, 1121 void *data) = NULL; 1122 1123 switch (index) { 1124 case VFIO_PCI_INTX_IRQ_INDEX: 1125 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1126 case VFIO_IRQ_SET_ACTION_MASK: 1127 func = intel_vgpu_set_intx_mask; 1128 break; 1129 case VFIO_IRQ_SET_ACTION_UNMASK: 1130 func = intel_vgpu_set_intx_unmask; 1131 break; 1132 case VFIO_IRQ_SET_ACTION_TRIGGER: 1133 func = intel_vgpu_set_intx_trigger; 1134 break; 1135 } 1136 break; 1137 case VFIO_PCI_MSI_IRQ_INDEX: 1138 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1139 case VFIO_IRQ_SET_ACTION_MASK: 1140 case VFIO_IRQ_SET_ACTION_UNMASK: 1141 /* XXX Need masking support exported */ 1142 break; 1143 case VFIO_IRQ_SET_ACTION_TRIGGER: 1144 func = intel_vgpu_set_msi_trigger; 1145 break; 1146 } 1147 break; 1148 } 1149 1150 if (!func) 1151 return -ENOTTY; 1152 1153 return func(vgpu, index, start, count, flags, data); 1154 } 1155 1156 static long intel_vgpu_ioctl(struct vfio_device *vfio_dev, unsigned int cmd, 1157 unsigned long arg) 1158 { 1159 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1160 unsigned long minsz; 1161 1162 gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); 1163 1164 if (cmd == VFIO_DEVICE_GET_INFO) { 1165 struct vfio_device_info info; 1166 1167 minsz = offsetofend(struct vfio_device_info, num_irqs); 1168 1169 if (copy_from_user(&info, (void __user *)arg, minsz)) 1170 return -EFAULT; 1171 1172 if (info.argsz < minsz) 1173 return -EINVAL; 1174 1175 info.flags = VFIO_DEVICE_FLAGS_PCI; 1176 info.flags |= VFIO_DEVICE_FLAGS_RESET; 1177 info.num_regions = VFIO_PCI_NUM_REGIONS + 1178 vgpu->num_regions; 1179 info.num_irqs = VFIO_PCI_NUM_IRQS; 1180 1181 return copy_to_user((void __user *)arg, &info, minsz) ? 1182 -EFAULT : 0; 1183 1184 } else if (cmd == VFIO_DEVICE_GET_REGION_INFO) { 1185 struct vfio_region_info info; 1186 struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; 1187 unsigned int i; 1188 int ret; 1189 struct vfio_region_info_cap_sparse_mmap *sparse = NULL; 1190 int nr_areas = 1; 1191 int cap_type_id; 1192 1193 minsz = offsetofend(struct vfio_region_info, offset); 1194 1195 if (copy_from_user(&info, (void __user *)arg, minsz)) 1196 return -EFAULT; 1197 1198 if (info.argsz < minsz) 1199 return -EINVAL; 1200 1201 switch (info.index) { 1202 case VFIO_PCI_CONFIG_REGION_INDEX: 1203 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1204 info.size = vgpu->gvt->device_info.cfg_space_size; 1205 info.flags = VFIO_REGION_INFO_FLAG_READ | 1206 VFIO_REGION_INFO_FLAG_WRITE; 1207 break; 1208 case VFIO_PCI_BAR0_REGION_INDEX: 1209 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1210 info.size = vgpu->cfg_space.bar[info.index].size; 1211 if (!info.size) { 1212 info.flags = 0; 1213 break; 1214 } 1215 1216 info.flags = VFIO_REGION_INFO_FLAG_READ | 1217 VFIO_REGION_INFO_FLAG_WRITE; 1218 break; 1219 case VFIO_PCI_BAR1_REGION_INDEX: 1220 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1221 info.size = 0; 1222 info.flags = 0; 1223 break; 1224 case VFIO_PCI_BAR2_REGION_INDEX: 1225 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1226 info.flags = VFIO_REGION_INFO_FLAG_CAPS | 1227 VFIO_REGION_INFO_FLAG_MMAP | 1228 VFIO_REGION_INFO_FLAG_READ | 1229 VFIO_REGION_INFO_FLAG_WRITE; 1230 info.size = gvt_aperture_sz(vgpu->gvt); 1231 1232 sparse = kzalloc(struct_size(sparse, areas, nr_areas), 1233 GFP_KERNEL); 1234 if (!sparse) 1235 return -ENOMEM; 1236 1237 sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1238 sparse->header.version = 1; 1239 sparse->nr_areas = nr_areas; 1240 cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1241 sparse->areas[0].offset = 1242 PAGE_ALIGN(vgpu_aperture_offset(vgpu)); 1243 sparse->areas[0].size = vgpu_aperture_sz(vgpu); 1244 break; 1245 1246 case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: 1247 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1248 info.size = 0; 1249 info.flags = 0; 1250 1251 gvt_dbg_core("get region info bar:%d\n", info.index); 1252 break; 1253 1254 case VFIO_PCI_ROM_REGION_INDEX: 1255 case VFIO_PCI_VGA_REGION_INDEX: 1256 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1257 info.size = 0; 1258 info.flags = 0; 1259 1260 gvt_dbg_core("get region info index:%d\n", info.index); 1261 break; 1262 default: 1263 { 1264 struct vfio_region_info_cap_type cap_type = { 1265 .header.id = VFIO_REGION_INFO_CAP_TYPE, 1266 .header.version = 1 }; 1267 1268 if (info.index >= VFIO_PCI_NUM_REGIONS + 1269 vgpu->num_regions) 1270 return -EINVAL; 1271 info.index = 1272 array_index_nospec(info.index, 1273 VFIO_PCI_NUM_REGIONS + 1274 vgpu->num_regions); 1275 1276 i = info.index - VFIO_PCI_NUM_REGIONS; 1277 1278 info.offset = 1279 VFIO_PCI_INDEX_TO_OFFSET(info.index); 1280 info.size = vgpu->region[i].size; 1281 info.flags = vgpu->region[i].flags; 1282 1283 cap_type.type = vgpu->region[i].type; 1284 cap_type.subtype = vgpu->region[i].subtype; 1285 1286 ret = vfio_info_add_capability(&caps, 1287 &cap_type.header, 1288 sizeof(cap_type)); 1289 if (ret) 1290 return ret; 1291 } 1292 } 1293 1294 if ((info.flags & VFIO_REGION_INFO_FLAG_CAPS) && sparse) { 1295 switch (cap_type_id) { 1296 case VFIO_REGION_INFO_CAP_SPARSE_MMAP: 1297 ret = vfio_info_add_capability(&caps, 1298 &sparse->header, 1299 struct_size(sparse, areas, 1300 sparse->nr_areas)); 1301 if (ret) { 1302 kfree(sparse); 1303 return ret; 1304 } 1305 break; 1306 default: 1307 kfree(sparse); 1308 return -EINVAL; 1309 } 1310 } 1311 1312 if (caps.size) { 1313 info.flags |= VFIO_REGION_INFO_FLAG_CAPS; 1314 if (info.argsz < sizeof(info) + caps.size) { 1315 info.argsz = sizeof(info) + caps.size; 1316 info.cap_offset = 0; 1317 } else { 1318 vfio_info_cap_shift(&caps, sizeof(info)); 1319 if (copy_to_user((void __user *)arg + 1320 sizeof(info), caps.buf, 1321 caps.size)) { 1322 kfree(caps.buf); 1323 kfree(sparse); 1324 return -EFAULT; 1325 } 1326 info.cap_offset = sizeof(info); 1327 } 1328 1329 kfree(caps.buf); 1330 } 1331 1332 kfree(sparse); 1333 return copy_to_user((void __user *)arg, &info, minsz) ? 1334 -EFAULT : 0; 1335 } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { 1336 struct vfio_irq_info info; 1337 1338 minsz = offsetofend(struct vfio_irq_info, count); 1339 1340 if (copy_from_user(&info, (void __user *)arg, minsz)) 1341 return -EFAULT; 1342 1343 if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) 1344 return -EINVAL; 1345 1346 switch (info.index) { 1347 case VFIO_PCI_INTX_IRQ_INDEX: 1348 case VFIO_PCI_MSI_IRQ_INDEX: 1349 break; 1350 default: 1351 return -EINVAL; 1352 } 1353 1354 info.flags = VFIO_IRQ_INFO_EVENTFD; 1355 1356 info.count = intel_vgpu_get_irq_count(vgpu, info.index); 1357 1358 if (info.index == VFIO_PCI_INTX_IRQ_INDEX) 1359 info.flags |= (VFIO_IRQ_INFO_MASKABLE | 1360 VFIO_IRQ_INFO_AUTOMASKED); 1361 else 1362 info.flags |= VFIO_IRQ_INFO_NORESIZE; 1363 1364 return copy_to_user((void __user *)arg, &info, minsz) ? 1365 -EFAULT : 0; 1366 } else if (cmd == VFIO_DEVICE_SET_IRQS) { 1367 struct vfio_irq_set hdr; 1368 u8 *data = NULL; 1369 int ret = 0; 1370 size_t data_size = 0; 1371 1372 minsz = offsetofend(struct vfio_irq_set, count); 1373 1374 if (copy_from_user(&hdr, (void __user *)arg, minsz)) 1375 return -EFAULT; 1376 1377 if (!(hdr.flags & VFIO_IRQ_SET_DATA_NONE)) { 1378 int max = intel_vgpu_get_irq_count(vgpu, hdr.index); 1379 1380 ret = vfio_set_irqs_validate_and_prepare(&hdr, max, 1381 VFIO_PCI_NUM_IRQS, &data_size); 1382 if (ret) { 1383 gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); 1384 return -EINVAL; 1385 } 1386 if (data_size) { 1387 data = memdup_user((void __user *)(arg + minsz), 1388 data_size); 1389 if (IS_ERR(data)) 1390 return PTR_ERR(data); 1391 } 1392 } 1393 1394 ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index, 1395 hdr.start, hdr.count, data); 1396 kfree(data); 1397 1398 return ret; 1399 } else if (cmd == VFIO_DEVICE_RESET) { 1400 intel_gvt_reset_vgpu(vgpu); 1401 return 0; 1402 } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { 1403 struct vfio_device_gfx_plane_info dmabuf; 1404 int ret = 0; 1405 1406 minsz = offsetofend(struct vfio_device_gfx_plane_info, 1407 dmabuf_id); 1408 if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) 1409 return -EFAULT; 1410 if (dmabuf.argsz < minsz) 1411 return -EINVAL; 1412 1413 ret = intel_vgpu_query_plane(vgpu, &dmabuf); 1414 if (ret != 0) 1415 return ret; 1416 1417 return copy_to_user((void __user *)arg, &dmabuf, minsz) ? 1418 -EFAULT : 0; 1419 } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { 1420 __u32 dmabuf_id; 1421 1422 if (get_user(dmabuf_id, (__u32 __user *)arg)) 1423 return -EFAULT; 1424 return intel_vgpu_get_dmabuf(vgpu, dmabuf_id); 1425 } 1426 1427 return -ENOTTY; 1428 } 1429 1430 static ssize_t 1431 vgpu_id_show(struct device *dev, struct device_attribute *attr, 1432 char *buf) 1433 { 1434 struct intel_vgpu *vgpu = dev_get_drvdata(dev); 1435 1436 return sprintf(buf, "%d\n", vgpu->id); 1437 } 1438 1439 static DEVICE_ATTR_RO(vgpu_id); 1440 1441 static struct attribute *intel_vgpu_attrs[] = { 1442 &dev_attr_vgpu_id.attr, 1443 NULL 1444 }; 1445 1446 static const struct attribute_group intel_vgpu_group = { 1447 .name = "intel_vgpu", 1448 .attrs = intel_vgpu_attrs, 1449 }; 1450 1451 static const struct attribute_group *intel_vgpu_groups[] = { 1452 &intel_vgpu_group, 1453 NULL, 1454 }; 1455 1456 static int intel_vgpu_init_dev(struct vfio_device *vfio_dev) 1457 { 1458 struct mdev_device *mdev = to_mdev_device(vfio_dev->dev); 1459 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1460 struct intel_vgpu_type *type = 1461 container_of(mdev->type, struct intel_vgpu_type, type); 1462 1463 vgpu->gvt = kdev_to_i915(mdev->type->parent->dev)->gvt; 1464 return intel_gvt_create_vgpu(vgpu, type->conf); 1465 } 1466 1467 static void intel_vgpu_release_dev(struct vfio_device *vfio_dev) 1468 { 1469 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1470 1471 intel_gvt_destroy_vgpu(vgpu); 1472 vfio_free_device(vfio_dev); 1473 } 1474 1475 static const struct vfio_device_ops intel_vgpu_dev_ops = { 1476 .init = intel_vgpu_init_dev, 1477 .release = intel_vgpu_release_dev, 1478 .open_device = intel_vgpu_open_device, 1479 .close_device = intel_vgpu_close_device, 1480 .read = intel_vgpu_read, 1481 .write = intel_vgpu_write, 1482 .mmap = intel_vgpu_mmap, 1483 .ioctl = intel_vgpu_ioctl, 1484 .dma_unmap = intel_vgpu_dma_unmap, 1485 }; 1486 1487 static int intel_vgpu_probe(struct mdev_device *mdev) 1488 { 1489 struct intel_vgpu *vgpu; 1490 int ret; 1491 1492 vgpu = vfio_alloc_device(intel_vgpu, vfio_device, &mdev->dev, 1493 &intel_vgpu_dev_ops); 1494 if (IS_ERR(vgpu)) { 1495 gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu)); 1496 return PTR_ERR(vgpu); 1497 } 1498 1499 dev_set_drvdata(&mdev->dev, vgpu); 1500 ret = vfio_register_emulated_iommu_dev(&vgpu->vfio_device); 1501 if (ret) 1502 goto out_put_vdev; 1503 1504 gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", 1505 dev_name(mdev_dev(mdev))); 1506 return 0; 1507 1508 out_put_vdev: 1509 vfio_put_device(&vgpu->vfio_device); 1510 return ret; 1511 } 1512 1513 static void intel_vgpu_remove(struct mdev_device *mdev) 1514 { 1515 struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev); 1516 1517 if (WARN_ON_ONCE(vgpu->attached)) 1518 return; 1519 1520 vfio_unregister_group_dev(&vgpu->vfio_device); 1521 vfio_put_device(&vgpu->vfio_device); 1522 } 1523 1524 static unsigned int intel_vgpu_get_available(struct mdev_type *mtype) 1525 { 1526 struct intel_vgpu_type *type = 1527 container_of(mtype, struct intel_vgpu_type, type); 1528 struct intel_gvt *gvt = kdev_to_i915(mtype->parent->dev)->gvt; 1529 unsigned int low_gm_avail, high_gm_avail, fence_avail; 1530 1531 mutex_lock(&gvt->lock); 1532 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE - 1533 gvt->gm.vgpu_allocated_low_gm_size; 1534 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE - 1535 gvt->gm.vgpu_allocated_high_gm_size; 1536 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - 1537 gvt->fence.vgpu_allocated_fence_num; 1538 mutex_unlock(&gvt->lock); 1539 1540 return min3(low_gm_avail / type->conf->low_mm, 1541 high_gm_avail / type->conf->high_mm, 1542 fence_avail / type->conf->fence); 1543 } 1544 1545 static struct mdev_driver intel_vgpu_mdev_driver = { 1546 .device_api = VFIO_DEVICE_API_PCI_STRING, 1547 .driver = { 1548 .name = "intel_vgpu_mdev", 1549 .owner = THIS_MODULE, 1550 .dev_groups = intel_vgpu_groups, 1551 }, 1552 .probe = intel_vgpu_probe, 1553 .remove = intel_vgpu_remove, 1554 .get_available = intel_vgpu_get_available, 1555 .types_attrs = gvt_type_attrs, 1556 }; 1557 1558 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) 1559 { 1560 struct kvm *kvm = info->vfio_device.kvm; 1561 struct kvm_memory_slot *slot; 1562 int idx; 1563 1564 if (!info->attached) 1565 return -ESRCH; 1566 1567 idx = srcu_read_lock(&kvm->srcu); 1568 slot = gfn_to_memslot(kvm, gfn); 1569 if (!slot) { 1570 srcu_read_unlock(&kvm->srcu, idx); 1571 return -EINVAL; 1572 } 1573 1574 write_lock(&kvm->mmu_lock); 1575 1576 if (kvmgt_gfn_is_write_protected(info, gfn)) 1577 goto out; 1578 1579 kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); 1580 kvmgt_protect_table_add(info, gfn); 1581 1582 out: 1583 write_unlock(&kvm->mmu_lock); 1584 srcu_read_unlock(&kvm->srcu, idx); 1585 return 0; 1586 } 1587 1588 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) 1589 { 1590 struct kvm *kvm = info->vfio_device.kvm; 1591 struct kvm_memory_slot *slot; 1592 int idx; 1593 1594 if (!info->attached) 1595 return 0; 1596 1597 idx = srcu_read_lock(&kvm->srcu); 1598 slot = gfn_to_memslot(kvm, gfn); 1599 if (!slot) { 1600 srcu_read_unlock(&kvm->srcu, idx); 1601 return -EINVAL; 1602 } 1603 1604 write_lock(&kvm->mmu_lock); 1605 1606 if (!kvmgt_gfn_is_write_protected(info, gfn)) 1607 goto out; 1608 1609 kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); 1610 kvmgt_protect_table_del(info, gfn); 1611 1612 out: 1613 write_unlock(&kvm->mmu_lock); 1614 srcu_read_unlock(&kvm->srcu, idx); 1615 return 0; 1616 } 1617 1618 static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 1619 const u8 *val, int len, 1620 struct kvm_page_track_notifier_node *node) 1621 { 1622 struct intel_vgpu *info = 1623 container_of(node, struct intel_vgpu, track_node); 1624 1625 if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) 1626 intel_vgpu_page_track_handler(info, gpa, 1627 (void *)val, len); 1628 } 1629 1630 static void kvmgt_page_track_flush_slot(struct kvm *kvm, 1631 struct kvm_memory_slot *slot, 1632 struct kvm_page_track_notifier_node *node) 1633 { 1634 int i; 1635 gfn_t gfn; 1636 struct intel_vgpu *info = 1637 container_of(node, struct intel_vgpu, track_node); 1638 1639 write_lock(&kvm->mmu_lock); 1640 for (i = 0; i < slot->npages; i++) { 1641 gfn = slot->base_gfn + i; 1642 if (kvmgt_gfn_is_write_protected(info, gfn)) { 1643 kvm_slot_page_track_remove_page(kvm, slot, gfn, 1644 KVM_PAGE_TRACK_WRITE); 1645 kvmgt_protect_table_del(info, gfn); 1646 } 1647 } 1648 write_unlock(&kvm->mmu_lock); 1649 } 1650 1651 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) 1652 { 1653 int i; 1654 1655 if (!vgpu->region) 1656 return; 1657 1658 for (i = 0; i < vgpu->num_regions; i++) 1659 if (vgpu->region[i].ops->release) 1660 vgpu->region[i].ops->release(vgpu, 1661 &vgpu->region[i]); 1662 vgpu->num_regions = 0; 1663 kfree(vgpu->region); 1664 vgpu->region = NULL; 1665 } 1666 1667 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 1668 unsigned long size, dma_addr_t *dma_addr) 1669 { 1670 struct gvt_dma *entry; 1671 int ret; 1672 1673 if (!vgpu->attached) 1674 return -EINVAL; 1675 1676 mutex_lock(&vgpu->cache_lock); 1677 1678 entry = __gvt_cache_find_gfn(vgpu, gfn); 1679 if (!entry) { 1680 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1681 if (ret) 1682 goto err_unlock; 1683 1684 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1685 if (ret) 1686 goto err_unmap; 1687 } else if (entry->size != size) { 1688 /* the same gfn with different size: unmap and re-map */ 1689 gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); 1690 __gvt_cache_remove_entry(vgpu, entry); 1691 1692 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1693 if (ret) 1694 goto err_unlock; 1695 1696 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1697 if (ret) 1698 goto err_unmap; 1699 } else { 1700 kref_get(&entry->ref); 1701 *dma_addr = entry->dma_addr; 1702 } 1703 1704 mutex_unlock(&vgpu->cache_lock); 1705 return 0; 1706 1707 err_unmap: 1708 gvt_dma_unmap_page(vgpu, gfn, *dma_addr, size); 1709 err_unlock: 1710 mutex_unlock(&vgpu->cache_lock); 1711 return ret; 1712 } 1713 1714 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr) 1715 { 1716 struct gvt_dma *entry; 1717 int ret = 0; 1718 1719 if (!vgpu->attached) 1720 return -ENODEV; 1721 1722 mutex_lock(&vgpu->cache_lock); 1723 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1724 if (entry) 1725 kref_get(&entry->ref); 1726 else 1727 ret = -ENOMEM; 1728 mutex_unlock(&vgpu->cache_lock); 1729 1730 return ret; 1731 } 1732 1733 static void __gvt_dma_release(struct kref *ref) 1734 { 1735 struct gvt_dma *entry = container_of(ref, typeof(*entry), ref); 1736 1737 gvt_dma_unmap_page(entry->vgpu, entry->gfn, entry->dma_addr, 1738 entry->size); 1739 __gvt_cache_remove_entry(entry->vgpu, entry); 1740 } 1741 1742 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, 1743 dma_addr_t dma_addr) 1744 { 1745 struct gvt_dma *entry; 1746 1747 if (!vgpu->attached) 1748 return; 1749 1750 mutex_lock(&vgpu->cache_lock); 1751 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1752 if (entry) 1753 kref_put(&entry->ref, __gvt_dma_release); 1754 mutex_unlock(&vgpu->cache_lock); 1755 } 1756 1757 static void init_device_info(struct intel_gvt *gvt) 1758 { 1759 struct intel_gvt_device_info *info = &gvt->device_info; 1760 struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); 1761 1762 info->max_support_vgpus = 8; 1763 info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE; 1764 info->mmio_size = 2 * 1024 * 1024; 1765 info->mmio_bar = 0; 1766 info->gtt_start_offset = 8 * 1024 * 1024; 1767 info->gtt_entry_size = 8; 1768 info->gtt_entry_size_shift = 3; 1769 info->gmadr_bytes_in_cmd = 8; 1770 info->max_surface_size = 36 * 1024 * 1024; 1771 info->msi_cap_offset = pdev->msi_cap; 1772 } 1773 1774 static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) 1775 { 1776 struct intel_vgpu *vgpu; 1777 int id; 1778 1779 mutex_lock(&gvt->lock); 1780 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) { 1781 if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id, 1782 (void *)&gvt->service_request)) { 1783 if (vgpu->active) 1784 intel_vgpu_emulate_vblank(vgpu); 1785 } 1786 } 1787 mutex_unlock(&gvt->lock); 1788 } 1789 1790 static int gvt_service_thread(void *data) 1791 { 1792 struct intel_gvt *gvt = (struct intel_gvt *)data; 1793 int ret; 1794 1795 gvt_dbg_core("service thread start\n"); 1796 1797 while (!kthread_should_stop()) { 1798 ret = wait_event_interruptible(gvt->service_thread_wq, 1799 kthread_should_stop() || gvt->service_request); 1800 1801 if (kthread_should_stop()) 1802 break; 1803 1804 if (WARN_ONCE(ret, "service thread is waken up by signal.\n")) 1805 continue; 1806 1807 intel_gvt_test_and_emulate_vblank(gvt); 1808 1809 if (test_bit(INTEL_GVT_REQUEST_SCHED, 1810 (void *)&gvt->service_request) || 1811 test_bit(INTEL_GVT_REQUEST_EVENT_SCHED, 1812 (void *)&gvt->service_request)) { 1813 intel_gvt_schedule(gvt); 1814 } 1815 } 1816 1817 return 0; 1818 } 1819 1820 static void clean_service_thread(struct intel_gvt *gvt) 1821 { 1822 kthread_stop(gvt->service_thread); 1823 } 1824 1825 static int init_service_thread(struct intel_gvt *gvt) 1826 { 1827 init_waitqueue_head(&gvt->service_thread_wq); 1828 1829 gvt->service_thread = kthread_run(gvt_service_thread, 1830 gvt, "gvt_service_thread"); 1831 if (IS_ERR(gvt->service_thread)) { 1832 gvt_err("fail to start service thread.\n"); 1833 return PTR_ERR(gvt->service_thread); 1834 } 1835 return 0; 1836 } 1837 1838 /** 1839 * intel_gvt_clean_device - clean a GVT device 1840 * @i915: i915 private 1841 * 1842 * This function is called at the driver unloading stage, to free the 1843 * resources owned by a GVT device. 1844 * 1845 */ 1846 static void intel_gvt_clean_device(struct drm_i915_private *i915) 1847 { 1848 struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); 1849 1850 if (drm_WARN_ON(&i915->drm, !gvt)) 1851 return; 1852 1853 mdev_unregister_parent(&gvt->parent); 1854 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1855 intel_gvt_clean_vgpu_types(gvt); 1856 1857 intel_gvt_debugfs_clean(gvt); 1858 clean_service_thread(gvt); 1859 intel_gvt_clean_cmd_parser(gvt); 1860 intel_gvt_clean_sched_policy(gvt); 1861 intel_gvt_clean_workload_scheduler(gvt); 1862 intel_gvt_clean_gtt(gvt); 1863 intel_gvt_free_firmware(gvt); 1864 intel_gvt_clean_mmio_info(gvt); 1865 idr_destroy(&gvt->vgpu_idr); 1866 1867 kfree(i915->gvt); 1868 } 1869 1870 /** 1871 * intel_gvt_init_device - initialize a GVT device 1872 * @i915: drm i915 private data 1873 * 1874 * This function is called at the initialization stage, to initialize 1875 * necessary GVT components. 1876 * 1877 * Returns: 1878 * Zero on success, negative error code if failed. 1879 * 1880 */ 1881 static int intel_gvt_init_device(struct drm_i915_private *i915) 1882 { 1883 struct intel_gvt *gvt; 1884 struct intel_vgpu *vgpu; 1885 int ret; 1886 1887 if (drm_WARN_ON(&i915->drm, i915->gvt)) 1888 return -EEXIST; 1889 1890 gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL); 1891 if (!gvt) 1892 return -ENOMEM; 1893 1894 gvt_dbg_core("init gvt device\n"); 1895 1896 idr_init_base(&gvt->vgpu_idr, 1); 1897 spin_lock_init(&gvt->scheduler.mmio_context_lock); 1898 mutex_init(&gvt->lock); 1899 mutex_init(&gvt->sched_lock); 1900 gvt->gt = to_gt(i915); 1901 i915->gvt = gvt; 1902 1903 init_device_info(gvt); 1904 1905 ret = intel_gvt_setup_mmio_info(gvt); 1906 if (ret) 1907 goto out_clean_idr; 1908 1909 intel_gvt_init_engine_mmio_context(gvt); 1910 1911 ret = intel_gvt_load_firmware(gvt); 1912 if (ret) 1913 goto out_clean_mmio_info; 1914 1915 ret = intel_gvt_init_irq(gvt); 1916 if (ret) 1917 goto out_free_firmware; 1918 1919 ret = intel_gvt_init_gtt(gvt); 1920 if (ret) 1921 goto out_free_firmware; 1922 1923 ret = intel_gvt_init_workload_scheduler(gvt); 1924 if (ret) 1925 goto out_clean_gtt; 1926 1927 ret = intel_gvt_init_sched_policy(gvt); 1928 if (ret) 1929 goto out_clean_workload_scheduler; 1930 1931 ret = intel_gvt_init_cmd_parser(gvt); 1932 if (ret) 1933 goto out_clean_sched_policy; 1934 1935 ret = init_service_thread(gvt); 1936 if (ret) 1937 goto out_clean_cmd_parser; 1938 1939 ret = intel_gvt_init_vgpu_types(gvt); 1940 if (ret) 1941 goto out_clean_thread; 1942 1943 vgpu = intel_gvt_create_idle_vgpu(gvt); 1944 if (IS_ERR(vgpu)) { 1945 ret = PTR_ERR(vgpu); 1946 gvt_err("failed to create idle vgpu\n"); 1947 goto out_clean_types; 1948 } 1949 gvt->idle_vgpu = vgpu; 1950 1951 intel_gvt_debugfs_init(gvt); 1952 1953 ret = mdev_register_parent(&gvt->parent, i915->drm.dev, 1954 &intel_vgpu_mdev_driver, 1955 gvt->mdev_types, gvt->num_types); 1956 if (ret) 1957 goto out_destroy_idle_vgpu; 1958 1959 gvt_dbg_core("gvt device initialization is done\n"); 1960 return 0; 1961 1962 out_destroy_idle_vgpu: 1963 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1964 intel_gvt_debugfs_clean(gvt); 1965 out_clean_types: 1966 intel_gvt_clean_vgpu_types(gvt); 1967 out_clean_thread: 1968 clean_service_thread(gvt); 1969 out_clean_cmd_parser: 1970 intel_gvt_clean_cmd_parser(gvt); 1971 out_clean_sched_policy: 1972 intel_gvt_clean_sched_policy(gvt); 1973 out_clean_workload_scheduler: 1974 intel_gvt_clean_workload_scheduler(gvt); 1975 out_clean_gtt: 1976 intel_gvt_clean_gtt(gvt); 1977 out_free_firmware: 1978 intel_gvt_free_firmware(gvt); 1979 out_clean_mmio_info: 1980 intel_gvt_clean_mmio_info(gvt); 1981 out_clean_idr: 1982 idr_destroy(&gvt->vgpu_idr); 1983 kfree(gvt); 1984 i915->gvt = NULL; 1985 return ret; 1986 } 1987 1988 static void intel_gvt_pm_resume(struct drm_i915_private *i915) 1989 { 1990 struct intel_gvt *gvt = i915->gvt; 1991 1992 intel_gvt_restore_fence(gvt); 1993 intel_gvt_restore_mmio(gvt); 1994 intel_gvt_restore_ggtt(gvt); 1995 } 1996 1997 static const struct intel_vgpu_ops intel_gvt_vgpu_ops = { 1998 .init_device = intel_gvt_init_device, 1999 .clean_device = intel_gvt_clean_device, 2000 .pm_resume = intel_gvt_pm_resume, 2001 }; 2002 2003 static int __init kvmgt_init(void) 2004 { 2005 int ret; 2006 2007 ret = intel_gvt_set_ops(&intel_gvt_vgpu_ops); 2008 if (ret) 2009 return ret; 2010 2011 ret = mdev_register_driver(&intel_vgpu_mdev_driver); 2012 if (ret) 2013 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 2014 return ret; 2015 } 2016 2017 static void __exit kvmgt_exit(void) 2018 { 2019 mdev_unregister_driver(&intel_vgpu_mdev_driver); 2020 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 2021 } 2022 2023 module_init(kvmgt_init); 2024 module_exit(kvmgt_exit); 2025 2026 MODULE_LICENSE("GPL and additional rights"); 2027 MODULE_AUTHOR("Intel Corporation"); 2028