1 /* 2 * KVMGT - the implementation of Intel mediated pass-through framework for KVM 3 * 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Kevin Tian <kevin.tian@intel.com> 27 * Jike Song <jike.song@intel.com> 28 * Xiaoguang Chen <xiaoguang.chen@intel.com> 29 * Eddie Dong <eddie.dong@intel.com> 30 * 31 * Contributors: 32 * Niu Bing <bing.niu@intel.com> 33 * Zhi Wang <zhi.a.wang@intel.com> 34 */ 35 36 #include <linux/init.h> 37 #include <linux/mm.h> 38 #include <linux/kthread.h> 39 #include <linux/sched/mm.h> 40 #include <linux/types.h> 41 #include <linux/list.h> 42 #include <linux/rbtree.h> 43 #include <linux/spinlock.h> 44 #include <linux/eventfd.h> 45 #include <linux/mdev.h> 46 #include <linux/debugfs.h> 47 48 #include <linux/nospec.h> 49 50 #include <drm/drm_edid.h> 51 52 #include "i915_drv.h" 53 #include "intel_gvt.h" 54 #include "gvt.h" 55 56 MODULE_IMPORT_NS(DMA_BUF); 57 MODULE_IMPORT_NS(I915_GVT); 58 59 /* helper macros copied from vfio-pci */ 60 #define VFIO_PCI_OFFSET_SHIFT 40 61 #define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) 62 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) 63 #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) 64 65 #define EDID_BLOB_OFFSET (PAGE_SIZE/2) 66 67 #define OPREGION_SIGNATURE "IntelGraphicsMem" 68 69 struct vfio_region; 70 struct intel_vgpu_regops { 71 size_t (*rw)(struct intel_vgpu *vgpu, char *buf, 72 size_t count, loff_t *ppos, bool iswrite); 73 void (*release)(struct intel_vgpu *vgpu, 74 struct vfio_region *region); 75 }; 76 77 struct vfio_region { 78 u32 type; 79 u32 subtype; 80 size_t size; 81 u32 flags; 82 const struct intel_vgpu_regops *ops; 83 void *data; 84 }; 85 86 struct vfio_edid_region { 87 struct vfio_region_gfx_edid vfio_edid_regs; 88 void *edid_blob; 89 }; 90 91 struct kvmgt_pgfn { 92 gfn_t gfn; 93 struct hlist_node hnode; 94 }; 95 96 struct gvt_dma { 97 struct intel_vgpu *vgpu; 98 struct rb_node gfn_node; 99 struct rb_node dma_addr_node; 100 gfn_t gfn; 101 dma_addr_t dma_addr; 102 unsigned long size; 103 struct kref ref; 104 }; 105 106 #define vfio_dev_to_vgpu(vfio_dev) \ 107 container_of((vfio_dev), struct intel_vgpu, vfio_device) 108 109 static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 110 const u8 *val, int len, 111 struct kvm_page_track_notifier_node *node); 112 static void kvmgt_page_track_flush_slot(struct kvm *kvm, 113 struct kvm_memory_slot *slot, 114 struct kvm_page_track_notifier_node *node); 115 116 static ssize_t available_instances_show(struct mdev_type *mtype, 117 struct mdev_type_attribute *attr, 118 char *buf) 119 { 120 struct intel_vgpu_type *type = 121 container_of(mtype, struct intel_vgpu_type, type); 122 123 return sprintf(buf, "%u\n", type->avail_instance); 124 } 125 126 static ssize_t description_show(struct mdev_type *mtype, 127 struct mdev_type_attribute *attr, char *buf) 128 { 129 struct intel_vgpu_type *type = 130 container_of(mtype, struct intel_vgpu_type, type); 131 132 return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n" 133 "fence: %d\nresolution: %s\n" 134 "weight: %d\n", 135 BYTES_TO_MB(type->conf->low_mm), 136 BYTES_TO_MB(type->conf->high_mm), 137 type->conf->fence, vgpu_edid_str(type->conf->edid), 138 type->conf->weight); 139 } 140 141 static ssize_t name_show(struct mdev_type *mtype, 142 struct mdev_type_attribute *attr, char *buf) 143 { 144 return sprintf(buf, "%s\n", mtype->sysfs_name); 145 } 146 147 static MDEV_TYPE_ATTR_RO(available_instances); 148 static MDEV_TYPE_ATTR_RO(description); 149 static MDEV_TYPE_ATTR_RO(name); 150 151 static const struct attribute *gvt_type_attrs[] = { 152 &mdev_type_attr_available_instances.attr, 153 &mdev_type_attr_description.attr, 154 &mdev_type_attr_name.attr, 155 NULL, 156 }; 157 158 static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 159 unsigned long size) 160 { 161 vfio_unpin_pages(&vgpu->vfio_device, gfn << PAGE_SHIFT, 162 DIV_ROUND_UP(size, PAGE_SIZE)); 163 } 164 165 /* Pin a normal or compound guest page for dma. */ 166 static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 167 unsigned long size, struct page **page) 168 { 169 int total_pages = DIV_ROUND_UP(size, PAGE_SIZE); 170 struct page *base_page = NULL; 171 int npage; 172 int ret; 173 174 /* 175 * We pin the pages one-by-one to avoid allocating a big arrary 176 * on stack to hold pfns. 177 */ 178 for (npage = 0; npage < total_pages; npage++) { 179 dma_addr_t cur_iova = (gfn + npage) << PAGE_SHIFT; 180 struct page *cur_page; 181 182 ret = vfio_pin_pages(&vgpu->vfio_device, cur_iova, 1, 183 IOMMU_READ | IOMMU_WRITE, &cur_page); 184 if (ret != 1) { 185 gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n", 186 &cur_iova, ret); 187 goto err; 188 } 189 190 if (npage == 0) 191 base_page = cur_page; 192 else if (base_page + npage != cur_page) { 193 gvt_vgpu_err("The pages are not continuous\n"); 194 ret = -EINVAL; 195 npage++; 196 goto err; 197 } 198 } 199 200 *page = base_page; 201 return 0; 202 err: 203 gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); 204 return ret; 205 } 206 207 static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, 208 dma_addr_t *dma_addr, unsigned long size) 209 { 210 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 211 struct page *page = NULL; 212 int ret; 213 214 ret = gvt_pin_guest_page(vgpu, gfn, size, &page); 215 if (ret) 216 return ret; 217 218 /* Setup DMA mapping. */ 219 *dma_addr = dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); 220 if (dma_mapping_error(dev, *dma_addr)) { 221 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", 222 page_to_pfn(page), ret); 223 gvt_unpin_guest_page(vgpu, gfn, size); 224 return -ENOMEM; 225 } 226 227 return 0; 228 } 229 230 static void gvt_dma_unmap_page(struct intel_vgpu *vgpu, unsigned long gfn, 231 dma_addr_t dma_addr, unsigned long size) 232 { 233 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 234 235 dma_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL); 236 gvt_unpin_guest_page(vgpu, gfn, size); 237 } 238 239 static struct gvt_dma *__gvt_cache_find_dma_addr(struct intel_vgpu *vgpu, 240 dma_addr_t dma_addr) 241 { 242 struct rb_node *node = vgpu->dma_addr_cache.rb_node; 243 struct gvt_dma *itr; 244 245 while (node) { 246 itr = rb_entry(node, struct gvt_dma, dma_addr_node); 247 248 if (dma_addr < itr->dma_addr) 249 node = node->rb_left; 250 else if (dma_addr > itr->dma_addr) 251 node = node->rb_right; 252 else 253 return itr; 254 } 255 return NULL; 256 } 257 258 static struct gvt_dma *__gvt_cache_find_gfn(struct intel_vgpu *vgpu, gfn_t gfn) 259 { 260 struct rb_node *node = vgpu->gfn_cache.rb_node; 261 struct gvt_dma *itr; 262 263 while (node) { 264 itr = rb_entry(node, struct gvt_dma, gfn_node); 265 266 if (gfn < itr->gfn) 267 node = node->rb_left; 268 else if (gfn > itr->gfn) 269 node = node->rb_right; 270 else 271 return itr; 272 } 273 return NULL; 274 } 275 276 static int __gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, 277 dma_addr_t dma_addr, unsigned long size) 278 { 279 struct gvt_dma *new, *itr; 280 struct rb_node **link, *parent = NULL; 281 282 new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); 283 if (!new) 284 return -ENOMEM; 285 286 new->vgpu = vgpu; 287 new->gfn = gfn; 288 new->dma_addr = dma_addr; 289 new->size = size; 290 kref_init(&new->ref); 291 292 /* gfn_cache maps gfn to struct gvt_dma. */ 293 link = &vgpu->gfn_cache.rb_node; 294 while (*link) { 295 parent = *link; 296 itr = rb_entry(parent, struct gvt_dma, gfn_node); 297 298 if (gfn < itr->gfn) 299 link = &parent->rb_left; 300 else 301 link = &parent->rb_right; 302 } 303 rb_link_node(&new->gfn_node, parent, link); 304 rb_insert_color(&new->gfn_node, &vgpu->gfn_cache); 305 306 /* dma_addr_cache maps dma addr to struct gvt_dma. */ 307 parent = NULL; 308 link = &vgpu->dma_addr_cache.rb_node; 309 while (*link) { 310 parent = *link; 311 itr = rb_entry(parent, struct gvt_dma, dma_addr_node); 312 313 if (dma_addr < itr->dma_addr) 314 link = &parent->rb_left; 315 else 316 link = &parent->rb_right; 317 } 318 rb_link_node(&new->dma_addr_node, parent, link); 319 rb_insert_color(&new->dma_addr_node, &vgpu->dma_addr_cache); 320 321 vgpu->nr_cache_entries++; 322 return 0; 323 } 324 325 static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, 326 struct gvt_dma *entry) 327 { 328 rb_erase(&entry->gfn_node, &vgpu->gfn_cache); 329 rb_erase(&entry->dma_addr_node, &vgpu->dma_addr_cache); 330 kfree(entry); 331 vgpu->nr_cache_entries--; 332 } 333 334 static void gvt_cache_destroy(struct intel_vgpu *vgpu) 335 { 336 struct gvt_dma *dma; 337 struct rb_node *node = NULL; 338 339 for (;;) { 340 mutex_lock(&vgpu->cache_lock); 341 node = rb_first(&vgpu->gfn_cache); 342 if (!node) { 343 mutex_unlock(&vgpu->cache_lock); 344 break; 345 } 346 dma = rb_entry(node, struct gvt_dma, gfn_node); 347 gvt_dma_unmap_page(vgpu, dma->gfn, dma->dma_addr, dma->size); 348 __gvt_cache_remove_entry(vgpu, dma); 349 mutex_unlock(&vgpu->cache_lock); 350 } 351 } 352 353 static void gvt_cache_init(struct intel_vgpu *vgpu) 354 { 355 vgpu->gfn_cache = RB_ROOT; 356 vgpu->dma_addr_cache = RB_ROOT; 357 vgpu->nr_cache_entries = 0; 358 mutex_init(&vgpu->cache_lock); 359 } 360 361 static void kvmgt_protect_table_init(struct intel_vgpu *info) 362 { 363 hash_init(info->ptable); 364 } 365 366 static void kvmgt_protect_table_destroy(struct intel_vgpu *info) 367 { 368 struct kvmgt_pgfn *p; 369 struct hlist_node *tmp; 370 int i; 371 372 hash_for_each_safe(info->ptable, i, tmp, p, hnode) { 373 hash_del(&p->hnode); 374 kfree(p); 375 } 376 } 377 378 static struct kvmgt_pgfn * 379 __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) 380 { 381 struct kvmgt_pgfn *p, *res = NULL; 382 383 hash_for_each_possible(info->ptable, p, hnode, gfn) { 384 if (gfn == p->gfn) { 385 res = p; 386 break; 387 } 388 } 389 390 return res; 391 } 392 393 static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn) 394 { 395 struct kvmgt_pgfn *p; 396 397 p = __kvmgt_protect_table_find(info, gfn); 398 return !!p; 399 } 400 401 static void kvmgt_protect_table_add(struct intel_vgpu *info, gfn_t gfn) 402 { 403 struct kvmgt_pgfn *p; 404 405 if (kvmgt_gfn_is_write_protected(info, gfn)) 406 return; 407 408 p = kzalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); 409 if (WARN(!p, "gfn: 0x%llx\n", gfn)) 410 return; 411 412 p->gfn = gfn; 413 hash_add(info->ptable, &p->hnode, gfn); 414 } 415 416 static void kvmgt_protect_table_del(struct intel_vgpu *info, gfn_t gfn) 417 { 418 struct kvmgt_pgfn *p; 419 420 p = __kvmgt_protect_table_find(info, gfn); 421 if (p) { 422 hash_del(&p->hnode); 423 kfree(p); 424 } 425 } 426 427 static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, 428 size_t count, loff_t *ppos, bool iswrite) 429 { 430 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 431 VFIO_PCI_NUM_REGIONS; 432 void *base = vgpu->region[i].data; 433 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 434 435 436 if (pos >= vgpu->region[i].size || iswrite) { 437 gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); 438 return -EINVAL; 439 } 440 count = min(count, (size_t)(vgpu->region[i].size - pos)); 441 memcpy(buf, base + pos, count); 442 443 return count; 444 } 445 446 static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, 447 struct vfio_region *region) 448 { 449 } 450 451 static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { 452 .rw = intel_vgpu_reg_rw_opregion, 453 .release = intel_vgpu_reg_release_opregion, 454 }; 455 456 static int handle_edid_regs(struct intel_vgpu *vgpu, 457 struct vfio_edid_region *region, char *buf, 458 size_t count, u16 offset, bool is_write) 459 { 460 struct vfio_region_gfx_edid *regs = ®ion->vfio_edid_regs; 461 unsigned int data; 462 463 if (offset + count > sizeof(*regs)) 464 return -EINVAL; 465 466 if (count != 4) 467 return -EINVAL; 468 469 if (is_write) { 470 data = *((unsigned int *)buf); 471 switch (offset) { 472 case offsetof(struct vfio_region_gfx_edid, link_state): 473 if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) { 474 if (!drm_edid_block_valid( 475 (u8 *)region->edid_blob, 476 0, 477 true, 478 NULL)) { 479 gvt_vgpu_err("invalid EDID blob\n"); 480 return -EINVAL; 481 } 482 intel_vgpu_emulate_hotplug(vgpu, true); 483 } else if (data == VFIO_DEVICE_GFX_LINK_STATE_DOWN) 484 intel_vgpu_emulate_hotplug(vgpu, false); 485 else { 486 gvt_vgpu_err("invalid EDID link state %d\n", 487 regs->link_state); 488 return -EINVAL; 489 } 490 regs->link_state = data; 491 break; 492 case offsetof(struct vfio_region_gfx_edid, edid_size): 493 if (data > regs->edid_max_size) { 494 gvt_vgpu_err("EDID size is bigger than %d!\n", 495 regs->edid_max_size); 496 return -EINVAL; 497 } 498 regs->edid_size = data; 499 break; 500 default: 501 /* read-only regs */ 502 gvt_vgpu_err("write read-only EDID region at offset %d\n", 503 offset); 504 return -EPERM; 505 } 506 } else { 507 memcpy(buf, (char *)regs + offset, count); 508 } 509 510 return count; 511 } 512 513 static int handle_edid_blob(struct vfio_edid_region *region, char *buf, 514 size_t count, u16 offset, bool is_write) 515 { 516 if (offset + count > region->vfio_edid_regs.edid_size) 517 return -EINVAL; 518 519 if (is_write) 520 memcpy(region->edid_blob + offset, buf, count); 521 else 522 memcpy(buf, region->edid_blob + offset, count); 523 524 return count; 525 } 526 527 static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, 528 size_t count, loff_t *ppos, bool iswrite) 529 { 530 int ret; 531 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 532 VFIO_PCI_NUM_REGIONS; 533 struct vfio_edid_region *region = vgpu->region[i].data; 534 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 535 536 if (pos < region->vfio_edid_regs.edid_offset) { 537 ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); 538 } else { 539 pos -= EDID_BLOB_OFFSET; 540 ret = handle_edid_blob(region, buf, count, pos, iswrite); 541 } 542 543 if (ret < 0) 544 gvt_vgpu_err("failed to access EDID region\n"); 545 546 return ret; 547 } 548 549 static void intel_vgpu_reg_release_edid(struct intel_vgpu *vgpu, 550 struct vfio_region *region) 551 { 552 kfree(region->data); 553 } 554 555 static const struct intel_vgpu_regops intel_vgpu_regops_edid = { 556 .rw = intel_vgpu_reg_rw_edid, 557 .release = intel_vgpu_reg_release_edid, 558 }; 559 560 static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, 561 unsigned int type, unsigned int subtype, 562 const struct intel_vgpu_regops *ops, 563 size_t size, u32 flags, void *data) 564 { 565 struct vfio_region *region; 566 567 region = krealloc(vgpu->region, 568 (vgpu->num_regions + 1) * sizeof(*region), 569 GFP_KERNEL); 570 if (!region) 571 return -ENOMEM; 572 573 vgpu->region = region; 574 vgpu->region[vgpu->num_regions].type = type; 575 vgpu->region[vgpu->num_regions].subtype = subtype; 576 vgpu->region[vgpu->num_regions].ops = ops; 577 vgpu->region[vgpu->num_regions].size = size; 578 vgpu->region[vgpu->num_regions].flags = flags; 579 vgpu->region[vgpu->num_regions].data = data; 580 vgpu->num_regions++; 581 return 0; 582 } 583 584 int intel_gvt_set_opregion(struct intel_vgpu *vgpu) 585 { 586 void *base; 587 int ret; 588 589 /* Each vgpu has its own opregion, although VFIO would create another 590 * one later. This one is used to expose opregion to VFIO. And the 591 * other one created by VFIO later, is used by guest actually. 592 */ 593 base = vgpu_opregion(vgpu)->va; 594 if (!base) 595 return -ENOMEM; 596 597 if (memcmp(base, OPREGION_SIGNATURE, 16)) { 598 memunmap(base); 599 return -EINVAL; 600 } 601 602 ret = intel_vgpu_register_reg(vgpu, 603 PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, 604 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, 605 &intel_vgpu_regops_opregion, OPREGION_SIZE, 606 VFIO_REGION_INFO_FLAG_READ, base); 607 608 return ret; 609 } 610 611 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num) 612 { 613 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 614 struct vfio_edid_region *base; 615 int ret; 616 617 base = kzalloc(sizeof(*base), GFP_KERNEL); 618 if (!base) 619 return -ENOMEM; 620 621 /* TODO: Add multi-port and EDID extension block support */ 622 base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; 623 base->vfio_edid_regs.edid_max_size = EDID_SIZE; 624 base->vfio_edid_regs.edid_size = EDID_SIZE; 625 base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); 626 base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); 627 base->edid_blob = port->edid->edid_block; 628 629 ret = intel_vgpu_register_reg(vgpu, 630 VFIO_REGION_TYPE_GFX, 631 VFIO_REGION_SUBTYPE_GFX_EDID, 632 &intel_vgpu_regops_edid, EDID_SIZE, 633 VFIO_REGION_INFO_FLAG_READ | 634 VFIO_REGION_INFO_FLAG_WRITE | 635 VFIO_REGION_INFO_FLAG_CAPS, base); 636 637 return ret; 638 } 639 640 static void intel_vgpu_dma_unmap(struct vfio_device *vfio_dev, u64 iova, 641 u64 length) 642 { 643 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 644 struct gvt_dma *entry; 645 u64 iov_pfn = iova >> PAGE_SHIFT; 646 u64 end_iov_pfn = iov_pfn + length / PAGE_SIZE; 647 648 mutex_lock(&vgpu->cache_lock); 649 for (; iov_pfn < end_iov_pfn; iov_pfn++) { 650 entry = __gvt_cache_find_gfn(vgpu, iov_pfn); 651 if (!entry) 652 continue; 653 654 gvt_dma_unmap_page(vgpu, entry->gfn, entry->dma_addr, 655 entry->size); 656 __gvt_cache_remove_entry(vgpu, entry); 657 } 658 mutex_unlock(&vgpu->cache_lock); 659 } 660 661 static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu) 662 { 663 struct intel_vgpu *itr; 664 int id; 665 bool ret = false; 666 667 mutex_lock(&vgpu->gvt->lock); 668 for_each_active_vgpu(vgpu->gvt, itr, id) { 669 if (!itr->attached) 670 continue; 671 672 if (vgpu->vfio_device.kvm == itr->vfio_device.kvm) { 673 ret = true; 674 goto out; 675 } 676 } 677 out: 678 mutex_unlock(&vgpu->gvt->lock); 679 return ret; 680 } 681 682 static int intel_vgpu_open_device(struct vfio_device *vfio_dev) 683 { 684 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 685 686 if (vgpu->attached) 687 return -EEXIST; 688 689 if (!vgpu->vfio_device.kvm || 690 vgpu->vfio_device.kvm->mm != current->mm) { 691 gvt_vgpu_err("KVM is required to use Intel vGPU\n"); 692 return -ESRCH; 693 } 694 695 kvm_get_kvm(vgpu->vfio_device.kvm); 696 697 if (__kvmgt_vgpu_exist(vgpu)) 698 return -EEXIST; 699 700 vgpu->attached = true; 701 702 kvmgt_protect_table_init(vgpu); 703 gvt_cache_init(vgpu); 704 705 vgpu->track_node.track_write = kvmgt_page_track_write; 706 vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot; 707 kvm_page_track_register_notifier(vgpu->vfio_device.kvm, 708 &vgpu->track_node); 709 710 debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs, 711 &vgpu->nr_cache_entries); 712 713 intel_gvt_activate_vgpu(vgpu); 714 715 atomic_set(&vgpu->released, 0); 716 return 0; 717 } 718 719 static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu) 720 { 721 struct eventfd_ctx *trigger; 722 723 trigger = vgpu->msi_trigger; 724 if (trigger) { 725 eventfd_ctx_put(trigger); 726 vgpu->msi_trigger = NULL; 727 } 728 } 729 730 static void intel_vgpu_close_device(struct vfio_device *vfio_dev) 731 { 732 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 733 734 if (!vgpu->attached) 735 return; 736 737 if (atomic_cmpxchg(&vgpu->released, 0, 1)) 738 return; 739 740 intel_gvt_release_vgpu(vgpu); 741 742 debugfs_remove(debugfs_lookup(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs)); 743 744 kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm, 745 &vgpu->track_node); 746 kvmgt_protect_table_destroy(vgpu); 747 gvt_cache_destroy(vgpu); 748 749 intel_vgpu_release_msi_eventfd_ctx(vgpu); 750 751 vgpu->attached = false; 752 753 if (vgpu->vfio_device.kvm) 754 kvm_put_kvm(vgpu->vfio_device.kvm); 755 } 756 757 static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar) 758 { 759 u32 start_lo, start_hi; 760 u32 mem_type; 761 762 start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 763 PCI_BASE_ADDRESS_MEM_MASK; 764 mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 765 PCI_BASE_ADDRESS_MEM_TYPE_MASK; 766 767 switch (mem_type) { 768 case PCI_BASE_ADDRESS_MEM_TYPE_64: 769 start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space 770 + bar + 4)); 771 break; 772 case PCI_BASE_ADDRESS_MEM_TYPE_32: 773 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 774 /* 1M mem BAR treated as 32-bit BAR */ 775 default: 776 /* mem unknown type treated as 32-bit BAR */ 777 start_hi = 0; 778 break; 779 } 780 781 return ((u64)start_hi << 32) | start_lo; 782 } 783 784 static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off, 785 void *buf, unsigned int count, bool is_write) 786 { 787 u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar); 788 int ret; 789 790 if (is_write) 791 ret = intel_vgpu_emulate_mmio_write(vgpu, 792 bar_start + off, buf, count); 793 else 794 ret = intel_vgpu_emulate_mmio_read(vgpu, 795 bar_start + off, buf, count); 796 return ret; 797 } 798 799 static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) 800 { 801 return off >= vgpu_aperture_offset(vgpu) && 802 off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); 803 } 804 805 static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, 806 void *buf, unsigned long count, bool is_write) 807 { 808 void __iomem *aperture_va; 809 810 if (!intel_vgpu_in_aperture(vgpu, off) || 811 !intel_vgpu_in_aperture(vgpu, off + count)) { 812 gvt_vgpu_err("Invalid aperture offset %llu\n", off); 813 return -EINVAL; 814 } 815 816 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, 817 ALIGN_DOWN(off, PAGE_SIZE), 818 count + offset_in_page(off)); 819 if (!aperture_va) 820 return -EIO; 821 822 if (is_write) 823 memcpy_toio(aperture_va + offset_in_page(off), buf, count); 824 else 825 memcpy_fromio(buf, aperture_va + offset_in_page(off), count); 826 827 io_mapping_unmap(aperture_va); 828 829 return 0; 830 } 831 832 static ssize_t intel_vgpu_rw(struct intel_vgpu *vgpu, char *buf, 833 size_t count, loff_t *ppos, bool is_write) 834 { 835 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 836 u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; 837 int ret = -EINVAL; 838 839 840 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) { 841 gvt_vgpu_err("invalid index: %u\n", index); 842 return -EINVAL; 843 } 844 845 switch (index) { 846 case VFIO_PCI_CONFIG_REGION_INDEX: 847 if (is_write) 848 ret = intel_vgpu_emulate_cfg_write(vgpu, pos, 849 buf, count); 850 else 851 ret = intel_vgpu_emulate_cfg_read(vgpu, pos, 852 buf, count); 853 break; 854 case VFIO_PCI_BAR0_REGION_INDEX: 855 ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos, 856 buf, count, is_write); 857 break; 858 case VFIO_PCI_BAR2_REGION_INDEX: 859 ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write); 860 break; 861 case VFIO_PCI_BAR1_REGION_INDEX: 862 case VFIO_PCI_BAR3_REGION_INDEX: 863 case VFIO_PCI_BAR4_REGION_INDEX: 864 case VFIO_PCI_BAR5_REGION_INDEX: 865 case VFIO_PCI_VGA_REGION_INDEX: 866 case VFIO_PCI_ROM_REGION_INDEX: 867 break; 868 default: 869 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) 870 return -EINVAL; 871 872 index -= VFIO_PCI_NUM_REGIONS; 873 return vgpu->region[index].ops->rw(vgpu, buf, count, 874 ppos, is_write); 875 } 876 877 return ret == 0 ? count : ret; 878 } 879 880 static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos) 881 { 882 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 883 struct intel_gvt *gvt = vgpu->gvt; 884 int offset; 885 886 /* Only allow MMIO GGTT entry access */ 887 if (index != PCI_BASE_ADDRESS_0) 888 return false; 889 890 offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - 891 intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 892 893 return (offset >= gvt->device_info.gtt_start_offset && 894 offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? 895 true : false; 896 } 897 898 static ssize_t intel_vgpu_read(struct vfio_device *vfio_dev, char __user *buf, 899 size_t count, loff_t *ppos) 900 { 901 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 902 unsigned int done = 0; 903 int ret; 904 905 while (count) { 906 size_t filled; 907 908 /* Only support GGTT entry 8 bytes read */ 909 if (count >= 8 && !(*ppos % 8) && 910 gtt_entry(vgpu, ppos)) { 911 u64 val; 912 913 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 914 ppos, false); 915 if (ret <= 0) 916 goto read_err; 917 918 if (copy_to_user(buf, &val, sizeof(val))) 919 goto read_err; 920 921 filled = 8; 922 } else if (count >= 4 && !(*ppos % 4)) { 923 u32 val; 924 925 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 926 ppos, false); 927 if (ret <= 0) 928 goto read_err; 929 930 if (copy_to_user(buf, &val, sizeof(val))) 931 goto read_err; 932 933 filled = 4; 934 } else if (count >= 2 && !(*ppos % 2)) { 935 u16 val; 936 937 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 938 ppos, false); 939 if (ret <= 0) 940 goto read_err; 941 942 if (copy_to_user(buf, &val, sizeof(val))) 943 goto read_err; 944 945 filled = 2; 946 } else { 947 u8 val; 948 949 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos, 950 false); 951 if (ret <= 0) 952 goto read_err; 953 954 if (copy_to_user(buf, &val, sizeof(val))) 955 goto read_err; 956 957 filled = 1; 958 } 959 960 count -= filled; 961 done += filled; 962 *ppos += filled; 963 buf += filled; 964 } 965 966 return done; 967 968 read_err: 969 return -EFAULT; 970 } 971 972 static ssize_t intel_vgpu_write(struct vfio_device *vfio_dev, 973 const char __user *buf, 974 size_t count, loff_t *ppos) 975 { 976 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 977 unsigned int done = 0; 978 int ret; 979 980 while (count) { 981 size_t filled; 982 983 /* Only support GGTT entry 8 bytes write */ 984 if (count >= 8 && !(*ppos % 8) && 985 gtt_entry(vgpu, ppos)) { 986 u64 val; 987 988 if (copy_from_user(&val, buf, sizeof(val))) 989 goto write_err; 990 991 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 992 ppos, true); 993 if (ret <= 0) 994 goto write_err; 995 996 filled = 8; 997 } else if (count >= 4 && !(*ppos % 4)) { 998 u32 val; 999 1000 if (copy_from_user(&val, buf, sizeof(val))) 1001 goto write_err; 1002 1003 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 1004 ppos, true); 1005 if (ret <= 0) 1006 goto write_err; 1007 1008 filled = 4; 1009 } else if (count >= 2 && !(*ppos % 2)) { 1010 u16 val; 1011 1012 if (copy_from_user(&val, buf, sizeof(val))) 1013 goto write_err; 1014 1015 ret = intel_vgpu_rw(vgpu, (char *)&val, 1016 sizeof(val), ppos, true); 1017 if (ret <= 0) 1018 goto write_err; 1019 1020 filled = 2; 1021 } else { 1022 u8 val; 1023 1024 if (copy_from_user(&val, buf, sizeof(val))) 1025 goto write_err; 1026 1027 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), 1028 ppos, true); 1029 if (ret <= 0) 1030 goto write_err; 1031 1032 filled = 1; 1033 } 1034 1035 count -= filled; 1036 done += filled; 1037 *ppos += filled; 1038 buf += filled; 1039 } 1040 1041 return done; 1042 write_err: 1043 return -EFAULT; 1044 } 1045 1046 static int intel_vgpu_mmap(struct vfio_device *vfio_dev, 1047 struct vm_area_struct *vma) 1048 { 1049 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1050 unsigned int index; 1051 u64 virtaddr; 1052 unsigned long req_size, pgoff, req_start; 1053 pgprot_t pg_prot; 1054 1055 index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); 1056 if (index >= VFIO_PCI_ROM_REGION_INDEX) 1057 return -EINVAL; 1058 1059 if (vma->vm_end < vma->vm_start) 1060 return -EINVAL; 1061 if ((vma->vm_flags & VM_SHARED) == 0) 1062 return -EINVAL; 1063 if (index != VFIO_PCI_BAR2_REGION_INDEX) 1064 return -EINVAL; 1065 1066 pg_prot = vma->vm_page_prot; 1067 virtaddr = vma->vm_start; 1068 req_size = vma->vm_end - vma->vm_start; 1069 pgoff = vma->vm_pgoff & 1070 ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); 1071 req_start = pgoff << PAGE_SHIFT; 1072 1073 if (!intel_vgpu_in_aperture(vgpu, req_start)) 1074 return -EINVAL; 1075 if (req_start + req_size > 1076 vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) 1077 return -EINVAL; 1078 1079 pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; 1080 1081 return remap_pfn_range(vma, virtaddr, pgoff, req_size, pg_prot); 1082 } 1083 1084 static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) 1085 { 1086 if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) 1087 return 1; 1088 1089 return 0; 1090 } 1091 1092 static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu, 1093 unsigned int index, unsigned int start, 1094 unsigned int count, u32 flags, 1095 void *data) 1096 { 1097 return 0; 1098 } 1099 1100 static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu, 1101 unsigned int index, unsigned int start, 1102 unsigned int count, u32 flags, void *data) 1103 { 1104 return 0; 1105 } 1106 1107 static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu, 1108 unsigned int index, unsigned int start, unsigned int count, 1109 u32 flags, void *data) 1110 { 1111 return 0; 1112 } 1113 1114 static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, 1115 unsigned int index, unsigned int start, unsigned int count, 1116 u32 flags, void *data) 1117 { 1118 struct eventfd_ctx *trigger; 1119 1120 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { 1121 int fd = *(int *)data; 1122 1123 trigger = eventfd_ctx_fdget(fd); 1124 if (IS_ERR(trigger)) { 1125 gvt_vgpu_err("eventfd_ctx_fdget failed\n"); 1126 return PTR_ERR(trigger); 1127 } 1128 vgpu->msi_trigger = trigger; 1129 } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) 1130 intel_vgpu_release_msi_eventfd_ctx(vgpu); 1131 1132 return 0; 1133 } 1134 1135 static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, 1136 unsigned int index, unsigned int start, unsigned int count, 1137 void *data) 1138 { 1139 int (*func)(struct intel_vgpu *vgpu, unsigned int index, 1140 unsigned int start, unsigned int count, u32 flags, 1141 void *data) = NULL; 1142 1143 switch (index) { 1144 case VFIO_PCI_INTX_IRQ_INDEX: 1145 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1146 case VFIO_IRQ_SET_ACTION_MASK: 1147 func = intel_vgpu_set_intx_mask; 1148 break; 1149 case VFIO_IRQ_SET_ACTION_UNMASK: 1150 func = intel_vgpu_set_intx_unmask; 1151 break; 1152 case VFIO_IRQ_SET_ACTION_TRIGGER: 1153 func = intel_vgpu_set_intx_trigger; 1154 break; 1155 } 1156 break; 1157 case VFIO_PCI_MSI_IRQ_INDEX: 1158 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1159 case VFIO_IRQ_SET_ACTION_MASK: 1160 case VFIO_IRQ_SET_ACTION_UNMASK: 1161 /* XXX Need masking support exported */ 1162 break; 1163 case VFIO_IRQ_SET_ACTION_TRIGGER: 1164 func = intel_vgpu_set_msi_trigger; 1165 break; 1166 } 1167 break; 1168 } 1169 1170 if (!func) 1171 return -ENOTTY; 1172 1173 return func(vgpu, index, start, count, flags, data); 1174 } 1175 1176 static long intel_vgpu_ioctl(struct vfio_device *vfio_dev, unsigned int cmd, 1177 unsigned long arg) 1178 { 1179 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1180 unsigned long minsz; 1181 1182 gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); 1183 1184 if (cmd == VFIO_DEVICE_GET_INFO) { 1185 struct vfio_device_info info; 1186 1187 minsz = offsetofend(struct vfio_device_info, num_irqs); 1188 1189 if (copy_from_user(&info, (void __user *)arg, minsz)) 1190 return -EFAULT; 1191 1192 if (info.argsz < minsz) 1193 return -EINVAL; 1194 1195 info.flags = VFIO_DEVICE_FLAGS_PCI; 1196 info.flags |= VFIO_DEVICE_FLAGS_RESET; 1197 info.num_regions = VFIO_PCI_NUM_REGIONS + 1198 vgpu->num_regions; 1199 info.num_irqs = VFIO_PCI_NUM_IRQS; 1200 1201 return copy_to_user((void __user *)arg, &info, minsz) ? 1202 -EFAULT : 0; 1203 1204 } else if (cmd == VFIO_DEVICE_GET_REGION_INFO) { 1205 struct vfio_region_info info; 1206 struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; 1207 unsigned int i; 1208 int ret; 1209 struct vfio_region_info_cap_sparse_mmap *sparse = NULL; 1210 int nr_areas = 1; 1211 int cap_type_id; 1212 1213 minsz = offsetofend(struct vfio_region_info, offset); 1214 1215 if (copy_from_user(&info, (void __user *)arg, minsz)) 1216 return -EFAULT; 1217 1218 if (info.argsz < minsz) 1219 return -EINVAL; 1220 1221 switch (info.index) { 1222 case VFIO_PCI_CONFIG_REGION_INDEX: 1223 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1224 info.size = vgpu->gvt->device_info.cfg_space_size; 1225 info.flags = VFIO_REGION_INFO_FLAG_READ | 1226 VFIO_REGION_INFO_FLAG_WRITE; 1227 break; 1228 case VFIO_PCI_BAR0_REGION_INDEX: 1229 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1230 info.size = vgpu->cfg_space.bar[info.index].size; 1231 if (!info.size) { 1232 info.flags = 0; 1233 break; 1234 } 1235 1236 info.flags = VFIO_REGION_INFO_FLAG_READ | 1237 VFIO_REGION_INFO_FLAG_WRITE; 1238 break; 1239 case VFIO_PCI_BAR1_REGION_INDEX: 1240 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1241 info.size = 0; 1242 info.flags = 0; 1243 break; 1244 case VFIO_PCI_BAR2_REGION_INDEX: 1245 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1246 info.flags = VFIO_REGION_INFO_FLAG_CAPS | 1247 VFIO_REGION_INFO_FLAG_MMAP | 1248 VFIO_REGION_INFO_FLAG_READ | 1249 VFIO_REGION_INFO_FLAG_WRITE; 1250 info.size = gvt_aperture_sz(vgpu->gvt); 1251 1252 sparse = kzalloc(struct_size(sparse, areas, nr_areas), 1253 GFP_KERNEL); 1254 if (!sparse) 1255 return -ENOMEM; 1256 1257 sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1258 sparse->header.version = 1; 1259 sparse->nr_areas = nr_areas; 1260 cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1261 sparse->areas[0].offset = 1262 PAGE_ALIGN(vgpu_aperture_offset(vgpu)); 1263 sparse->areas[0].size = vgpu_aperture_sz(vgpu); 1264 break; 1265 1266 case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: 1267 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1268 info.size = 0; 1269 info.flags = 0; 1270 1271 gvt_dbg_core("get region info bar:%d\n", info.index); 1272 break; 1273 1274 case VFIO_PCI_ROM_REGION_INDEX: 1275 case VFIO_PCI_VGA_REGION_INDEX: 1276 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1277 info.size = 0; 1278 info.flags = 0; 1279 1280 gvt_dbg_core("get region info index:%d\n", info.index); 1281 break; 1282 default: 1283 { 1284 struct vfio_region_info_cap_type cap_type = { 1285 .header.id = VFIO_REGION_INFO_CAP_TYPE, 1286 .header.version = 1 }; 1287 1288 if (info.index >= VFIO_PCI_NUM_REGIONS + 1289 vgpu->num_regions) 1290 return -EINVAL; 1291 info.index = 1292 array_index_nospec(info.index, 1293 VFIO_PCI_NUM_REGIONS + 1294 vgpu->num_regions); 1295 1296 i = info.index - VFIO_PCI_NUM_REGIONS; 1297 1298 info.offset = 1299 VFIO_PCI_INDEX_TO_OFFSET(info.index); 1300 info.size = vgpu->region[i].size; 1301 info.flags = vgpu->region[i].flags; 1302 1303 cap_type.type = vgpu->region[i].type; 1304 cap_type.subtype = vgpu->region[i].subtype; 1305 1306 ret = vfio_info_add_capability(&caps, 1307 &cap_type.header, 1308 sizeof(cap_type)); 1309 if (ret) 1310 return ret; 1311 } 1312 } 1313 1314 if ((info.flags & VFIO_REGION_INFO_FLAG_CAPS) && sparse) { 1315 switch (cap_type_id) { 1316 case VFIO_REGION_INFO_CAP_SPARSE_MMAP: 1317 ret = vfio_info_add_capability(&caps, 1318 &sparse->header, 1319 struct_size(sparse, areas, 1320 sparse->nr_areas)); 1321 if (ret) { 1322 kfree(sparse); 1323 return ret; 1324 } 1325 break; 1326 default: 1327 kfree(sparse); 1328 return -EINVAL; 1329 } 1330 } 1331 1332 if (caps.size) { 1333 info.flags |= VFIO_REGION_INFO_FLAG_CAPS; 1334 if (info.argsz < sizeof(info) + caps.size) { 1335 info.argsz = sizeof(info) + caps.size; 1336 info.cap_offset = 0; 1337 } else { 1338 vfio_info_cap_shift(&caps, sizeof(info)); 1339 if (copy_to_user((void __user *)arg + 1340 sizeof(info), caps.buf, 1341 caps.size)) { 1342 kfree(caps.buf); 1343 kfree(sparse); 1344 return -EFAULT; 1345 } 1346 info.cap_offset = sizeof(info); 1347 } 1348 1349 kfree(caps.buf); 1350 } 1351 1352 kfree(sparse); 1353 return copy_to_user((void __user *)arg, &info, minsz) ? 1354 -EFAULT : 0; 1355 } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { 1356 struct vfio_irq_info info; 1357 1358 minsz = offsetofend(struct vfio_irq_info, count); 1359 1360 if (copy_from_user(&info, (void __user *)arg, minsz)) 1361 return -EFAULT; 1362 1363 if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) 1364 return -EINVAL; 1365 1366 switch (info.index) { 1367 case VFIO_PCI_INTX_IRQ_INDEX: 1368 case VFIO_PCI_MSI_IRQ_INDEX: 1369 break; 1370 default: 1371 return -EINVAL; 1372 } 1373 1374 info.flags = VFIO_IRQ_INFO_EVENTFD; 1375 1376 info.count = intel_vgpu_get_irq_count(vgpu, info.index); 1377 1378 if (info.index == VFIO_PCI_INTX_IRQ_INDEX) 1379 info.flags |= (VFIO_IRQ_INFO_MASKABLE | 1380 VFIO_IRQ_INFO_AUTOMASKED); 1381 else 1382 info.flags |= VFIO_IRQ_INFO_NORESIZE; 1383 1384 return copy_to_user((void __user *)arg, &info, minsz) ? 1385 -EFAULT : 0; 1386 } else if (cmd == VFIO_DEVICE_SET_IRQS) { 1387 struct vfio_irq_set hdr; 1388 u8 *data = NULL; 1389 int ret = 0; 1390 size_t data_size = 0; 1391 1392 minsz = offsetofend(struct vfio_irq_set, count); 1393 1394 if (copy_from_user(&hdr, (void __user *)arg, minsz)) 1395 return -EFAULT; 1396 1397 if (!(hdr.flags & VFIO_IRQ_SET_DATA_NONE)) { 1398 int max = intel_vgpu_get_irq_count(vgpu, hdr.index); 1399 1400 ret = vfio_set_irqs_validate_and_prepare(&hdr, max, 1401 VFIO_PCI_NUM_IRQS, &data_size); 1402 if (ret) { 1403 gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); 1404 return -EINVAL; 1405 } 1406 if (data_size) { 1407 data = memdup_user((void __user *)(arg + minsz), 1408 data_size); 1409 if (IS_ERR(data)) 1410 return PTR_ERR(data); 1411 } 1412 } 1413 1414 ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index, 1415 hdr.start, hdr.count, data); 1416 kfree(data); 1417 1418 return ret; 1419 } else if (cmd == VFIO_DEVICE_RESET) { 1420 intel_gvt_reset_vgpu(vgpu); 1421 return 0; 1422 } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { 1423 struct vfio_device_gfx_plane_info dmabuf; 1424 int ret = 0; 1425 1426 minsz = offsetofend(struct vfio_device_gfx_plane_info, 1427 dmabuf_id); 1428 if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) 1429 return -EFAULT; 1430 if (dmabuf.argsz < minsz) 1431 return -EINVAL; 1432 1433 ret = intel_vgpu_query_plane(vgpu, &dmabuf); 1434 if (ret != 0) 1435 return ret; 1436 1437 return copy_to_user((void __user *)arg, &dmabuf, minsz) ? 1438 -EFAULT : 0; 1439 } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { 1440 __u32 dmabuf_id; 1441 1442 if (get_user(dmabuf_id, (__u32 __user *)arg)) 1443 return -EFAULT; 1444 return intel_vgpu_get_dmabuf(vgpu, dmabuf_id); 1445 } 1446 1447 return -ENOTTY; 1448 } 1449 1450 static ssize_t 1451 vgpu_id_show(struct device *dev, struct device_attribute *attr, 1452 char *buf) 1453 { 1454 struct intel_vgpu *vgpu = dev_get_drvdata(dev); 1455 1456 return sprintf(buf, "%d\n", vgpu->id); 1457 } 1458 1459 static DEVICE_ATTR_RO(vgpu_id); 1460 1461 static struct attribute *intel_vgpu_attrs[] = { 1462 &dev_attr_vgpu_id.attr, 1463 NULL 1464 }; 1465 1466 static const struct attribute_group intel_vgpu_group = { 1467 .name = "intel_vgpu", 1468 .attrs = intel_vgpu_attrs, 1469 }; 1470 1471 static const struct attribute_group *intel_vgpu_groups[] = { 1472 &intel_vgpu_group, 1473 NULL, 1474 }; 1475 1476 static int intel_vgpu_init_dev(struct vfio_device *vfio_dev) 1477 { 1478 struct mdev_device *mdev = to_mdev_device(vfio_dev->dev); 1479 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1480 struct intel_vgpu_type *type = 1481 container_of(mdev->type, struct intel_vgpu_type, type); 1482 1483 vgpu->gvt = kdev_to_i915(mdev->type->parent->dev)->gvt; 1484 return intel_gvt_create_vgpu(vgpu, type->conf); 1485 } 1486 1487 static void intel_vgpu_release_dev(struct vfio_device *vfio_dev) 1488 { 1489 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1490 1491 intel_gvt_destroy_vgpu(vgpu); 1492 vfio_free_device(vfio_dev); 1493 } 1494 1495 static const struct vfio_device_ops intel_vgpu_dev_ops = { 1496 .init = intel_vgpu_init_dev, 1497 .release = intel_vgpu_release_dev, 1498 .open_device = intel_vgpu_open_device, 1499 .close_device = intel_vgpu_close_device, 1500 .read = intel_vgpu_read, 1501 .write = intel_vgpu_write, 1502 .mmap = intel_vgpu_mmap, 1503 .ioctl = intel_vgpu_ioctl, 1504 .dma_unmap = intel_vgpu_dma_unmap, 1505 }; 1506 1507 static int intel_vgpu_probe(struct mdev_device *mdev) 1508 { 1509 struct intel_vgpu *vgpu; 1510 int ret; 1511 1512 vgpu = vfio_alloc_device(intel_vgpu, vfio_device, &mdev->dev, 1513 &intel_vgpu_dev_ops); 1514 if (IS_ERR(vgpu)) { 1515 gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu)); 1516 return PTR_ERR(vgpu); 1517 } 1518 1519 dev_set_drvdata(&mdev->dev, vgpu); 1520 ret = vfio_register_emulated_iommu_dev(&vgpu->vfio_device); 1521 if (ret) 1522 goto out_put_vdev; 1523 1524 gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", 1525 dev_name(mdev_dev(mdev))); 1526 return 0; 1527 1528 out_put_vdev: 1529 vfio_put_device(&vgpu->vfio_device); 1530 return ret; 1531 } 1532 1533 static void intel_vgpu_remove(struct mdev_device *mdev) 1534 { 1535 struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev); 1536 1537 if (WARN_ON_ONCE(vgpu->attached)) 1538 return; 1539 1540 vfio_unregister_group_dev(&vgpu->vfio_device); 1541 vfio_put_device(&vgpu->vfio_device); 1542 } 1543 1544 static struct mdev_driver intel_vgpu_mdev_driver = { 1545 .device_api = VFIO_DEVICE_API_PCI_STRING, 1546 .driver = { 1547 .name = "intel_vgpu_mdev", 1548 .owner = THIS_MODULE, 1549 .dev_groups = intel_vgpu_groups, 1550 }, 1551 .probe = intel_vgpu_probe, 1552 .remove = intel_vgpu_remove, 1553 .types_attrs = gvt_type_attrs, 1554 }; 1555 1556 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) 1557 { 1558 struct kvm *kvm = info->vfio_device.kvm; 1559 struct kvm_memory_slot *slot; 1560 int idx; 1561 1562 if (!info->attached) 1563 return -ESRCH; 1564 1565 idx = srcu_read_lock(&kvm->srcu); 1566 slot = gfn_to_memslot(kvm, gfn); 1567 if (!slot) { 1568 srcu_read_unlock(&kvm->srcu, idx); 1569 return -EINVAL; 1570 } 1571 1572 write_lock(&kvm->mmu_lock); 1573 1574 if (kvmgt_gfn_is_write_protected(info, gfn)) 1575 goto out; 1576 1577 kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); 1578 kvmgt_protect_table_add(info, gfn); 1579 1580 out: 1581 write_unlock(&kvm->mmu_lock); 1582 srcu_read_unlock(&kvm->srcu, idx); 1583 return 0; 1584 } 1585 1586 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) 1587 { 1588 struct kvm *kvm = info->vfio_device.kvm; 1589 struct kvm_memory_slot *slot; 1590 int idx; 1591 1592 if (!info->attached) 1593 return 0; 1594 1595 idx = srcu_read_lock(&kvm->srcu); 1596 slot = gfn_to_memslot(kvm, gfn); 1597 if (!slot) { 1598 srcu_read_unlock(&kvm->srcu, idx); 1599 return -EINVAL; 1600 } 1601 1602 write_lock(&kvm->mmu_lock); 1603 1604 if (!kvmgt_gfn_is_write_protected(info, gfn)) 1605 goto out; 1606 1607 kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); 1608 kvmgt_protect_table_del(info, gfn); 1609 1610 out: 1611 write_unlock(&kvm->mmu_lock); 1612 srcu_read_unlock(&kvm->srcu, idx); 1613 return 0; 1614 } 1615 1616 static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 1617 const u8 *val, int len, 1618 struct kvm_page_track_notifier_node *node) 1619 { 1620 struct intel_vgpu *info = 1621 container_of(node, struct intel_vgpu, track_node); 1622 1623 if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) 1624 intel_vgpu_page_track_handler(info, gpa, 1625 (void *)val, len); 1626 } 1627 1628 static void kvmgt_page_track_flush_slot(struct kvm *kvm, 1629 struct kvm_memory_slot *slot, 1630 struct kvm_page_track_notifier_node *node) 1631 { 1632 int i; 1633 gfn_t gfn; 1634 struct intel_vgpu *info = 1635 container_of(node, struct intel_vgpu, track_node); 1636 1637 write_lock(&kvm->mmu_lock); 1638 for (i = 0; i < slot->npages; i++) { 1639 gfn = slot->base_gfn + i; 1640 if (kvmgt_gfn_is_write_protected(info, gfn)) { 1641 kvm_slot_page_track_remove_page(kvm, slot, gfn, 1642 KVM_PAGE_TRACK_WRITE); 1643 kvmgt_protect_table_del(info, gfn); 1644 } 1645 } 1646 write_unlock(&kvm->mmu_lock); 1647 } 1648 1649 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) 1650 { 1651 int i; 1652 1653 if (!vgpu->region) 1654 return; 1655 1656 for (i = 0; i < vgpu->num_regions; i++) 1657 if (vgpu->region[i].ops->release) 1658 vgpu->region[i].ops->release(vgpu, 1659 &vgpu->region[i]); 1660 vgpu->num_regions = 0; 1661 kfree(vgpu->region); 1662 vgpu->region = NULL; 1663 } 1664 1665 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 1666 unsigned long size, dma_addr_t *dma_addr) 1667 { 1668 struct gvt_dma *entry; 1669 int ret; 1670 1671 if (!vgpu->attached) 1672 return -EINVAL; 1673 1674 mutex_lock(&vgpu->cache_lock); 1675 1676 entry = __gvt_cache_find_gfn(vgpu, gfn); 1677 if (!entry) { 1678 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1679 if (ret) 1680 goto err_unlock; 1681 1682 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1683 if (ret) 1684 goto err_unmap; 1685 } else if (entry->size != size) { 1686 /* the same gfn with different size: unmap and re-map */ 1687 gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); 1688 __gvt_cache_remove_entry(vgpu, entry); 1689 1690 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1691 if (ret) 1692 goto err_unlock; 1693 1694 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1695 if (ret) 1696 goto err_unmap; 1697 } else { 1698 kref_get(&entry->ref); 1699 *dma_addr = entry->dma_addr; 1700 } 1701 1702 mutex_unlock(&vgpu->cache_lock); 1703 return 0; 1704 1705 err_unmap: 1706 gvt_dma_unmap_page(vgpu, gfn, *dma_addr, size); 1707 err_unlock: 1708 mutex_unlock(&vgpu->cache_lock); 1709 return ret; 1710 } 1711 1712 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr) 1713 { 1714 struct gvt_dma *entry; 1715 int ret = 0; 1716 1717 if (!vgpu->attached) 1718 return -ENODEV; 1719 1720 mutex_lock(&vgpu->cache_lock); 1721 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1722 if (entry) 1723 kref_get(&entry->ref); 1724 else 1725 ret = -ENOMEM; 1726 mutex_unlock(&vgpu->cache_lock); 1727 1728 return ret; 1729 } 1730 1731 static void __gvt_dma_release(struct kref *ref) 1732 { 1733 struct gvt_dma *entry = container_of(ref, typeof(*entry), ref); 1734 1735 gvt_dma_unmap_page(entry->vgpu, entry->gfn, entry->dma_addr, 1736 entry->size); 1737 __gvt_cache_remove_entry(entry->vgpu, entry); 1738 } 1739 1740 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, 1741 dma_addr_t dma_addr) 1742 { 1743 struct gvt_dma *entry; 1744 1745 if (!vgpu->attached) 1746 return; 1747 1748 mutex_lock(&vgpu->cache_lock); 1749 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1750 if (entry) 1751 kref_put(&entry->ref, __gvt_dma_release); 1752 mutex_unlock(&vgpu->cache_lock); 1753 } 1754 1755 static void init_device_info(struct intel_gvt *gvt) 1756 { 1757 struct intel_gvt_device_info *info = &gvt->device_info; 1758 struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); 1759 1760 info->max_support_vgpus = 8; 1761 info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE; 1762 info->mmio_size = 2 * 1024 * 1024; 1763 info->mmio_bar = 0; 1764 info->gtt_start_offset = 8 * 1024 * 1024; 1765 info->gtt_entry_size = 8; 1766 info->gtt_entry_size_shift = 3; 1767 info->gmadr_bytes_in_cmd = 8; 1768 info->max_surface_size = 36 * 1024 * 1024; 1769 info->msi_cap_offset = pdev->msi_cap; 1770 } 1771 1772 static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) 1773 { 1774 struct intel_vgpu *vgpu; 1775 int id; 1776 1777 mutex_lock(&gvt->lock); 1778 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) { 1779 if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id, 1780 (void *)&gvt->service_request)) { 1781 if (vgpu->active) 1782 intel_vgpu_emulate_vblank(vgpu); 1783 } 1784 } 1785 mutex_unlock(&gvt->lock); 1786 } 1787 1788 static int gvt_service_thread(void *data) 1789 { 1790 struct intel_gvt *gvt = (struct intel_gvt *)data; 1791 int ret; 1792 1793 gvt_dbg_core("service thread start\n"); 1794 1795 while (!kthread_should_stop()) { 1796 ret = wait_event_interruptible(gvt->service_thread_wq, 1797 kthread_should_stop() || gvt->service_request); 1798 1799 if (kthread_should_stop()) 1800 break; 1801 1802 if (WARN_ONCE(ret, "service thread is waken up by signal.\n")) 1803 continue; 1804 1805 intel_gvt_test_and_emulate_vblank(gvt); 1806 1807 if (test_bit(INTEL_GVT_REQUEST_SCHED, 1808 (void *)&gvt->service_request) || 1809 test_bit(INTEL_GVT_REQUEST_EVENT_SCHED, 1810 (void *)&gvt->service_request)) { 1811 intel_gvt_schedule(gvt); 1812 } 1813 } 1814 1815 return 0; 1816 } 1817 1818 static void clean_service_thread(struct intel_gvt *gvt) 1819 { 1820 kthread_stop(gvt->service_thread); 1821 } 1822 1823 static int init_service_thread(struct intel_gvt *gvt) 1824 { 1825 init_waitqueue_head(&gvt->service_thread_wq); 1826 1827 gvt->service_thread = kthread_run(gvt_service_thread, 1828 gvt, "gvt_service_thread"); 1829 if (IS_ERR(gvt->service_thread)) { 1830 gvt_err("fail to start service thread.\n"); 1831 return PTR_ERR(gvt->service_thread); 1832 } 1833 return 0; 1834 } 1835 1836 /** 1837 * intel_gvt_clean_device - clean a GVT device 1838 * @i915: i915 private 1839 * 1840 * This function is called at the driver unloading stage, to free the 1841 * resources owned by a GVT device. 1842 * 1843 */ 1844 static void intel_gvt_clean_device(struct drm_i915_private *i915) 1845 { 1846 struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); 1847 1848 if (drm_WARN_ON(&i915->drm, !gvt)) 1849 return; 1850 1851 mdev_unregister_parent(&gvt->parent); 1852 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1853 intel_gvt_clean_vgpu_types(gvt); 1854 1855 intel_gvt_debugfs_clean(gvt); 1856 clean_service_thread(gvt); 1857 intel_gvt_clean_cmd_parser(gvt); 1858 intel_gvt_clean_sched_policy(gvt); 1859 intel_gvt_clean_workload_scheduler(gvt); 1860 intel_gvt_clean_gtt(gvt); 1861 intel_gvt_free_firmware(gvt); 1862 intel_gvt_clean_mmio_info(gvt); 1863 idr_destroy(&gvt->vgpu_idr); 1864 1865 kfree(i915->gvt); 1866 } 1867 1868 /** 1869 * intel_gvt_init_device - initialize a GVT device 1870 * @i915: drm i915 private data 1871 * 1872 * This function is called at the initialization stage, to initialize 1873 * necessary GVT components. 1874 * 1875 * Returns: 1876 * Zero on success, negative error code if failed. 1877 * 1878 */ 1879 static int intel_gvt_init_device(struct drm_i915_private *i915) 1880 { 1881 struct intel_gvt *gvt; 1882 struct intel_vgpu *vgpu; 1883 int ret; 1884 1885 if (drm_WARN_ON(&i915->drm, i915->gvt)) 1886 return -EEXIST; 1887 1888 gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL); 1889 if (!gvt) 1890 return -ENOMEM; 1891 1892 gvt_dbg_core("init gvt device\n"); 1893 1894 idr_init_base(&gvt->vgpu_idr, 1); 1895 spin_lock_init(&gvt->scheduler.mmio_context_lock); 1896 mutex_init(&gvt->lock); 1897 mutex_init(&gvt->sched_lock); 1898 gvt->gt = to_gt(i915); 1899 i915->gvt = gvt; 1900 1901 init_device_info(gvt); 1902 1903 ret = intel_gvt_setup_mmio_info(gvt); 1904 if (ret) 1905 goto out_clean_idr; 1906 1907 intel_gvt_init_engine_mmio_context(gvt); 1908 1909 ret = intel_gvt_load_firmware(gvt); 1910 if (ret) 1911 goto out_clean_mmio_info; 1912 1913 ret = intel_gvt_init_irq(gvt); 1914 if (ret) 1915 goto out_free_firmware; 1916 1917 ret = intel_gvt_init_gtt(gvt); 1918 if (ret) 1919 goto out_free_firmware; 1920 1921 ret = intel_gvt_init_workload_scheduler(gvt); 1922 if (ret) 1923 goto out_clean_gtt; 1924 1925 ret = intel_gvt_init_sched_policy(gvt); 1926 if (ret) 1927 goto out_clean_workload_scheduler; 1928 1929 ret = intel_gvt_init_cmd_parser(gvt); 1930 if (ret) 1931 goto out_clean_sched_policy; 1932 1933 ret = init_service_thread(gvt); 1934 if (ret) 1935 goto out_clean_cmd_parser; 1936 1937 ret = intel_gvt_init_vgpu_types(gvt); 1938 if (ret) 1939 goto out_clean_thread; 1940 1941 vgpu = intel_gvt_create_idle_vgpu(gvt); 1942 if (IS_ERR(vgpu)) { 1943 ret = PTR_ERR(vgpu); 1944 gvt_err("failed to create idle vgpu\n"); 1945 goto out_clean_types; 1946 } 1947 gvt->idle_vgpu = vgpu; 1948 1949 intel_gvt_debugfs_init(gvt); 1950 1951 ret = mdev_register_parent(&gvt->parent, i915->drm.dev, 1952 &intel_vgpu_mdev_driver, 1953 gvt->mdev_types, gvt->num_types); 1954 if (ret) 1955 goto out_destroy_idle_vgpu; 1956 1957 gvt_dbg_core("gvt device initialization is done\n"); 1958 return 0; 1959 1960 out_destroy_idle_vgpu: 1961 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1962 intel_gvt_debugfs_clean(gvt); 1963 out_clean_types: 1964 intel_gvt_clean_vgpu_types(gvt); 1965 out_clean_thread: 1966 clean_service_thread(gvt); 1967 out_clean_cmd_parser: 1968 intel_gvt_clean_cmd_parser(gvt); 1969 out_clean_sched_policy: 1970 intel_gvt_clean_sched_policy(gvt); 1971 out_clean_workload_scheduler: 1972 intel_gvt_clean_workload_scheduler(gvt); 1973 out_clean_gtt: 1974 intel_gvt_clean_gtt(gvt); 1975 out_free_firmware: 1976 intel_gvt_free_firmware(gvt); 1977 out_clean_mmio_info: 1978 intel_gvt_clean_mmio_info(gvt); 1979 out_clean_idr: 1980 idr_destroy(&gvt->vgpu_idr); 1981 kfree(gvt); 1982 i915->gvt = NULL; 1983 return ret; 1984 } 1985 1986 static void intel_gvt_pm_resume(struct drm_i915_private *i915) 1987 { 1988 struct intel_gvt *gvt = i915->gvt; 1989 1990 intel_gvt_restore_fence(gvt); 1991 intel_gvt_restore_mmio(gvt); 1992 intel_gvt_restore_ggtt(gvt); 1993 } 1994 1995 static const struct intel_vgpu_ops intel_gvt_vgpu_ops = { 1996 .init_device = intel_gvt_init_device, 1997 .clean_device = intel_gvt_clean_device, 1998 .pm_resume = intel_gvt_pm_resume, 1999 }; 2000 2001 static int __init kvmgt_init(void) 2002 { 2003 int ret; 2004 2005 ret = intel_gvt_set_ops(&intel_gvt_vgpu_ops); 2006 if (ret) 2007 return ret; 2008 2009 ret = mdev_register_driver(&intel_vgpu_mdev_driver); 2010 if (ret) 2011 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 2012 return ret; 2013 } 2014 2015 static void __exit kvmgt_exit(void) 2016 { 2017 mdev_unregister_driver(&intel_vgpu_mdev_driver); 2018 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 2019 } 2020 2021 module_init(kvmgt_init); 2022 module_exit(kvmgt_exit); 2023 2024 MODULE_LICENSE("GPL and additional rights"); 2025 MODULE_AUTHOR("Intel Corporation"); 2026