1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min he <min.he@intel.com> 29 * 30 */ 31 32 #include "i915_drv.h" 33 #include "gvt.h" 34 35 /* common offset among interrupt control registers */ 36 #define regbase_to_isr(base) (base) 37 #define regbase_to_imr(base) (base + 0x4) 38 #define regbase_to_iir(base) (base + 0x8) 39 #define regbase_to_ier(base) (base + 0xC) 40 41 #define iir_to_regbase(iir) (iir - 0x8) 42 #define ier_to_regbase(ier) (ier - 0xC) 43 44 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler) 45 #define get_irq_info(irq, e) (irq->events[e].info) 46 47 #define irq_to_gvt(irq) \ 48 container_of(irq, struct intel_gvt, irq) 49 50 static void update_upstream_irq(struct intel_vgpu *vgpu, 51 struct intel_gvt_irq_info *info); 52 53 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = { 54 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT", 55 [RCS_DEBUG] = "Render EU debug from SVG", 56 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status", 57 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt", 58 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify", 59 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded", 60 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults", 61 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt", 62 63 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT", 64 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status", 65 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt", 66 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify", 67 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded", 68 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults", 69 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt", 70 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT", 71 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify", 72 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt", 73 74 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT", 75 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status", 76 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt", 77 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify", 78 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults", 79 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt", 80 81 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify", 82 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt", 83 84 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun", 85 [PIPE_A_CRC_ERR] = "Pipe A CRC error", 86 [PIPE_A_CRC_DONE] = "Pipe A CRC done", 87 [PIPE_A_VSYNC] = "Pipe A vsync", 88 [PIPE_A_LINE_COMPARE] = "Pipe A line compare", 89 [PIPE_A_ODD_FIELD] = "Pipe A odd field", 90 [PIPE_A_EVEN_FIELD] = "Pipe A even field", 91 [PIPE_A_VBLANK] = "Pipe A vblank", 92 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun", 93 [PIPE_B_CRC_ERR] = "Pipe B CRC error", 94 [PIPE_B_CRC_DONE] = "Pipe B CRC done", 95 [PIPE_B_VSYNC] = "Pipe B vsync", 96 [PIPE_B_LINE_COMPARE] = "Pipe B line compare", 97 [PIPE_B_ODD_FIELD] = "Pipe B odd field", 98 [PIPE_B_EVEN_FIELD] = "Pipe B even field", 99 [PIPE_B_VBLANK] = "Pipe B vblank", 100 [PIPE_C_VBLANK] = "Pipe C vblank", 101 [DPST_PHASE_IN] = "DPST phase in event", 102 [DPST_HISTOGRAM] = "DPST histogram event", 103 [GSE] = "GSE", 104 [DP_A_HOTPLUG] = "DP A Hotplug", 105 [AUX_CHANNEL_A] = "AUX Channel A", 106 [PERF_COUNTER] = "Performance counter", 107 [POISON] = "Poison", 108 [GTT_FAULT] = "GTT fault", 109 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done", 110 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done", 111 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done", 112 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done", 113 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done", 114 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done", 115 116 [PCU_THERMAL] = "PCU Thermal Event", 117 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event", 118 119 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A", 120 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A", 121 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A", 122 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B", 123 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B", 124 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B", 125 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C", 126 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C", 127 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C", 128 [ERR_AND_DBG] = "South Error and Debug Interupts Combined", 129 [GMBUS] = "Gmbus", 130 [SDVO_B_HOTPLUG] = "SDVO B hotplug", 131 [CRT_HOTPLUG] = "CRT Hotplug", 132 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug", 133 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug", 134 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug", 135 [AUX_CHANNEL_B] = "AUX Channel B", 136 [AUX_CHANNEL_C] = "AUX Channel C", 137 [AUX_CHANNEL_D] = "AUX Channel D", 138 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B", 139 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C", 140 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D", 141 142 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!", 143 }; 144 145 static inline struct intel_gvt_irq_info *regbase_to_irq_info( 146 struct intel_gvt *gvt, 147 unsigned int reg) 148 { 149 struct intel_gvt_irq *irq = &gvt->irq; 150 int i; 151 152 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 153 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) 154 return irq->info[i]; 155 } 156 157 return NULL; 158 } 159 160 /** 161 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler 162 * @vgpu: a vGPU 163 * @reg: register offset written by guest 164 * @p_data: register data written by guest 165 * @bytes: register data length 166 * 167 * This function is used to emulate the generic IMR register bit change 168 * behavior. 169 * 170 * Returns: 171 * Zero on success, negative error code if failed. 172 * 173 */ 174 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 175 unsigned int reg, void *p_data, unsigned int bytes) 176 { 177 struct intel_gvt *gvt = vgpu->gvt; 178 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 179 u32 imr = *(u32 *)p_data; 180 181 gvt_dbg_irq("write IMR %x, new %08x, old %08x, changed %08x\n", 182 reg, imr, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ imr); 183 184 vgpu_vreg(vgpu, reg) = imr; 185 186 ops->check_pending_irq(vgpu); 187 188 return 0; 189 } 190 191 /** 192 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler 193 * @vgpu: a vGPU 194 * @reg: register offset written by guest 195 * @p_data: register data written by guest 196 * @bytes: register data length 197 * 198 * This function is used to emulate the master IRQ register on gen8+. 199 * 200 * Returns: 201 * Zero on success, negative error code if failed. 202 * 203 */ 204 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 205 unsigned int reg, void *p_data, unsigned int bytes) 206 { 207 struct intel_gvt *gvt = vgpu->gvt; 208 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 209 u32 ier = *(u32 *)p_data; 210 u32 virtual_ier = vgpu_vreg(vgpu, reg); 211 212 gvt_dbg_irq("write MASTER_IRQ %x, new %08x, old %08x, changed %08x\n", 213 reg, ier, virtual_ier, virtual_ier ^ ier); 214 215 /* 216 * GEN8_MASTER_IRQ is a special irq register, 217 * only bit 31 is allowed to be modified 218 * and treated as an IER bit. 219 */ 220 ier &= GEN8_MASTER_IRQ_CONTROL; 221 virtual_ier &= GEN8_MASTER_IRQ_CONTROL; 222 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; 223 vgpu_vreg(vgpu, reg) |= ier; 224 225 ops->check_pending_irq(vgpu); 226 227 return 0; 228 } 229 230 /** 231 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler 232 * @vgpu: a vGPU 233 * @reg: register offset written by guest 234 * @p_data: register data written by guest 235 * @bytes: register data length 236 * 237 * This function is used to emulate the generic IER register behavior. 238 * 239 * Returns: 240 * Zero on success, negative error code if failed. 241 * 242 */ 243 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 244 unsigned int reg, void *p_data, unsigned int bytes) 245 { 246 struct intel_gvt *gvt = vgpu->gvt; 247 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 248 struct intel_gvt_irq_info *info; 249 u32 ier = *(u32 *)p_data; 250 251 gvt_dbg_irq("write IER %x, new %08x, old %08x, changed %08x\n", 252 reg, ier, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ ier); 253 254 vgpu_vreg(vgpu, reg) = ier; 255 256 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); 257 if (WARN_ON(!info)) 258 return -EINVAL; 259 260 if (info->has_upstream_irq) 261 update_upstream_irq(vgpu, info); 262 263 ops->check_pending_irq(vgpu); 264 265 return 0; 266 } 267 268 /** 269 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler 270 * @vgpu: a vGPU 271 * @reg: register offset written by guest 272 * @p_data: register data written by guest 273 * @bytes: register data length 274 * 275 * This function is used to emulate the generic IIR register behavior. 276 * 277 * Returns: 278 * Zero on success, negative error code if failed. 279 * 280 */ 281 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 282 void *p_data, unsigned int bytes) 283 { 284 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, 285 iir_to_regbase(reg)); 286 u32 iir = *(u32 *)p_data; 287 288 gvt_dbg_irq("write IIR %x, new %08x, old %08x, changed %08x\n", 289 reg, iir, vgpu_vreg(vgpu, reg), vgpu_vreg(vgpu, reg) ^ iir); 290 291 if (WARN_ON(!info)) 292 return -EINVAL; 293 294 vgpu_vreg(vgpu, reg) &= ~iir; 295 296 if (info->has_upstream_irq) 297 update_upstream_irq(vgpu, info); 298 return 0; 299 } 300 301 static struct intel_gvt_irq_map gen8_irq_map[] = { 302 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff }, 303 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 }, 304 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff }, 305 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 }, 306 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff }, 307 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff }, 308 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 }, 309 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 }, 310 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 }, 311 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 }, 312 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 }, 313 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 }, 314 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 }, 315 { -1, -1, ~0 }, 316 }; 317 318 static void update_upstream_irq(struct intel_vgpu *vgpu, 319 struct intel_gvt_irq_info *info) 320 { 321 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 322 struct intel_gvt_irq_map *map = irq->irq_map; 323 struct intel_gvt_irq_info *up_irq_info = NULL; 324 u32 set_bits = 0; 325 u32 clear_bits = 0; 326 int bit; 327 u32 val = vgpu_vreg(vgpu, 328 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) 329 & vgpu_vreg(vgpu, 330 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); 331 332 if (!info->has_upstream_irq) 333 return; 334 335 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 336 if (info->group != map->down_irq_group) 337 continue; 338 339 if (!up_irq_info) 340 up_irq_info = irq->info[map->up_irq_group]; 341 else 342 WARN_ON(up_irq_info != irq->info[map->up_irq_group]); 343 344 bit = map->up_irq_bit; 345 346 if (val & map->down_irq_bitmask) 347 set_bits |= (1 << bit); 348 else 349 clear_bits |= (1 << bit); 350 } 351 352 WARN_ON(!up_irq_info); 353 354 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { 355 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); 356 357 vgpu_vreg(vgpu, isr) &= ~clear_bits; 358 vgpu_vreg(vgpu, isr) |= set_bits; 359 } else { 360 u32 iir = regbase_to_iir( 361 i915_mmio_reg_offset(up_irq_info->reg_base)); 362 u32 imr = regbase_to_imr( 363 i915_mmio_reg_offset(up_irq_info->reg_base)); 364 365 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); 366 } 367 368 if (up_irq_info->has_upstream_irq) 369 update_upstream_irq(vgpu, up_irq_info); 370 } 371 372 static void init_irq_map(struct intel_gvt_irq *irq) 373 { 374 struct intel_gvt_irq_map *map; 375 struct intel_gvt_irq_info *up_info, *down_info; 376 int up_bit; 377 378 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 379 up_info = irq->info[map->up_irq_group]; 380 up_bit = map->up_irq_bit; 381 down_info = irq->info[map->down_irq_group]; 382 383 set_bit(up_bit, up_info->downstream_irq_bitmap); 384 down_info->has_upstream_irq = true; 385 386 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", 387 up_info->group, up_bit, 388 down_info->group, map->down_irq_bitmask); 389 } 390 } 391 392 /* =======================vEvent injection===================== */ 393 static int inject_virtual_interrupt(struct intel_vgpu *vgpu) 394 { 395 return intel_gvt_hypervisor_inject_msi(vgpu); 396 } 397 398 static void propagate_event(struct intel_gvt_irq *irq, 399 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 400 { 401 struct intel_gvt_irq_info *info; 402 unsigned int reg_base; 403 int bit; 404 405 info = get_irq_info(irq, event); 406 if (WARN_ON(!info)) 407 return; 408 409 reg_base = i915_mmio_reg_offset(info->reg_base); 410 bit = irq->events[event].bit; 411 412 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu, 413 regbase_to_imr(reg_base)))) { 414 gvt_dbg_irq("set bit (%d) for (%s) for vgpu (%d)\n", 415 bit, irq_name[event], vgpu->id); 416 set_bit(bit, (void *)&vgpu_vreg(vgpu, 417 regbase_to_iir(reg_base))); 418 } 419 } 420 421 /* =======================vEvent Handlers===================== */ 422 static void handle_default_event_virt(struct intel_gvt_irq *irq, 423 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 424 { 425 if (!vgpu->irq.irq_warn_once[event]) { 426 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", 427 vgpu->id, event, irq_name[event]); 428 vgpu->irq.irq_warn_once[event] = true; 429 } 430 propagate_event(irq, event, vgpu); 431 } 432 433 /* =====================GEN specific logic======================= */ 434 /* GEN8 interrupt routines. */ 435 436 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \ 437 static struct intel_gvt_irq_info gen8_##regname##_info = { \ 438 .name = #regname"-IRQ", \ 439 .reg_base = (regbase), \ 440 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \ 441 INTEL_GVT_EVENT_RESERVED}, \ 442 } 443 444 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0)); 445 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1)); 446 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2)); 447 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3)); 448 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A)); 449 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B)); 450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C)); 451 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR); 452 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR); 453 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR); 454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ); 455 456 static struct intel_gvt_irq_info gvt_base_pch_info = { 457 .name = "PCH-IRQ", 458 .reg_base = SDEISR, 459 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = 460 INTEL_GVT_EVENT_RESERVED}, 461 }; 462 463 static void gen8_check_pending_irq(struct intel_vgpu *vgpu) 464 { 465 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 466 int i; 467 468 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & 469 GEN8_MASTER_IRQ_CONTROL)) 470 return; 471 472 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 473 struct intel_gvt_irq_info *info = irq->info[i]; 474 u32 reg_base; 475 476 if (!info->has_upstream_irq) 477 continue; 478 479 reg_base = i915_mmio_reg_offset(info->reg_base); 480 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base)) 481 & vgpu_vreg(vgpu, regbase_to_ier(reg_base)))) 482 update_upstream_irq(vgpu, info); 483 } 484 485 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) 486 & ~GEN8_MASTER_IRQ_CONTROL) 487 inject_virtual_interrupt(vgpu); 488 } 489 490 static void gen8_init_irq( 491 struct intel_gvt_irq *irq) 492 { 493 struct intel_gvt *gvt = irq_to_gvt(irq); 494 495 #define SET_BIT_INFO(s, b, e, i) \ 496 do { \ 497 s->events[e].bit = b; \ 498 s->events[e].info = s->info[i]; \ 499 s->info[i]->bit_to_event[b] = e;\ 500 } while (0) 501 502 #define SET_IRQ_GROUP(s, g, i) \ 503 do { \ 504 s->info[g] = i; \ 505 (i)->group = g; \ 506 set_bit(g, s->irq_info_bitmap); \ 507 } while (0) 508 509 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info); 510 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info); 511 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info); 512 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info); 513 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info); 514 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info); 515 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info); 516 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info); 517 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info); 518 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info); 519 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info); 520 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info); 521 522 /* GEN8 level 2 interrupts. */ 523 524 /* GEN8 interrupt GT0 events */ 525 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 526 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0); 527 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 528 529 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 530 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0); 531 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 532 533 /* GEN8 interrupt GT1 events */ 534 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1); 535 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); 536 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); 537 538 if (HAS_BSD2(gvt->dev_priv)) { 539 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, 540 INTEL_GVT_IRQ_INFO_GT1); 541 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, 542 INTEL_GVT_IRQ_INFO_GT1); 543 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH, 544 INTEL_GVT_IRQ_INFO_GT1); 545 } 546 547 /* GEN8 interrupt GT3 events */ 548 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3); 549 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3); 550 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3); 551 552 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 553 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 554 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 555 556 /* GEN8 interrupt DE PORT events */ 557 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT); 558 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT); 559 560 /* GEN8 interrupt DE MISC events */ 561 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC); 562 563 /* PCH events */ 564 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH); 565 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 566 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 567 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 568 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 569 570 if (IS_BROADWELL(gvt->dev_priv)) { 571 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH); 572 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH); 573 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH); 574 575 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 576 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 577 578 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 579 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 580 581 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 582 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 583 } else if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv)) { 584 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT); 585 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT); 586 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT); 587 588 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 589 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 590 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 591 592 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 593 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 594 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 595 } 596 597 /* GEN8 interrupt PCU events */ 598 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU); 599 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU); 600 } 601 602 static struct intel_gvt_irq_ops gen8_irq_ops = { 603 .init_irq = gen8_init_irq, 604 .check_pending_irq = gen8_check_pending_irq, 605 }; 606 607 /** 608 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU 609 * @vgpu: a vGPU 610 * @event: interrupt event 611 * 612 * This function is used to trigger a virtual interrupt event for vGPU. 613 * The caller provides the event to be triggered, the framework itself 614 * will emulate the IRQ register bit change. 615 * 616 */ 617 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 618 enum intel_gvt_event_type event) 619 { 620 struct intel_gvt *gvt = vgpu->gvt; 621 struct intel_gvt_irq *irq = &gvt->irq; 622 gvt_event_virt_handler_t handler; 623 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 624 625 handler = get_event_virt_handler(irq, event); 626 WARN_ON(!handler); 627 628 handler(irq, event, vgpu); 629 630 ops->check_pending_irq(vgpu); 631 } 632 633 static void init_events( 634 struct intel_gvt_irq *irq) 635 { 636 int i; 637 638 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) { 639 irq->events[i].info = NULL; 640 irq->events[i].v_handler = handle_default_event_virt; 641 } 642 } 643 644 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 645 { 646 struct intel_gvt_vblank_timer *vblank_timer; 647 struct intel_gvt_irq *irq; 648 struct intel_gvt *gvt; 649 650 vblank_timer = container_of(data, struct intel_gvt_vblank_timer, timer); 651 irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer); 652 gvt = container_of(irq, struct intel_gvt, irq); 653 654 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EMULATE_VBLANK); 655 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 656 return HRTIMER_RESTART; 657 } 658 659 /** 660 * intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem 661 * @gvt: a GVT device 662 * 663 * This function is called at driver unloading stage, to clean up GVT-g IRQ 664 * emulation subsystem. 665 * 666 */ 667 void intel_gvt_clean_irq(struct intel_gvt *gvt) 668 { 669 struct intel_gvt_irq *irq = &gvt->irq; 670 671 hrtimer_cancel(&irq->vblank_timer.timer); 672 } 673 674 #define VBLNAK_TIMER_PERIOD 16000000 675 676 /** 677 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem 678 * @gvt: a GVT device 679 * 680 * This function is called at driver loading stage, to initialize the GVT-g IRQ 681 * emulation subsystem. 682 * 683 * Returns: 684 * Zero on success, negative error code if failed. 685 */ 686 int intel_gvt_init_irq(struct intel_gvt *gvt) 687 { 688 struct intel_gvt_irq *irq = &gvt->irq; 689 struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer; 690 691 gvt_dbg_core("init irq framework\n"); 692 693 if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv) 694 || IS_KABYLAKE(gvt->dev_priv)) { 695 irq->ops = &gen8_irq_ops; 696 irq->irq_map = gen8_irq_map; 697 } else { 698 WARN_ON(1); 699 return -ENODEV; 700 } 701 702 /* common event initialization */ 703 init_events(irq); 704 705 /* gen specific initialization */ 706 irq->ops->init_irq(irq); 707 708 init_irq_map(irq); 709 710 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 711 vblank_timer->timer.function = vblank_timer_fn; 712 vblank_timer->period = VBLNAK_TIMER_PERIOD; 713 714 return 0; 715 } 716