1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min he <min.he@intel.com> 29 * 30 */ 31 32 #include <linux/eventfd.h> 33 34 #include <drm/drm_print.h> 35 36 #include "display/intel_display_regs.h" 37 38 #include "gvt.h" 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "trace.h" 42 43 struct intel_gvt_irq_info { 44 char *name; 45 i915_reg_t reg_base; 46 enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; 47 int group; 48 DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); 49 bool has_upstream_irq; 50 }; 51 52 struct intel_gvt_irq_map { 53 int up_irq_group; 54 int up_irq_bit; 55 int down_irq_group; 56 u32 down_irq_bitmask; 57 }; 58 59 /* common offset among interrupt control registers */ 60 #define regbase_to_isr(base) (base) 61 #define regbase_to_imr(base) (base + 0x4) 62 #define regbase_to_iir(base) (base + 0x8) 63 #define regbase_to_ier(base) (base + 0xC) 64 65 #define iir_to_regbase(iir) (iir - 0x8) 66 #define ier_to_regbase(ier) (ier - 0xC) 67 68 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler) 69 #define get_irq_info(irq, e) (irq->events[e].info) 70 71 #define irq_to_gvt(irq) \ 72 container_of(irq, struct intel_gvt, irq) 73 74 static void update_upstream_irq(struct intel_vgpu *vgpu, 75 struct intel_gvt_irq_info *info); 76 77 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = { 78 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT", 79 [RCS_DEBUG] = "Render EU debug from SVG", 80 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status", 81 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt", 82 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify", 83 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded", 84 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults", 85 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt", 86 87 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT", 88 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status", 89 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt", 90 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify", 91 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded", 92 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults", 93 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt", 94 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT", 95 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify", 96 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt", 97 98 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT", 99 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status", 100 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt", 101 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify", 102 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults", 103 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt", 104 105 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify", 106 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt", 107 108 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun", 109 [PIPE_A_CRC_ERR] = "Pipe A CRC error", 110 [PIPE_A_CRC_DONE] = "Pipe A CRC done", 111 [PIPE_A_VSYNC] = "Pipe A vsync", 112 [PIPE_A_LINE_COMPARE] = "Pipe A line compare", 113 [PIPE_A_ODD_FIELD] = "Pipe A odd field", 114 [PIPE_A_EVEN_FIELD] = "Pipe A even field", 115 [PIPE_A_VBLANK] = "Pipe A vblank", 116 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun", 117 [PIPE_B_CRC_ERR] = "Pipe B CRC error", 118 [PIPE_B_CRC_DONE] = "Pipe B CRC done", 119 [PIPE_B_VSYNC] = "Pipe B vsync", 120 [PIPE_B_LINE_COMPARE] = "Pipe B line compare", 121 [PIPE_B_ODD_FIELD] = "Pipe B odd field", 122 [PIPE_B_EVEN_FIELD] = "Pipe B even field", 123 [PIPE_B_VBLANK] = "Pipe B vblank", 124 [PIPE_C_VBLANK] = "Pipe C vblank", 125 [DPST_PHASE_IN] = "DPST phase in event", 126 [DPST_HISTOGRAM] = "DPST histogram event", 127 [GSE] = "GSE", 128 [DP_A_HOTPLUG] = "DP A Hotplug", 129 [AUX_CHANNEL_A] = "AUX Channel A", 130 [PERF_COUNTER] = "Performance counter", 131 [POISON] = "Poison", 132 [GTT_FAULT] = "GTT fault", 133 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done", 134 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done", 135 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done", 136 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done", 137 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done", 138 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done", 139 140 [PCU_THERMAL] = "PCU Thermal Event", 141 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event", 142 143 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A", 144 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A", 145 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A", 146 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B", 147 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B", 148 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B", 149 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C", 150 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C", 151 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C", 152 [ERR_AND_DBG] = "South Error and Debug Interrupts Combined", 153 [GMBUS] = "Gmbus", 154 [SDVO_B_HOTPLUG] = "SDVO B hotplug", 155 [CRT_HOTPLUG] = "CRT Hotplug", 156 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug", 157 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug", 158 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug", 159 [AUX_CHANNEL_B] = "AUX Channel B", 160 [AUX_CHANNEL_C] = "AUX Channel C", 161 [AUX_CHANNEL_D] = "AUX Channel D", 162 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B", 163 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C", 164 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D", 165 166 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!", 167 }; 168 169 static inline struct intel_gvt_irq_info *regbase_to_irq_info( 170 struct intel_gvt *gvt, 171 unsigned int reg) 172 { 173 struct intel_gvt_irq *irq = &gvt->irq; 174 int i; 175 176 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 177 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) 178 return irq->info[i]; 179 } 180 181 return NULL; 182 } 183 184 /** 185 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler 186 * @vgpu: a vGPU 187 * @reg: register offset written by guest 188 * @p_data: register data written by guest 189 * @bytes: register data length 190 * 191 * This function is used to emulate the generic IMR register bit change 192 * behavior. 193 * 194 * Returns: 195 * Zero on success, negative error code if failed. 196 * 197 */ 198 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 199 unsigned int reg, void *p_data, unsigned int bytes) 200 { 201 struct intel_gvt *gvt = vgpu->gvt; 202 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 203 u32 imr = *(u32 *)p_data; 204 205 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), 206 (vgpu_vreg(vgpu, reg) ^ imr)); 207 208 vgpu_vreg(vgpu, reg) = imr; 209 210 ops->check_pending_irq(vgpu); 211 212 return 0; 213 } 214 215 /** 216 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler 217 * @vgpu: a vGPU 218 * @reg: register offset written by guest 219 * @p_data: register data written by guest 220 * @bytes: register data length 221 * 222 * This function is used to emulate the master IRQ register on gen8+. 223 * 224 * Returns: 225 * Zero on success, negative error code if failed. 226 * 227 */ 228 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 229 unsigned int reg, void *p_data, unsigned int bytes) 230 { 231 struct intel_gvt *gvt = vgpu->gvt; 232 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 233 u32 ier = *(u32 *)p_data; 234 u32 virtual_ier = vgpu_vreg(vgpu, reg); 235 236 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier, 237 (virtual_ier ^ ier)); 238 239 /* 240 * GEN8_MASTER_IRQ is a special irq register, 241 * only bit 31 is allowed to be modified 242 * and treated as an IER bit. 243 */ 244 ier &= GEN8_MASTER_IRQ_CONTROL; 245 virtual_ier &= GEN8_MASTER_IRQ_CONTROL; 246 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; 247 vgpu_vreg(vgpu, reg) |= ier; 248 249 ops->check_pending_irq(vgpu); 250 251 return 0; 252 } 253 254 /** 255 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler 256 * @vgpu: a vGPU 257 * @reg: register offset written by guest 258 * @p_data: register data written by guest 259 * @bytes: register data length 260 * 261 * This function is used to emulate the generic IER register behavior. 262 * 263 * Returns: 264 * Zero on success, negative error code if failed. 265 * 266 */ 267 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 268 unsigned int reg, void *p_data, unsigned int bytes) 269 { 270 struct intel_gvt *gvt = vgpu->gvt; 271 struct drm_i915_private *i915 = gvt->gt->i915; 272 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 273 struct intel_gvt_irq_info *info; 274 u32 ier = *(u32 *)p_data; 275 276 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), 277 (vgpu_vreg(vgpu, reg) ^ ier)); 278 279 vgpu_vreg(vgpu, reg) = ier; 280 281 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); 282 if (drm_WARN_ON(&i915->drm, !info)) 283 return -EINVAL; 284 285 if (info->has_upstream_irq) 286 update_upstream_irq(vgpu, info); 287 288 ops->check_pending_irq(vgpu); 289 290 return 0; 291 } 292 293 /** 294 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler 295 * @vgpu: a vGPU 296 * @reg: register offset written by guest 297 * @p_data: register data written by guest 298 * @bytes: register data length 299 * 300 * This function is used to emulate the generic IIR register behavior. 301 * 302 * Returns: 303 * Zero on success, negative error code if failed. 304 * 305 */ 306 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 307 void *p_data, unsigned int bytes) 308 { 309 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 310 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, 311 iir_to_regbase(reg)); 312 u32 iir = *(u32 *)p_data; 313 314 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), 315 (vgpu_vreg(vgpu, reg) ^ iir)); 316 317 if (drm_WARN_ON(&i915->drm, !info)) 318 return -EINVAL; 319 320 vgpu_vreg(vgpu, reg) &= ~iir; 321 322 if (info->has_upstream_irq) 323 update_upstream_irq(vgpu, info); 324 return 0; 325 } 326 327 static struct intel_gvt_irq_map gen8_irq_map[] = { 328 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff }, 329 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 }, 330 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff }, 331 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 }, 332 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff }, 333 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff }, 334 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 }, 335 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 }, 336 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 }, 337 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 }, 338 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 }, 339 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 }, 340 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 }, 341 { -1, -1, ~0 }, 342 }; 343 344 static void update_upstream_irq(struct intel_vgpu *vgpu, 345 struct intel_gvt_irq_info *info) 346 { 347 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 348 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 349 struct intel_gvt_irq_map *map = irq->irq_map; 350 struct intel_gvt_irq_info *up_irq_info = NULL; 351 u32 set_bits = 0; 352 u32 clear_bits = 0; 353 int bit; 354 u32 val = vgpu_vreg(vgpu, 355 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) 356 & vgpu_vreg(vgpu, 357 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); 358 359 if (!info->has_upstream_irq) 360 return; 361 362 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 363 if (info->group != map->down_irq_group) 364 continue; 365 366 if (!up_irq_info) 367 up_irq_info = irq->info[map->up_irq_group]; 368 else 369 drm_WARN_ON(&i915->drm, up_irq_info != 370 irq->info[map->up_irq_group]); 371 372 bit = map->up_irq_bit; 373 374 if (val & map->down_irq_bitmask) 375 set_bits |= (1 << bit); 376 else 377 clear_bits |= (1 << bit); 378 } 379 380 if (drm_WARN_ON(&i915->drm, !up_irq_info)) 381 return; 382 383 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { 384 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); 385 386 vgpu_vreg(vgpu, isr) &= ~clear_bits; 387 vgpu_vreg(vgpu, isr) |= set_bits; 388 } else { 389 u32 iir = regbase_to_iir( 390 i915_mmio_reg_offset(up_irq_info->reg_base)); 391 u32 imr = regbase_to_imr( 392 i915_mmio_reg_offset(up_irq_info->reg_base)); 393 394 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); 395 } 396 397 if (up_irq_info->has_upstream_irq) 398 update_upstream_irq(vgpu, up_irq_info); 399 } 400 401 static void init_irq_map(struct intel_gvt_irq *irq) 402 { 403 struct intel_gvt_irq_map *map; 404 struct intel_gvt_irq_info *up_info, *down_info; 405 int up_bit; 406 407 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 408 up_info = irq->info[map->up_irq_group]; 409 up_bit = map->up_irq_bit; 410 down_info = irq->info[map->down_irq_group]; 411 412 set_bit(up_bit, up_info->downstream_irq_bitmap); 413 down_info->has_upstream_irq = true; 414 415 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", 416 up_info->group, up_bit, 417 down_info->group, map->down_irq_bitmask); 418 } 419 } 420 421 /* =======================vEvent injection===================== */ 422 423 #define MSI_CAP_CONTROL(offset) (offset + 2) 424 #define MSI_CAP_ADDRESS(offset) (offset + 4) 425 #define MSI_CAP_DATA(offset) (offset + 8) 426 #define MSI_CAP_EN 0x1 427 428 static void inject_virtual_interrupt(struct intel_vgpu *vgpu) 429 { 430 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset; 431 u16 control, data; 432 u32 addr; 433 434 control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset)); 435 addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset)); 436 data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset)); 437 438 /* Do not generate MSI if MSIEN is disabled */ 439 if (!(control & MSI_CAP_EN)) 440 return; 441 442 if (WARN(control & GENMASK(15, 1), "only support one MSI format\n")) 443 return; 444 445 trace_inject_msi(vgpu->id, addr, data); 446 447 /* 448 * When guest is powered off, msi_trigger is set to NULL, but vgpu's 449 * config and mmio register isn't restored to default during guest 450 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe 451 * may be enabled, then once this vgpu is active, it will get inject 452 * vblank interrupt request. But msi_trigger is null until msi is 453 * enabled by guest. so if msi_trigger is null, success is still 454 * returned and don't inject interrupt into guest. 455 */ 456 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) 457 return; 458 if (vgpu->msi_trigger) 459 eventfd_signal(vgpu->msi_trigger); 460 } 461 462 static void propagate_event(struct intel_gvt_irq *irq, 463 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 464 { 465 struct intel_gvt_irq_info *info; 466 unsigned int reg_base; 467 int bit; 468 469 info = get_irq_info(irq, event); 470 if (WARN_ON(!info)) 471 return; 472 473 reg_base = i915_mmio_reg_offset(info->reg_base); 474 bit = irq->events[event].bit; 475 476 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu, 477 regbase_to_imr(reg_base)))) { 478 trace_propagate_event(vgpu->id, irq_name[event], bit); 479 set_bit(bit, (void *)&vgpu_vreg(vgpu, 480 regbase_to_iir(reg_base))); 481 } 482 } 483 484 /* =======================vEvent Handlers===================== */ 485 static void handle_default_event_virt(struct intel_gvt_irq *irq, 486 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 487 { 488 if (!vgpu->irq.irq_warn_once[event]) { 489 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", 490 vgpu->id, event, irq_name[event]); 491 vgpu->irq.irq_warn_once[event] = true; 492 } 493 propagate_event(irq, event, vgpu); 494 } 495 496 /* =====================GEN specific logic======================= */ 497 /* GEN8 interrupt routines. */ 498 499 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \ 500 static struct intel_gvt_irq_info gen8_##regname##_info = { \ 501 .name = #regname"-IRQ", \ 502 .reg_base = (regbase), \ 503 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \ 504 INTEL_GVT_EVENT_RESERVED}, \ 505 } 506 507 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0)); 508 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1)); 509 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2)); 510 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3)); 511 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A)); 512 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B)); 513 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C)); 514 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR); 515 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR); 516 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR); 517 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ); 518 519 static struct intel_gvt_irq_info gvt_base_pch_info = { 520 .name = "PCH-IRQ", 521 .reg_base = SDEISR, 522 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = 523 INTEL_GVT_EVENT_RESERVED}, 524 }; 525 526 static void gen8_check_pending_irq(struct intel_vgpu *vgpu) 527 { 528 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 529 int i; 530 531 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & 532 GEN8_MASTER_IRQ_CONTROL)) 533 return; 534 535 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 536 struct intel_gvt_irq_info *info = irq->info[i]; 537 u32 reg_base; 538 539 if (!info->has_upstream_irq) 540 continue; 541 542 reg_base = i915_mmio_reg_offset(info->reg_base); 543 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base)) 544 & vgpu_vreg(vgpu, regbase_to_ier(reg_base)))) 545 update_upstream_irq(vgpu, info); 546 } 547 548 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) 549 & ~GEN8_MASTER_IRQ_CONTROL) 550 inject_virtual_interrupt(vgpu); 551 } 552 553 static void gen8_init_irq( 554 struct intel_gvt_irq *irq) 555 { 556 struct intel_gvt *gvt = irq_to_gvt(irq); 557 558 #define SET_BIT_INFO(s, b, e, i) \ 559 do { \ 560 s->events[e].bit = b; \ 561 s->events[e].info = s->info[i]; \ 562 s->info[i]->bit_to_event[b] = e;\ 563 } while (0) 564 565 #define SET_IRQ_GROUP(s, g, i) \ 566 do { \ 567 s->info[g] = i; \ 568 (i)->group = g; \ 569 set_bit(g, s->irq_info_bitmap); \ 570 } while (0) 571 572 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info); 573 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info); 574 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info); 575 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info); 576 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info); 577 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info); 578 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info); 579 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info); 580 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info); 581 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info); 582 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info); 583 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info); 584 585 /* GEN8 level 2 interrupts. */ 586 587 /* GEN8 interrupt GT0 events */ 588 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 589 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0); 590 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 591 592 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 593 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0); 594 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 595 596 /* GEN8 interrupt GT1 events */ 597 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1); 598 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); 599 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); 600 601 if (HAS_ENGINE(gvt->gt, VCS1)) { 602 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, 603 INTEL_GVT_IRQ_INFO_GT1); 604 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, 605 INTEL_GVT_IRQ_INFO_GT1); 606 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH, 607 INTEL_GVT_IRQ_INFO_GT1); 608 } 609 610 /* GEN8 interrupt GT3 events */ 611 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3); 612 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3); 613 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3); 614 615 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 616 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 617 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 618 619 /* GEN8 interrupt DE PORT events */ 620 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT); 621 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT); 622 623 /* GEN8 interrupt DE MISC events */ 624 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC); 625 626 /* PCH events */ 627 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH); 628 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 629 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 630 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 631 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 632 633 if (IS_BROADWELL(gvt->gt->i915)) { 634 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH); 635 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH); 636 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH); 637 638 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 639 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 640 641 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 642 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 643 644 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 645 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 646 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) { 647 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT); 648 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT); 649 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT); 650 651 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 652 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 653 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 654 655 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 656 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 657 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 658 } 659 660 /* GEN8 interrupt PCU events */ 661 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU); 662 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU); 663 } 664 665 static const struct intel_gvt_irq_ops gen8_irq_ops = { 666 .init_irq = gen8_init_irq, 667 .check_pending_irq = gen8_check_pending_irq, 668 }; 669 670 /** 671 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU 672 * @vgpu: a vGPU 673 * @event: interrupt event 674 * 675 * This function is used to trigger a virtual interrupt event for vGPU. 676 * The caller provides the event to be triggered, the framework itself 677 * will emulate the IRQ register bit change. 678 * 679 */ 680 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 681 enum intel_gvt_event_type event) 682 { 683 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 684 struct intel_gvt *gvt = vgpu->gvt; 685 struct intel_gvt_irq *irq = &gvt->irq; 686 gvt_event_virt_handler_t handler; 687 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 688 689 handler = get_event_virt_handler(irq, event); 690 drm_WARN_ON(&i915->drm, !handler); 691 692 handler(irq, event, vgpu); 693 694 ops->check_pending_irq(vgpu); 695 } 696 697 static void init_events( 698 struct intel_gvt_irq *irq) 699 { 700 int i; 701 702 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) { 703 irq->events[i].info = NULL; 704 irq->events[i].v_handler = handle_default_event_virt; 705 } 706 } 707 708 /** 709 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem 710 * @gvt: a GVT device 711 * 712 * This function is called at driver loading stage, to initialize the GVT-g IRQ 713 * emulation subsystem. 714 * 715 * Returns: 716 * Zero on success, negative error code if failed. 717 */ 718 int intel_gvt_init_irq(struct intel_gvt *gvt) 719 { 720 struct intel_gvt_irq *irq = &gvt->irq; 721 722 gvt_dbg_core("init irq framework\n"); 723 724 irq->ops = &gen8_irq_ops; 725 irq->irq_map = gen8_irq_map; 726 727 /* common event initialization */ 728 init_events(irq); 729 730 /* gen specific initialization */ 731 irq->ops->init_irq(irq); 732 733 init_irq_map(irq); 734 735 return 0; 736 } 737