1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min he <min.he@intel.com> 29 * 30 */ 31 32 #include <linux/eventfd.h> 33 34 #include <drm/drm_print.h> 35 36 #include "i915_drv.h" 37 #include "i915_reg.h" 38 #include "display/intel_display_regs.h" 39 #include "gvt.h" 40 #include "trace.h" 41 42 struct intel_gvt_irq_info { 43 char *name; 44 i915_reg_t reg_base; 45 enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; 46 int group; 47 DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); 48 bool has_upstream_irq; 49 }; 50 51 struct intel_gvt_irq_map { 52 int up_irq_group; 53 int up_irq_bit; 54 int down_irq_group; 55 u32 down_irq_bitmask; 56 }; 57 58 /* common offset among interrupt control registers */ 59 #define regbase_to_isr(base) (base) 60 #define regbase_to_imr(base) (base + 0x4) 61 #define regbase_to_iir(base) (base + 0x8) 62 #define regbase_to_ier(base) (base + 0xC) 63 64 #define iir_to_regbase(iir) (iir - 0x8) 65 #define ier_to_regbase(ier) (ier - 0xC) 66 67 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler) 68 #define get_irq_info(irq, e) (irq->events[e].info) 69 70 #define irq_to_gvt(irq) \ 71 container_of(irq, struct intel_gvt, irq) 72 73 static void update_upstream_irq(struct intel_vgpu *vgpu, 74 struct intel_gvt_irq_info *info); 75 76 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = { 77 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT", 78 [RCS_DEBUG] = "Render EU debug from SVG", 79 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status", 80 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt", 81 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify", 82 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded", 83 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults", 84 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt", 85 86 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT", 87 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status", 88 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt", 89 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify", 90 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded", 91 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults", 92 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt", 93 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT", 94 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify", 95 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt", 96 97 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT", 98 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status", 99 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt", 100 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify", 101 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults", 102 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt", 103 104 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify", 105 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt", 106 107 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun", 108 [PIPE_A_CRC_ERR] = "Pipe A CRC error", 109 [PIPE_A_CRC_DONE] = "Pipe A CRC done", 110 [PIPE_A_VSYNC] = "Pipe A vsync", 111 [PIPE_A_LINE_COMPARE] = "Pipe A line compare", 112 [PIPE_A_ODD_FIELD] = "Pipe A odd field", 113 [PIPE_A_EVEN_FIELD] = "Pipe A even field", 114 [PIPE_A_VBLANK] = "Pipe A vblank", 115 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun", 116 [PIPE_B_CRC_ERR] = "Pipe B CRC error", 117 [PIPE_B_CRC_DONE] = "Pipe B CRC done", 118 [PIPE_B_VSYNC] = "Pipe B vsync", 119 [PIPE_B_LINE_COMPARE] = "Pipe B line compare", 120 [PIPE_B_ODD_FIELD] = "Pipe B odd field", 121 [PIPE_B_EVEN_FIELD] = "Pipe B even field", 122 [PIPE_B_VBLANK] = "Pipe B vblank", 123 [PIPE_C_VBLANK] = "Pipe C vblank", 124 [DPST_PHASE_IN] = "DPST phase in event", 125 [DPST_HISTOGRAM] = "DPST histogram event", 126 [GSE] = "GSE", 127 [DP_A_HOTPLUG] = "DP A Hotplug", 128 [AUX_CHANNEL_A] = "AUX Channel A", 129 [PERF_COUNTER] = "Performance counter", 130 [POISON] = "Poison", 131 [GTT_FAULT] = "GTT fault", 132 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done", 133 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done", 134 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done", 135 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done", 136 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done", 137 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done", 138 139 [PCU_THERMAL] = "PCU Thermal Event", 140 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event", 141 142 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A", 143 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A", 144 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A", 145 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B", 146 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B", 147 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B", 148 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C", 149 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C", 150 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C", 151 [ERR_AND_DBG] = "South Error and Debug Interrupts Combined", 152 [GMBUS] = "Gmbus", 153 [SDVO_B_HOTPLUG] = "SDVO B hotplug", 154 [CRT_HOTPLUG] = "CRT Hotplug", 155 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug", 156 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug", 157 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug", 158 [AUX_CHANNEL_B] = "AUX Channel B", 159 [AUX_CHANNEL_C] = "AUX Channel C", 160 [AUX_CHANNEL_D] = "AUX Channel D", 161 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B", 162 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C", 163 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D", 164 165 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!", 166 }; 167 168 static inline struct intel_gvt_irq_info *regbase_to_irq_info( 169 struct intel_gvt *gvt, 170 unsigned int reg) 171 { 172 struct intel_gvt_irq *irq = &gvt->irq; 173 int i; 174 175 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 176 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) 177 return irq->info[i]; 178 } 179 180 return NULL; 181 } 182 183 /** 184 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler 185 * @vgpu: a vGPU 186 * @reg: register offset written by guest 187 * @p_data: register data written by guest 188 * @bytes: register data length 189 * 190 * This function is used to emulate the generic IMR register bit change 191 * behavior. 192 * 193 * Returns: 194 * Zero on success, negative error code if failed. 195 * 196 */ 197 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 198 unsigned int reg, void *p_data, unsigned int bytes) 199 { 200 struct intel_gvt *gvt = vgpu->gvt; 201 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 202 u32 imr = *(u32 *)p_data; 203 204 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), 205 (vgpu_vreg(vgpu, reg) ^ imr)); 206 207 vgpu_vreg(vgpu, reg) = imr; 208 209 ops->check_pending_irq(vgpu); 210 211 return 0; 212 } 213 214 /** 215 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler 216 * @vgpu: a vGPU 217 * @reg: register offset written by guest 218 * @p_data: register data written by guest 219 * @bytes: register data length 220 * 221 * This function is used to emulate the master IRQ register on gen8+. 222 * 223 * Returns: 224 * Zero on success, negative error code if failed. 225 * 226 */ 227 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 228 unsigned int reg, void *p_data, unsigned int bytes) 229 { 230 struct intel_gvt *gvt = vgpu->gvt; 231 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 232 u32 ier = *(u32 *)p_data; 233 u32 virtual_ier = vgpu_vreg(vgpu, reg); 234 235 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier, 236 (virtual_ier ^ ier)); 237 238 /* 239 * GEN8_MASTER_IRQ is a special irq register, 240 * only bit 31 is allowed to be modified 241 * and treated as an IER bit. 242 */ 243 ier &= GEN8_MASTER_IRQ_CONTROL; 244 virtual_ier &= GEN8_MASTER_IRQ_CONTROL; 245 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; 246 vgpu_vreg(vgpu, reg) |= ier; 247 248 ops->check_pending_irq(vgpu); 249 250 return 0; 251 } 252 253 /** 254 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler 255 * @vgpu: a vGPU 256 * @reg: register offset written by guest 257 * @p_data: register data written by guest 258 * @bytes: register data length 259 * 260 * This function is used to emulate the generic IER register behavior. 261 * 262 * Returns: 263 * Zero on success, negative error code if failed. 264 * 265 */ 266 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 267 unsigned int reg, void *p_data, unsigned int bytes) 268 { 269 struct intel_gvt *gvt = vgpu->gvt; 270 struct drm_i915_private *i915 = gvt->gt->i915; 271 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 272 struct intel_gvt_irq_info *info; 273 u32 ier = *(u32 *)p_data; 274 275 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), 276 (vgpu_vreg(vgpu, reg) ^ ier)); 277 278 vgpu_vreg(vgpu, reg) = ier; 279 280 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); 281 if (drm_WARN_ON(&i915->drm, !info)) 282 return -EINVAL; 283 284 if (info->has_upstream_irq) 285 update_upstream_irq(vgpu, info); 286 287 ops->check_pending_irq(vgpu); 288 289 return 0; 290 } 291 292 /** 293 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler 294 * @vgpu: a vGPU 295 * @reg: register offset written by guest 296 * @p_data: register data written by guest 297 * @bytes: register data length 298 * 299 * This function is used to emulate the generic IIR register behavior. 300 * 301 * Returns: 302 * Zero on success, negative error code if failed. 303 * 304 */ 305 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 306 void *p_data, unsigned int bytes) 307 { 308 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 309 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, 310 iir_to_regbase(reg)); 311 u32 iir = *(u32 *)p_data; 312 313 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), 314 (vgpu_vreg(vgpu, reg) ^ iir)); 315 316 if (drm_WARN_ON(&i915->drm, !info)) 317 return -EINVAL; 318 319 vgpu_vreg(vgpu, reg) &= ~iir; 320 321 if (info->has_upstream_irq) 322 update_upstream_irq(vgpu, info); 323 return 0; 324 } 325 326 static struct intel_gvt_irq_map gen8_irq_map[] = { 327 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff }, 328 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 }, 329 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff }, 330 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 }, 331 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff }, 332 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff }, 333 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 }, 334 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 }, 335 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 }, 336 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 }, 337 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 }, 338 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 }, 339 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 }, 340 { -1, -1, ~0 }, 341 }; 342 343 static void update_upstream_irq(struct intel_vgpu *vgpu, 344 struct intel_gvt_irq_info *info) 345 { 346 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 347 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 348 struct intel_gvt_irq_map *map = irq->irq_map; 349 struct intel_gvt_irq_info *up_irq_info = NULL; 350 u32 set_bits = 0; 351 u32 clear_bits = 0; 352 int bit; 353 u32 val = vgpu_vreg(vgpu, 354 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) 355 & vgpu_vreg(vgpu, 356 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); 357 358 if (!info->has_upstream_irq) 359 return; 360 361 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 362 if (info->group != map->down_irq_group) 363 continue; 364 365 if (!up_irq_info) 366 up_irq_info = irq->info[map->up_irq_group]; 367 else 368 drm_WARN_ON(&i915->drm, up_irq_info != 369 irq->info[map->up_irq_group]); 370 371 bit = map->up_irq_bit; 372 373 if (val & map->down_irq_bitmask) 374 set_bits |= (1 << bit); 375 else 376 clear_bits |= (1 << bit); 377 } 378 379 if (drm_WARN_ON(&i915->drm, !up_irq_info)) 380 return; 381 382 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { 383 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); 384 385 vgpu_vreg(vgpu, isr) &= ~clear_bits; 386 vgpu_vreg(vgpu, isr) |= set_bits; 387 } else { 388 u32 iir = regbase_to_iir( 389 i915_mmio_reg_offset(up_irq_info->reg_base)); 390 u32 imr = regbase_to_imr( 391 i915_mmio_reg_offset(up_irq_info->reg_base)); 392 393 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); 394 } 395 396 if (up_irq_info->has_upstream_irq) 397 update_upstream_irq(vgpu, up_irq_info); 398 } 399 400 static void init_irq_map(struct intel_gvt_irq *irq) 401 { 402 struct intel_gvt_irq_map *map; 403 struct intel_gvt_irq_info *up_info, *down_info; 404 int up_bit; 405 406 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 407 up_info = irq->info[map->up_irq_group]; 408 up_bit = map->up_irq_bit; 409 down_info = irq->info[map->down_irq_group]; 410 411 set_bit(up_bit, up_info->downstream_irq_bitmap); 412 down_info->has_upstream_irq = true; 413 414 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", 415 up_info->group, up_bit, 416 down_info->group, map->down_irq_bitmask); 417 } 418 } 419 420 /* =======================vEvent injection===================== */ 421 422 #define MSI_CAP_CONTROL(offset) (offset + 2) 423 #define MSI_CAP_ADDRESS(offset) (offset + 4) 424 #define MSI_CAP_DATA(offset) (offset + 8) 425 #define MSI_CAP_EN 0x1 426 427 static void inject_virtual_interrupt(struct intel_vgpu *vgpu) 428 { 429 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset; 430 u16 control, data; 431 u32 addr; 432 433 control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset)); 434 addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset)); 435 data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset)); 436 437 /* Do not generate MSI if MSIEN is disabled */ 438 if (!(control & MSI_CAP_EN)) 439 return; 440 441 if (WARN(control & GENMASK(15, 1), "only support one MSI format\n")) 442 return; 443 444 trace_inject_msi(vgpu->id, addr, data); 445 446 /* 447 * When guest is powered off, msi_trigger is set to NULL, but vgpu's 448 * config and mmio register isn't restored to default during guest 449 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe 450 * may be enabled, then once this vgpu is active, it will get inject 451 * vblank interrupt request. But msi_trigger is null until msi is 452 * enabled by guest. so if msi_trigger is null, success is still 453 * returned and don't inject interrupt into guest. 454 */ 455 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) 456 return; 457 if (vgpu->msi_trigger) 458 eventfd_signal(vgpu->msi_trigger); 459 } 460 461 static void propagate_event(struct intel_gvt_irq *irq, 462 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 463 { 464 struct intel_gvt_irq_info *info; 465 unsigned int reg_base; 466 int bit; 467 468 info = get_irq_info(irq, event); 469 if (WARN_ON(!info)) 470 return; 471 472 reg_base = i915_mmio_reg_offset(info->reg_base); 473 bit = irq->events[event].bit; 474 475 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu, 476 regbase_to_imr(reg_base)))) { 477 trace_propagate_event(vgpu->id, irq_name[event], bit); 478 set_bit(bit, (void *)&vgpu_vreg(vgpu, 479 regbase_to_iir(reg_base))); 480 } 481 } 482 483 /* =======================vEvent Handlers===================== */ 484 static void handle_default_event_virt(struct intel_gvt_irq *irq, 485 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 486 { 487 if (!vgpu->irq.irq_warn_once[event]) { 488 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", 489 vgpu->id, event, irq_name[event]); 490 vgpu->irq.irq_warn_once[event] = true; 491 } 492 propagate_event(irq, event, vgpu); 493 } 494 495 /* =====================GEN specific logic======================= */ 496 /* GEN8 interrupt routines. */ 497 498 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \ 499 static struct intel_gvt_irq_info gen8_##regname##_info = { \ 500 .name = #regname"-IRQ", \ 501 .reg_base = (regbase), \ 502 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \ 503 INTEL_GVT_EVENT_RESERVED}, \ 504 } 505 506 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0)); 507 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1)); 508 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2)); 509 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3)); 510 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A)); 511 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B)); 512 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C)); 513 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR); 514 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR); 515 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR); 516 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ); 517 518 static struct intel_gvt_irq_info gvt_base_pch_info = { 519 .name = "PCH-IRQ", 520 .reg_base = SDEISR, 521 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = 522 INTEL_GVT_EVENT_RESERVED}, 523 }; 524 525 static void gen8_check_pending_irq(struct intel_vgpu *vgpu) 526 { 527 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 528 int i; 529 530 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & 531 GEN8_MASTER_IRQ_CONTROL)) 532 return; 533 534 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 535 struct intel_gvt_irq_info *info = irq->info[i]; 536 u32 reg_base; 537 538 if (!info->has_upstream_irq) 539 continue; 540 541 reg_base = i915_mmio_reg_offset(info->reg_base); 542 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base)) 543 & vgpu_vreg(vgpu, regbase_to_ier(reg_base)))) 544 update_upstream_irq(vgpu, info); 545 } 546 547 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) 548 & ~GEN8_MASTER_IRQ_CONTROL) 549 inject_virtual_interrupt(vgpu); 550 } 551 552 static void gen8_init_irq( 553 struct intel_gvt_irq *irq) 554 { 555 struct intel_gvt *gvt = irq_to_gvt(irq); 556 557 #define SET_BIT_INFO(s, b, e, i) \ 558 do { \ 559 s->events[e].bit = b; \ 560 s->events[e].info = s->info[i]; \ 561 s->info[i]->bit_to_event[b] = e;\ 562 } while (0) 563 564 #define SET_IRQ_GROUP(s, g, i) \ 565 do { \ 566 s->info[g] = i; \ 567 (i)->group = g; \ 568 set_bit(g, s->irq_info_bitmap); \ 569 } while (0) 570 571 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info); 572 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info); 573 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info); 574 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info); 575 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info); 576 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info); 577 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info); 578 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info); 579 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info); 580 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info); 581 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info); 582 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info); 583 584 /* GEN8 level 2 interrupts. */ 585 586 /* GEN8 interrupt GT0 events */ 587 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 588 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0); 589 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 590 591 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 592 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0); 593 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 594 595 /* GEN8 interrupt GT1 events */ 596 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1); 597 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); 598 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); 599 600 if (HAS_ENGINE(gvt->gt, VCS1)) { 601 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, 602 INTEL_GVT_IRQ_INFO_GT1); 603 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, 604 INTEL_GVT_IRQ_INFO_GT1); 605 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH, 606 INTEL_GVT_IRQ_INFO_GT1); 607 } 608 609 /* GEN8 interrupt GT3 events */ 610 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3); 611 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3); 612 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3); 613 614 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 615 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 616 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 617 618 /* GEN8 interrupt DE PORT events */ 619 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT); 620 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT); 621 622 /* GEN8 interrupt DE MISC events */ 623 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC); 624 625 /* PCH events */ 626 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH); 627 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 628 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 629 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 630 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 631 632 if (IS_BROADWELL(gvt->gt->i915)) { 633 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH); 634 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH); 635 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH); 636 637 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 638 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 639 640 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 641 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 642 643 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 644 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 645 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) { 646 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT); 647 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT); 648 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT); 649 650 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 651 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 652 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 653 654 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 655 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 656 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 657 } 658 659 /* GEN8 interrupt PCU events */ 660 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU); 661 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU); 662 } 663 664 static const struct intel_gvt_irq_ops gen8_irq_ops = { 665 .init_irq = gen8_init_irq, 666 .check_pending_irq = gen8_check_pending_irq, 667 }; 668 669 /** 670 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU 671 * @vgpu: a vGPU 672 * @event: interrupt event 673 * 674 * This function is used to trigger a virtual interrupt event for vGPU. 675 * The caller provides the event to be triggered, the framework itself 676 * will emulate the IRQ register bit change. 677 * 678 */ 679 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 680 enum intel_gvt_event_type event) 681 { 682 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 683 struct intel_gvt *gvt = vgpu->gvt; 684 struct intel_gvt_irq *irq = &gvt->irq; 685 gvt_event_virt_handler_t handler; 686 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 687 688 handler = get_event_virt_handler(irq, event); 689 drm_WARN_ON(&i915->drm, !handler); 690 691 handler(irq, event, vgpu); 692 693 ops->check_pending_irq(vgpu); 694 } 695 696 static void init_events( 697 struct intel_gvt_irq *irq) 698 { 699 int i; 700 701 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) { 702 irq->events[i].info = NULL; 703 irq->events[i].v_handler = handle_default_event_virt; 704 } 705 } 706 707 /** 708 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem 709 * @gvt: a GVT device 710 * 711 * This function is called at driver loading stage, to initialize the GVT-g IRQ 712 * emulation subsystem. 713 * 714 * Returns: 715 * Zero on success, negative error code if failed. 716 */ 717 int intel_gvt_init_irq(struct intel_gvt *gvt) 718 { 719 struct intel_gvt_irq *irq = &gvt->irq; 720 721 gvt_dbg_core("init irq framework\n"); 722 723 irq->ops = &gen8_irq_ops; 724 irq->irq_map = gen8_irq_map; 725 726 /* common event initialization */ 727 init_events(irq); 728 729 /* gen specific initialization */ 730 irq->ops->init_irq(irq); 731 732 init_irq_map(irq); 733 734 return 0; 735 } 736