1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min he <min.he@intel.com> 29 * 30 */ 31 32 #include <linux/eventfd.h> 33 34 #include <drm/drm_print.h> 35 #include <drm/intel/intel_gmd_interrupt_regs.h> 36 37 #include "display/intel_display_regs.h" 38 39 #include "gvt.h" 40 #include "i915_drv.h" 41 #include "i915_reg.h" 42 #include "trace.h" 43 44 struct intel_gvt_irq_info { 45 char *name; 46 i915_reg_t reg_base; 47 enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; 48 int group; 49 DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); 50 bool has_upstream_irq; 51 }; 52 53 struct intel_gvt_irq_map { 54 int up_irq_group; 55 int up_irq_bit; 56 int down_irq_group; 57 u32 down_irq_bitmask; 58 }; 59 60 /* common offset among interrupt control registers */ 61 #define regbase_to_isr(base) (base) 62 #define regbase_to_imr(base) (base + 0x4) 63 #define regbase_to_iir(base) (base + 0x8) 64 #define regbase_to_ier(base) (base + 0xC) 65 66 #define iir_to_regbase(iir) (iir - 0x8) 67 #define ier_to_regbase(ier) (ier - 0xC) 68 69 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler) 70 #define get_irq_info(irq, e) (irq->events[e].info) 71 72 #define irq_to_gvt(irq) \ 73 container_of(irq, struct intel_gvt, irq) 74 75 static void update_upstream_irq(struct intel_vgpu *vgpu, 76 struct intel_gvt_irq_info *info); 77 78 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = { 79 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT", 80 [RCS_DEBUG] = "Render EU debug from SVG", 81 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status", 82 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt", 83 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify", 84 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded", 85 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults", 86 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt", 87 88 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT", 89 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status", 90 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt", 91 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify", 92 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded", 93 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults", 94 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt", 95 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT", 96 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify", 97 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt", 98 99 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT", 100 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status", 101 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt", 102 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify", 103 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults", 104 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt", 105 106 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify", 107 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt", 108 109 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun", 110 [PIPE_A_CRC_ERR] = "Pipe A CRC error", 111 [PIPE_A_CRC_DONE] = "Pipe A CRC done", 112 [PIPE_A_VSYNC] = "Pipe A vsync", 113 [PIPE_A_LINE_COMPARE] = "Pipe A line compare", 114 [PIPE_A_ODD_FIELD] = "Pipe A odd field", 115 [PIPE_A_EVEN_FIELD] = "Pipe A even field", 116 [PIPE_A_VBLANK] = "Pipe A vblank", 117 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun", 118 [PIPE_B_CRC_ERR] = "Pipe B CRC error", 119 [PIPE_B_CRC_DONE] = "Pipe B CRC done", 120 [PIPE_B_VSYNC] = "Pipe B vsync", 121 [PIPE_B_LINE_COMPARE] = "Pipe B line compare", 122 [PIPE_B_ODD_FIELD] = "Pipe B odd field", 123 [PIPE_B_EVEN_FIELD] = "Pipe B even field", 124 [PIPE_B_VBLANK] = "Pipe B vblank", 125 [PIPE_C_VBLANK] = "Pipe C vblank", 126 [DPST_PHASE_IN] = "DPST phase in event", 127 [DPST_HISTOGRAM] = "DPST histogram event", 128 [GSE] = "GSE", 129 [DP_A_HOTPLUG] = "DP A Hotplug", 130 [AUX_CHANNEL_A] = "AUX Channel A", 131 [PERF_COUNTER] = "Performance counter", 132 [POISON] = "Poison", 133 [GTT_FAULT] = "GTT fault", 134 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done", 135 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done", 136 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done", 137 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done", 138 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done", 139 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done", 140 141 [PCU_THERMAL] = "PCU Thermal Event", 142 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event", 143 144 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A", 145 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A", 146 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A", 147 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B", 148 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B", 149 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B", 150 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C", 151 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C", 152 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C", 153 [ERR_AND_DBG] = "South Error and Debug Interrupts Combined", 154 [GMBUS] = "Gmbus", 155 [SDVO_B_HOTPLUG] = "SDVO B hotplug", 156 [CRT_HOTPLUG] = "CRT Hotplug", 157 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug", 158 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug", 159 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug", 160 [AUX_CHANNEL_B] = "AUX Channel B", 161 [AUX_CHANNEL_C] = "AUX Channel C", 162 [AUX_CHANNEL_D] = "AUX Channel D", 163 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B", 164 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C", 165 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D", 166 167 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!", 168 }; 169 170 static inline struct intel_gvt_irq_info *regbase_to_irq_info( 171 struct intel_gvt *gvt, 172 unsigned int reg) 173 { 174 struct intel_gvt_irq *irq = &gvt->irq; 175 int i; 176 177 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 178 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) 179 return irq->info[i]; 180 } 181 182 return NULL; 183 } 184 185 /** 186 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler 187 * @vgpu: a vGPU 188 * @reg: register offset written by guest 189 * @p_data: register data written by guest 190 * @bytes: register data length 191 * 192 * This function is used to emulate the generic IMR register bit change 193 * behavior. 194 * 195 * Returns: 196 * Zero on success, negative error code if failed. 197 * 198 */ 199 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 200 unsigned int reg, void *p_data, unsigned int bytes) 201 { 202 struct intel_gvt *gvt = vgpu->gvt; 203 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 204 u32 imr = *(u32 *)p_data; 205 206 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), 207 (vgpu_vreg(vgpu, reg) ^ imr)); 208 209 vgpu_vreg(vgpu, reg) = imr; 210 211 ops->check_pending_irq(vgpu); 212 213 return 0; 214 } 215 216 /** 217 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler 218 * @vgpu: a vGPU 219 * @reg: register offset written by guest 220 * @p_data: register data written by guest 221 * @bytes: register data length 222 * 223 * This function is used to emulate the master IRQ register on gen8+. 224 * 225 * Returns: 226 * Zero on success, negative error code if failed. 227 * 228 */ 229 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 230 unsigned int reg, void *p_data, unsigned int bytes) 231 { 232 struct intel_gvt *gvt = vgpu->gvt; 233 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 234 u32 ier = *(u32 *)p_data; 235 u32 virtual_ier = vgpu_vreg(vgpu, reg); 236 237 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier, 238 (virtual_ier ^ ier)); 239 240 /* 241 * GEN8_MASTER_IRQ is a special irq register, 242 * only bit 31 is allowed to be modified 243 * and treated as an IER bit. 244 */ 245 ier &= GEN8_MASTER_IRQ_CONTROL; 246 virtual_ier &= GEN8_MASTER_IRQ_CONTROL; 247 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; 248 vgpu_vreg(vgpu, reg) |= ier; 249 250 ops->check_pending_irq(vgpu); 251 252 return 0; 253 } 254 255 /** 256 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler 257 * @vgpu: a vGPU 258 * @reg: register offset written by guest 259 * @p_data: register data written by guest 260 * @bytes: register data length 261 * 262 * This function is used to emulate the generic IER register behavior. 263 * 264 * Returns: 265 * Zero on success, negative error code if failed. 266 * 267 */ 268 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 269 unsigned int reg, void *p_data, unsigned int bytes) 270 { 271 struct intel_gvt *gvt = vgpu->gvt; 272 struct drm_i915_private *i915 = gvt->gt->i915; 273 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 274 struct intel_gvt_irq_info *info; 275 u32 ier = *(u32 *)p_data; 276 277 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), 278 (vgpu_vreg(vgpu, reg) ^ ier)); 279 280 vgpu_vreg(vgpu, reg) = ier; 281 282 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); 283 if (drm_WARN_ON(&i915->drm, !info)) 284 return -EINVAL; 285 286 if (info->has_upstream_irq) 287 update_upstream_irq(vgpu, info); 288 289 ops->check_pending_irq(vgpu); 290 291 return 0; 292 } 293 294 /** 295 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler 296 * @vgpu: a vGPU 297 * @reg: register offset written by guest 298 * @p_data: register data written by guest 299 * @bytes: register data length 300 * 301 * This function is used to emulate the generic IIR register behavior. 302 * 303 * Returns: 304 * Zero on success, negative error code if failed. 305 * 306 */ 307 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 308 void *p_data, unsigned int bytes) 309 { 310 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 311 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, 312 iir_to_regbase(reg)); 313 u32 iir = *(u32 *)p_data; 314 315 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), 316 (vgpu_vreg(vgpu, reg) ^ iir)); 317 318 if (drm_WARN_ON(&i915->drm, !info)) 319 return -EINVAL; 320 321 vgpu_vreg(vgpu, reg) &= ~iir; 322 323 if (info->has_upstream_irq) 324 update_upstream_irq(vgpu, info); 325 return 0; 326 } 327 328 static struct intel_gvt_irq_map gen8_irq_map[] = { 329 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff }, 330 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 }, 331 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff }, 332 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 }, 333 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff }, 334 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff }, 335 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 }, 336 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 }, 337 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 }, 338 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 }, 339 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 }, 340 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 }, 341 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 }, 342 { -1, -1, ~0 }, 343 }; 344 345 static void update_upstream_irq(struct intel_vgpu *vgpu, 346 struct intel_gvt_irq_info *info) 347 { 348 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 349 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 350 struct intel_gvt_irq_map *map = irq->irq_map; 351 struct intel_gvt_irq_info *up_irq_info = NULL; 352 u32 set_bits = 0; 353 u32 clear_bits = 0; 354 int bit; 355 u32 val = vgpu_vreg(vgpu, 356 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) 357 & vgpu_vreg(vgpu, 358 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); 359 360 if (!info->has_upstream_irq) 361 return; 362 363 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 364 if (info->group != map->down_irq_group) 365 continue; 366 367 if (!up_irq_info) 368 up_irq_info = irq->info[map->up_irq_group]; 369 else 370 drm_WARN_ON(&i915->drm, up_irq_info != 371 irq->info[map->up_irq_group]); 372 373 bit = map->up_irq_bit; 374 375 if (val & map->down_irq_bitmask) 376 set_bits |= (1 << bit); 377 else 378 clear_bits |= (1 << bit); 379 } 380 381 if (drm_WARN_ON(&i915->drm, !up_irq_info)) 382 return; 383 384 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { 385 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); 386 387 vgpu_vreg(vgpu, isr) &= ~clear_bits; 388 vgpu_vreg(vgpu, isr) |= set_bits; 389 } else { 390 u32 iir = regbase_to_iir( 391 i915_mmio_reg_offset(up_irq_info->reg_base)); 392 u32 imr = regbase_to_imr( 393 i915_mmio_reg_offset(up_irq_info->reg_base)); 394 395 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); 396 } 397 398 if (up_irq_info->has_upstream_irq) 399 update_upstream_irq(vgpu, up_irq_info); 400 } 401 402 static void init_irq_map(struct intel_gvt_irq *irq) 403 { 404 struct intel_gvt_irq_map *map; 405 struct intel_gvt_irq_info *up_info, *down_info; 406 int up_bit; 407 408 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 409 up_info = irq->info[map->up_irq_group]; 410 up_bit = map->up_irq_bit; 411 down_info = irq->info[map->down_irq_group]; 412 413 set_bit(up_bit, up_info->downstream_irq_bitmap); 414 down_info->has_upstream_irq = true; 415 416 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", 417 up_info->group, up_bit, 418 down_info->group, map->down_irq_bitmask); 419 } 420 } 421 422 /* =======================vEvent injection===================== */ 423 424 #define MSI_CAP_CONTROL(offset) (offset + 2) 425 #define MSI_CAP_ADDRESS(offset) (offset + 4) 426 #define MSI_CAP_DATA(offset) (offset + 8) 427 #define MSI_CAP_EN 0x1 428 429 static void inject_virtual_interrupt(struct intel_vgpu *vgpu) 430 { 431 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset; 432 u16 control, data; 433 u32 addr; 434 435 control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset)); 436 addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset)); 437 data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset)); 438 439 /* Do not generate MSI if MSIEN is disabled */ 440 if (!(control & MSI_CAP_EN)) 441 return; 442 443 if (WARN(control & GENMASK(15, 1), "only support one MSI format\n")) 444 return; 445 446 trace_inject_msi(vgpu->id, addr, data); 447 448 /* 449 * When guest is powered off, msi_trigger is set to NULL, but vgpu's 450 * config and mmio register isn't restored to default during guest 451 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe 452 * may be enabled, then once this vgpu is active, it will get inject 453 * vblank interrupt request. But msi_trigger is null until msi is 454 * enabled by guest. so if msi_trigger is null, success is still 455 * returned and don't inject interrupt into guest. 456 */ 457 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) 458 return; 459 if (vgpu->msi_trigger) 460 eventfd_signal(vgpu->msi_trigger); 461 } 462 463 static void propagate_event(struct intel_gvt_irq *irq, 464 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 465 { 466 struct intel_gvt_irq_info *info; 467 unsigned int reg_base; 468 int bit; 469 470 info = get_irq_info(irq, event); 471 if (WARN_ON(!info)) 472 return; 473 474 reg_base = i915_mmio_reg_offset(info->reg_base); 475 bit = irq->events[event].bit; 476 477 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu, 478 regbase_to_imr(reg_base)))) { 479 trace_propagate_event(vgpu->id, irq_name[event], bit); 480 set_bit(bit, (void *)&vgpu_vreg(vgpu, 481 regbase_to_iir(reg_base))); 482 } 483 } 484 485 /* =======================vEvent Handlers===================== */ 486 static void handle_default_event_virt(struct intel_gvt_irq *irq, 487 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 488 { 489 if (!vgpu->irq.irq_warn_once[event]) { 490 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", 491 vgpu->id, event, irq_name[event]); 492 vgpu->irq.irq_warn_once[event] = true; 493 } 494 propagate_event(irq, event, vgpu); 495 } 496 497 /* =====================GEN specific logic======================= */ 498 /* GEN8 interrupt routines. */ 499 500 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \ 501 static struct intel_gvt_irq_info gen8_##regname##_info = { \ 502 .name = #regname"-IRQ", \ 503 .reg_base = (regbase), \ 504 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \ 505 INTEL_GVT_EVENT_RESERVED}, \ 506 } 507 508 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0)); 509 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1)); 510 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2)); 511 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3)); 512 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A)); 513 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B)); 514 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C)); 515 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR); 516 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR); 517 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR); 518 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ); 519 520 static struct intel_gvt_irq_info gvt_base_pch_info = { 521 .name = "PCH-IRQ", 522 .reg_base = SDEISR, 523 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = 524 INTEL_GVT_EVENT_RESERVED}, 525 }; 526 527 static void gen8_check_pending_irq(struct intel_vgpu *vgpu) 528 { 529 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 530 int i; 531 532 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & 533 GEN8_MASTER_IRQ_CONTROL)) 534 return; 535 536 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 537 struct intel_gvt_irq_info *info = irq->info[i]; 538 u32 reg_base; 539 540 if (!info->has_upstream_irq) 541 continue; 542 543 reg_base = i915_mmio_reg_offset(info->reg_base); 544 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base)) 545 & vgpu_vreg(vgpu, regbase_to_ier(reg_base)))) 546 update_upstream_irq(vgpu, info); 547 } 548 549 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) 550 & ~GEN8_MASTER_IRQ_CONTROL) 551 inject_virtual_interrupt(vgpu); 552 } 553 554 static void gen8_init_irq( 555 struct intel_gvt_irq *irq) 556 { 557 struct intel_gvt *gvt = irq_to_gvt(irq); 558 559 #define SET_BIT_INFO(s, b, e, i) \ 560 do { \ 561 s->events[e].bit = b; \ 562 s->events[e].info = s->info[i]; \ 563 s->info[i]->bit_to_event[b] = e;\ 564 } while (0) 565 566 #define SET_IRQ_GROUP(s, g, i) \ 567 do { \ 568 s->info[g] = i; \ 569 (i)->group = g; \ 570 set_bit(g, s->irq_info_bitmap); \ 571 } while (0) 572 573 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info); 574 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info); 575 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info); 576 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info); 577 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info); 578 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info); 579 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info); 580 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info); 581 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info); 582 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info); 583 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info); 584 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info); 585 586 /* GEN8 level 2 interrupts. */ 587 588 /* GEN8 interrupt GT0 events */ 589 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 590 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0); 591 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 592 593 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 594 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0); 595 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 596 597 /* GEN8 interrupt GT1 events */ 598 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1); 599 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); 600 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); 601 602 if (HAS_ENGINE(gvt->gt, VCS1)) { 603 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, 604 INTEL_GVT_IRQ_INFO_GT1); 605 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, 606 INTEL_GVT_IRQ_INFO_GT1); 607 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH, 608 INTEL_GVT_IRQ_INFO_GT1); 609 } 610 611 /* GEN8 interrupt GT3 events */ 612 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3); 613 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3); 614 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3); 615 616 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 617 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 618 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 619 620 /* GEN8 interrupt DE PORT events */ 621 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT); 622 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT); 623 624 /* GEN8 interrupt DE MISC events */ 625 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC); 626 627 /* PCH events */ 628 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH); 629 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 630 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 631 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 632 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 633 634 if (IS_BROADWELL(gvt->gt->i915)) { 635 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH); 636 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH); 637 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH); 638 639 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 640 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 641 642 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 643 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 644 645 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 646 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 647 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) { 648 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT); 649 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT); 650 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT); 651 652 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 653 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 654 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 655 656 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 657 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 658 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 659 } 660 661 /* GEN8 interrupt PCU events */ 662 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU); 663 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU); 664 } 665 666 static const struct intel_gvt_irq_ops gen8_irq_ops = { 667 .init_irq = gen8_init_irq, 668 .check_pending_irq = gen8_check_pending_irq, 669 }; 670 671 /** 672 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU 673 * @vgpu: a vGPU 674 * @event: interrupt event 675 * 676 * This function is used to trigger a virtual interrupt event for vGPU. 677 * The caller provides the event to be triggered, the framework itself 678 * will emulate the IRQ register bit change. 679 * 680 */ 681 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 682 enum intel_gvt_event_type event) 683 { 684 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 685 struct intel_gvt *gvt = vgpu->gvt; 686 struct intel_gvt_irq *irq = &gvt->irq; 687 gvt_event_virt_handler_t handler; 688 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 689 690 handler = get_event_virt_handler(irq, event); 691 drm_WARN_ON(&i915->drm, !handler); 692 693 handler(irq, event, vgpu); 694 695 ops->check_pending_irq(vgpu); 696 } 697 698 static void init_events( 699 struct intel_gvt_irq *irq) 700 { 701 int i; 702 703 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) { 704 irq->events[i].info = NULL; 705 irq->events[i].v_handler = handle_default_event_virt; 706 } 707 } 708 709 /** 710 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem 711 * @gvt: a GVT device 712 * 713 * This function is called at driver loading stage, to initialize the GVT-g IRQ 714 * emulation subsystem. 715 * 716 * Returns: 717 * Zero on success, negative error code if failed. 718 */ 719 int intel_gvt_init_irq(struct intel_gvt *gvt) 720 { 721 struct intel_gvt_irq *irq = &gvt->irq; 722 723 gvt_dbg_core("init irq framework\n"); 724 725 irq->ops = &gen8_irq_ops; 726 irq->irq_map = gen8_irq_map; 727 728 /* common event initialization */ 729 init_events(irq); 730 731 /* gen specific initialization */ 732 irq->ops->init_irq(irq); 733 734 init_irq_map(irq); 735 736 return 0; 737 } 738