1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min he <min.he@intel.com> 29 * 30 */ 31 32 #include "i915_drv.h" 33 #include "gvt.h" 34 35 /* common offset among interrupt control registers */ 36 #define regbase_to_isr(base) (base) 37 #define regbase_to_imr(base) (base + 0x4) 38 #define regbase_to_iir(base) (base + 0x8) 39 #define regbase_to_ier(base) (base + 0xC) 40 41 #define iir_to_regbase(iir) (iir - 0x8) 42 #define ier_to_regbase(ier) (ier - 0xC) 43 44 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler) 45 #define get_irq_info(irq, e) (irq->events[e].info) 46 47 #define irq_to_gvt(irq) \ 48 container_of(irq, struct intel_gvt, irq) 49 50 static void update_upstream_irq(struct intel_vgpu *vgpu, 51 struct intel_gvt_irq_info *info); 52 53 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = { 54 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT", 55 [RCS_DEBUG] = "Render EU debug from SVG", 56 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status", 57 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt", 58 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify", 59 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded", 60 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults", 61 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt", 62 63 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT", 64 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status", 65 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt", 66 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify", 67 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded", 68 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults", 69 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt", 70 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT", 71 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify", 72 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt", 73 74 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT", 75 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status", 76 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt", 77 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify", 78 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults", 79 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt", 80 81 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify", 82 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt", 83 84 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun", 85 [PIPE_A_CRC_ERR] = "Pipe A CRC error", 86 [PIPE_A_CRC_DONE] = "Pipe A CRC done", 87 [PIPE_A_VSYNC] = "Pipe A vsync", 88 [PIPE_A_LINE_COMPARE] = "Pipe A line compare", 89 [PIPE_A_ODD_FIELD] = "Pipe A odd field", 90 [PIPE_A_EVEN_FIELD] = "Pipe A even field", 91 [PIPE_A_VBLANK] = "Pipe A vblank", 92 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun", 93 [PIPE_B_CRC_ERR] = "Pipe B CRC error", 94 [PIPE_B_CRC_DONE] = "Pipe B CRC done", 95 [PIPE_B_VSYNC] = "Pipe B vsync", 96 [PIPE_B_LINE_COMPARE] = "Pipe B line compare", 97 [PIPE_B_ODD_FIELD] = "Pipe B odd field", 98 [PIPE_B_EVEN_FIELD] = "Pipe B even field", 99 [PIPE_B_VBLANK] = "Pipe B vblank", 100 [PIPE_C_VBLANK] = "Pipe C vblank", 101 [DPST_PHASE_IN] = "DPST phase in event", 102 [DPST_HISTOGRAM] = "DPST histogram event", 103 [GSE] = "GSE", 104 [DP_A_HOTPLUG] = "DP A Hotplug", 105 [AUX_CHANNEL_A] = "AUX Channel A", 106 [PERF_COUNTER] = "Performance counter", 107 [POISON] = "Poison", 108 [GTT_FAULT] = "GTT fault", 109 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done", 110 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done", 111 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done", 112 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done", 113 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done", 114 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done", 115 116 [PCU_THERMAL] = "PCU Thermal Event", 117 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event", 118 119 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A", 120 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A", 121 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A", 122 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B", 123 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B", 124 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B", 125 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C", 126 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C", 127 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C", 128 [ERR_AND_DBG] = "South Error and Debug Interupts Combined", 129 [GMBUS] = "Gmbus", 130 [SDVO_B_HOTPLUG] = "SDVO B hotplug", 131 [CRT_HOTPLUG] = "CRT Hotplug", 132 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug", 133 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug", 134 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug", 135 [AUX_CHANNEL_B] = "AUX Channel B", 136 [AUX_CHANNEL_C] = "AUX Channel C", 137 [AUX_CHANNEL_D] = "AUX Channel D", 138 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B", 139 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C", 140 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D", 141 142 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!", 143 }; 144 145 static inline struct intel_gvt_irq_info *regbase_to_irq_info( 146 struct intel_gvt *gvt, 147 unsigned int reg) 148 { 149 struct intel_gvt_irq *irq = &gvt->irq; 150 int i; 151 152 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 153 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) 154 return irq->info[i]; 155 } 156 157 return NULL; 158 } 159 160 /** 161 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler 162 * @vgpu: a vGPU 163 * @reg: register offset written by guest 164 * @p_data: register data written by guest 165 * @bytes: register data length 166 * 167 * This function is used to emulate the generic IMR register bit change 168 * behavior. 169 * 170 * Returns: 171 * Zero on success, negative error code if failed. 172 * 173 */ 174 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 175 unsigned int reg, void *p_data, unsigned int bytes) 176 { 177 struct intel_gvt *gvt = vgpu->gvt; 178 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 179 u32 changed, masked, unmasked; 180 u32 imr = *(u32 *)p_data; 181 182 gvt_dbg_irq("write IMR %x with val %x\n", 183 reg, imr); 184 185 gvt_dbg_irq("old vIMR %x\n", vgpu_vreg(vgpu, reg)); 186 187 /* figure out newly masked/unmasked bits */ 188 changed = vgpu_vreg(vgpu, reg) ^ imr; 189 masked = (vgpu_vreg(vgpu, reg) & changed) ^ changed; 190 unmasked = masked ^ changed; 191 192 gvt_dbg_irq("changed %x, masked %x, unmasked %x\n", 193 changed, masked, unmasked); 194 195 vgpu_vreg(vgpu, reg) = imr; 196 197 ops->check_pending_irq(vgpu); 198 gvt_dbg_irq("IRQ: new vIMR %x\n", vgpu_vreg(vgpu, reg)); 199 return 0; 200 } 201 202 /** 203 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler 204 * @vgpu: a vGPU 205 * @reg: register offset written by guest 206 * @p_data: register data written by guest 207 * @bytes: register data length 208 * 209 * This function is used to emulate the master IRQ register on gen8+. 210 * 211 * Returns: 212 * Zero on success, negative error code if failed. 213 * 214 */ 215 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 216 unsigned int reg, void *p_data, unsigned int bytes) 217 { 218 struct intel_gvt *gvt = vgpu->gvt; 219 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 220 u32 changed, enabled, disabled; 221 u32 ier = *(u32 *)p_data; 222 u32 virtual_ier = vgpu_vreg(vgpu, reg); 223 224 gvt_dbg_irq("write master irq reg %x with val %x\n", 225 reg, ier); 226 227 gvt_dbg_irq("old vreg %x\n", vgpu_vreg(vgpu, reg)); 228 229 /* 230 * GEN8_MASTER_IRQ is a special irq register, 231 * only bit 31 is allowed to be modified 232 * and treated as an IER bit. 233 */ 234 ier &= GEN8_MASTER_IRQ_CONTROL; 235 virtual_ier &= GEN8_MASTER_IRQ_CONTROL; 236 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; 237 vgpu_vreg(vgpu, reg) |= ier; 238 239 /* figure out newly enabled/disable bits */ 240 changed = virtual_ier ^ ier; 241 enabled = (virtual_ier & changed) ^ changed; 242 disabled = enabled ^ changed; 243 244 gvt_dbg_irq("changed %x, enabled %x, disabled %x\n", 245 changed, enabled, disabled); 246 247 ops->check_pending_irq(vgpu); 248 gvt_dbg_irq("new vreg %x\n", vgpu_vreg(vgpu, reg)); 249 return 0; 250 } 251 252 /** 253 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler 254 * @vgpu: a vGPU 255 * @reg: register offset written by guest 256 * @p_data: register data written by guest 257 * @bytes: register data length 258 * 259 * This function is used to emulate the generic IER register behavior. 260 * 261 * Returns: 262 * Zero on success, negative error code if failed. 263 * 264 */ 265 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 266 unsigned int reg, void *p_data, unsigned int bytes) 267 { 268 struct intel_gvt *gvt = vgpu->gvt; 269 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 270 struct intel_gvt_irq_info *info; 271 u32 changed, enabled, disabled; 272 u32 ier = *(u32 *)p_data; 273 274 gvt_dbg_irq("write IER %x with val %x\n", 275 reg, ier); 276 277 gvt_dbg_irq("old vIER %x\n", vgpu_vreg(vgpu, reg)); 278 279 /* figure out newly enabled/disable bits */ 280 changed = vgpu_vreg(vgpu, reg) ^ ier; 281 enabled = (vgpu_vreg(vgpu, reg) & changed) ^ changed; 282 disabled = enabled ^ changed; 283 284 gvt_dbg_irq("changed %x, enabled %x, disabled %x\n", 285 changed, enabled, disabled); 286 vgpu_vreg(vgpu, reg) = ier; 287 288 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); 289 if (WARN_ON(!info)) 290 return -EINVAL; 291 292 if (info->has_upstream_irq) 293 update_upstream_irq(vgpu, info); 294 295 ops->check_pending_irq(vgpu); 296 gvt_dbg_irq("new vIER %x\n", vgpu_vreg(vgpu, reg)); 297 return 0; 298 } 299 300 /** 301 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler 302 * @vgpu: a vGPU 303 * @reg: register offset written by guest 304 * @p_data: register data written by guest 305 * @bytes: register data length 306 * 307 * This function is used to emulate the generic IIR register behavior. 308 * 309 * Returns: 310 * Zero on success, negative error code if failed. 311 * 312 */ 313 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 314 void *p_data, unsigned int bytes) 315 { 316 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, 317 iir_to_regbase(reg)); 318 u32 iir = *(u32 *)p_data; 319 320 gvt_dbg_irq("write IIR %x with val %x\n", reg, iir); 321 322 if (WARN_ON(!info)) 323 return -EINVAL; 324 325 vgpu_vreg(vgpu, reg) &= ~iir; 326 327 if (info->has_upstream_irq) 328 update_upstream_irq(vgpu, info); 329 return 0; 330 } 331 332 static struct intel_gvt_irq_map gen8_irq_map[] = { 333 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff }, 334 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 }, 335 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff }, 336 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 }, 337 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff }, 338 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff }, 339 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 }, 340 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 }, 341 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 }, 342 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 }, 343 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 }, 344 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 }, 345 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 }, 346 { -1, -1, ~0 }, 347 }; 348 349 static void update_upstream_irq(struct intel_vgpu *vgpu, 350 struct intel_gvt_irq_info *info) 351 { 352 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 353 struct intel_gvt_irq_map *map = irq->irq_map; 354 struct intel_gvt_irq_info *up_irq_info = NULL; 355 u32 set_bits = 0; 356 u32 clear_bits = 0; 357 int bit; 358 u32 val = vgpu_vreg(vgpu, 359 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) 360 & vgpu_vreg(vgpu, 361 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); 362 363 if (!info->has_upstream_irq) 364 return; 365 366 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 367 if (info->group != map->down_irq_group) 368 continue; 369 370 if (!up_irq_info) 371 up_irq_info = irq->info[map->up_irq_group]; 372 else 373 WARN_ON(up_irq_info != irq->info[map->up_irq_group]); 374 375 bit = map->up_irq_bit; 376 377 if (val & map->down_irq_bitmask) 378 set_bits |= (1 << bit); 379 else 380 clear_bits |= (1 << bit); 381 } 382 383 WARN_ON(!up_irq_info); 384 385 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { 386 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); 387 388 vgpu_vreg(vgpu, isr) &= ~clear_bits; 389 vgpu_vreg(vgpu, isr) |= set_bits; 390 } else { 391 u32 iir = regbase_to_iir( 392 i915_mmio_reg_offset(up_irq_info->reg_base)); 393 u32 imr = regbase_to_imr( 394 i915_mmio_reg_offset(up_irq_info->reg_base)); 395 396 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); 397 } 398 399 if (up_irq_info->has_upstream_irq) 400 update_upstream_irq(vgpu, up_irq_info); 401 } 402 403 static void init_irq_map(struct intel_gvt_irq *irq) 404 { 405 struct intel_gvt_irq_map *map; 406 struct intel_gvt_irq_info *up_info, *down_info; 407 int up_bit; 408 409 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 410 up_info = irq->info[map->up_irq_group]; 411 up_bit = map->up_irq_bit; 412 down_info = irq->info[map->down_irq_group]; 413 414 set_bit(up_bit, up_info->downstream_irq_bitmap); 415 down_info->has_upstream_irq = true; 416 417 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", 418 up_info->group, up_bit, 419 down_info->group, map->down_irq_bitmask); 420 } 421 } 422 423 /* =======================vEvent injection===================== */ 424 static int inject_virtual_interrupt(struct intel_vgpu *vgpu) 425 { 426 return intel_gvt_hypervisor_inject_msi(vgpu); 427 } 428 429 static void propagate_event(struct intel_gvt_irq *irq, 430 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 431 { 432 struct intel_gvt_irq_info *info; 433 unsigned int reg_base; 434 int bit; 435 436 info = get_irq_info(irq, event); 437 if (WARN_ON(!info)) 438 return; 439 440 reg_base = i915_mmio_reg_offset(info->reg_base); 441 bit = irq->events[event].bit; 442 443 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu, 444 regbase_to_imr(reg_base)))) { 445 gvt_dbg_irq("set bit (%d) for (%s) for vgpu (%d)\n", 446 bit, irq_name[event], vgpu->id); 447 set_bit(bit, (void *)&vgpu_vreg(vgpu, 448 regbase_to_iir(reg_base))); 449 } 450 } 451 452 /* =======================vEvent Handlers===================== */ 453 static void handle_default_event_virt(struct intel_gvt_irq *irq, 454 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 455 { 456 if (!vgpu->irq.irq_warn_once[event]) { 457 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", 458 vgpu->id, event, irq_name[event]); 459 vgpu->irq.irq_warn_once[event] = true; 460 } 461 propagate_event(irq, event, vgpu); 462 } 463 464 /* =====================GEN specific logic======================= */ 465 /* GEN8 interrupt routines. */ 466 467 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \ 468 static struct intel_gvt_irq_info gen8_##regname##_info = { \ 469 .name = #regname"-IRQ", \ 470 .reg_base = (regbase), \ 471 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \ 472 INTEL_GVT_EVENT_RESERVED}, \ 473 } 474 475 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0)); 476 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1)); 477 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2)); 478 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3)); 479 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A)); 480 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B)); 481 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C)); 482 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR); 483 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR); 484 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR); 485 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ); 486 487 static struct intel_gvt_irq_info gvt_base_pch_info = { 488 .name = "PCH-IRQ", 489 .reg_base = SDEISR, 490 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = 491 INTEL_GVT_EVENT_RESERVED}, 492 }; 493 494 static void gen8_check_pending_irq(struct intel_vgpu *vgpu) 495 { 496 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 497 int i; 498 499 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & 500 GEN8_MASTER_IRQ_CONTROL)) 501 return; 502 503 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 504 struct intel_gvt_irq_info *info = irq->info[i]; 505 u32 reg_base; 506 507 if (!info->has_upstream_irq) 508 continue; 509 510 reg_base = i915_mmio_reg_offset(info->reg_base); 511 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base)) 512 & vgpu_vreg(vgpu, regbase_to_ier(reg_base)))) 513 update_upstream_irq(vgpu, info); 514 } 515 516 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) 517 & ~GEN8_MASTER_IRQ_CONTROL) 518 inject_virtual_interrupt(vgpu); 519 } 520 521 static void gen8_init_irq( 522 struct intel_gvt_irq *irq) 523 { 524 struct intel_gvt *gvt = irq_to_gvt(irq); 525 526 #define SET_BIT_INFO(s, b, e, i) \ 527 do { \ 528 s->events[e].bit = b; \ 529 s->events[e].info = s->info[i]; \ 530 s->info[i]->bit_to_event[b] = e;\ 531 } while (0) 532 533 #define SET_IRQ_GROUP(s, g, i) \ 534 do { \ 535 s->info[g] = i; \ 536 (i)->group = g; \ 537 set_bit(g, s->irq_info_bitmap); \ 538 } while (0) 539 540 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info); 541 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info); 542 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info); 543 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info); 544 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info); 545 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info); 546 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info); 547 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info); 548 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info); 549 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info); 550 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info); 551 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info); 552 553 /* GEN8 level 2 interrupts. */ 554 555 /* GEN8 interrupt GT0 events */ 556 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 557 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0); 558 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 559 560 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 561 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0); 562 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 563 564 /* GEN8 interrupt GT1 events */ 565 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1); 566 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); 567 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); 568 569 if (HAS_BSD2(gvt->dev_priv)) { 570 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, 571 INTEL_GVT_IRQ_INFO_GT1); 572 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, 573 INTEL_GVT_IRQ_INFO_GT1); 574 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH, 575 INTEL_GVT_IRQ_INFO_GT1); 576 } 577 578 /* GEN8 interrupt GT3 events */ 579 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3); 580 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3); 581 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3); 582 583 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 584 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 585 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 586 587 /* GEN8 interrupt DE PORT events */ 588 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT); 589 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT); 590 591 /* GEN8 interrupt DE MISC events */ 592 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC); 593 594 /* PCH events */ 595 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH); 596 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 597 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 598 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 599 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 600 601 if (IS_BROADWELL(gvt->dev_priv)) { 602 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH); 603 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH); 604 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH); 605 606 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 607 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 608 609 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 610 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 611 612 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 613 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 614 } else if (IS_SKYLAKE(gvt->dev_priv)) { 615 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT); 616 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT); 617 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT); 618 619 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 620 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 621 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 622 } 623 624 /* GEN8 interrupt PCU events */ 625 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU); 626 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU); 627 } 628 629 static struct intel_gvt_irq_ops gen8_irq_ops = { 630 .init_irq = gen8_init_irq, 631 .check_pending_irq = gen8_check_pending_irq, 632 }; 633 634 /** 635 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU 636 * @vgpu: a vGPU 637 * @event: interrupt event 638 * 639 * This function is used to trigger a virtual interrupt event for vGPU. 640 * The caller provides the event to be triggered, the framework itself 641 * will emulate the IRQ register bit change. 642 * 643 */ 644 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 645 enum intel_gvt_event_type event) 646 { 647 struct intel_gvt *gvt = vgpu->gvt; 648 struct intel_gvt_irq *irq = &gvt->irq; 649 gvt_event_virt_handler_t handler; 650 struct intel_gvt_irq_ops *ops = gvt->irq.ops; 651 652 handler = get_event_virt_handler(irq, event); 653 WARN_ON(!handler); 654 655 handler(irq, event, vgpu); 656 657 ops->check_pending_irq(vgpu); 658 } 659 660 static void init_events( 661 struct intel_gvt_irq *irq) 662 { 663 int i; 664 665 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) { 666 irq->events[i].info = NULL; 667 irq->events[i].v_handler = handle_default_event_virt; 668 } 669 } 670 671 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 672 { 673 struct intel_gvt_vblank_timer *vblank_timer; 674 struct intel_gvt_irq *irq; 675 struct intel_gvt *gvt; 676 677 vblank_timer = container_of(data, struct intel_gvt_vblank_timer, timer); 678 irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer); 679 gvt = container_of(irq, struct intel_gvt, irq); 680 681 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EMULATE_VBLANK); 682 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 683 return HRTIMER_RESTART; 684 } 685 686 /** 687 * intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem 688 * @gvt: a GVT device 689 * 690 * This function is called at driver unloading stage, to clean up GVT-g IRQ 691 * emulation subsystem. 692 * 693 */ 694 void intel_gvt_clean_irq(struct intel_gvt *gvt) 695 { 696 struct intel_gvt_irq *irq = &gvt->irq; 697 698 hrtimer_cancel(&irq->vblank_timer.timer); 699 } 700 701 #define VBLNAK_TIMER_PERIOD 16000000 702 703 /** 704 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem 705 * @gvt: a GVT device 706 * 707 * This function is called at driver loading stage, to initialize the GVT-g IRQ 708 * emulation subsystem. 709 * 710 * Returns: 711 * Zero on success, negative error code if failed. 712 */ 713 int intel_gvt_init_irq(struct intel_gvt *gvt) 714 { 715 struct intel_gvt_irq *irq = &gvt->irq; 716 struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer; 717 718 gvt_dbg_core("init irq framework\n"); 719 720 if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) { 721 irq->ops = &gen8_irq_ops; 722 irq->irq_map = gen8_irq_map; 723 } else { 724 WARN_ON(1); 725 return -ENODEV; 726 } 727 728 /* common event initialization */ 729 init_events(irq); 730 731 /* gen specific initialization */ 732 irq->ops->init_irq(irq); 733 734 init_irq_map(irq); 735 736 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 737 vblank_timer->timer.function = vblank_timer_fn; 738 vblank_timer->period = VBLNAK_TIMER_PERIOD; 739 740 return 0; 741 } 742