1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include <uapi/linux/pci_regs.h> 37 #include <linux/kvm_host.h> 38 #include <linux/vfio.h> 39 #include <linux/mdev.h> 40 41 #include "i915_drv.h" 42 #include "intel_gvt.h" 43 44 #include "debug.h" 45 #include "mmio.h" 46 #include "reg.h" 47 #include "interrupt.h" 48 #include "gtt.h" 49 #include "display.h" 50 #include "edid.h" 51 #include "execlist.h" 52 #include "scheduler.h" 53 #include "sched_policy.h" 54 #include "mmio_context.h" 55 #include "cmd_parser.h" 56 #include "fb_decoder.h" 57 #include "dmabuf.h" 58 #include "page_track.h" 59 60 #define GVT_MAX_VGPU 8 61 62 /* Describe per-platform limitations. */ 63 struct intel_gvt_device_info { 64 u32 max_support_vgpus; 65 u32 cfg_space_size; 66 u32 mmio_size; 67 u32 mmio_bar; 68 unsigned long msi_cap_offset; 69 u32 gtt_start_offset; 70 u32 gtt_entry_size; 71 u32 gtt_entry_size_shift; 72 int gmadr_bytes_in_cmd; 73 u32 max_surface_size; 74 }; 75 76 /* GM resources owned by a vGPU */ 77 struct intel_vgpu_gm { 78 u64 aperture_sz; 79 u64 hidden_sz; 80 struct drm_mm_node low_gm_node; 81 struct drm_mm_node high_gm_node; 82 }; 83 84 #define INTEL_GVT_MAX_NUM_FENCES 32 85 86 /* Fences owned by a vGPU */ 87 struct intel_vgpu_fence { 88 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 89 u32 base; 90 u32 size; 91 }; 92 93 struct intel_vgpu_mmio { 94 void *vreg; 95 }; 96 97 #define INTEL_GVT_MAX_BAR_NUM 4 98 99 struct intel_vgpu_pci_bar { 100 u64 size; 101 bool tracked; 102 }; 103 104 struct intel_vgpu_cfg_space { 105 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 106 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 107 u32 pmcsr_off; 108 }; 109 110 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 111 112 struct intel_vgpu_irq { 113 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 114 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES], 115 INTEL_GVT_EVENT_MAX); 116 }; 117 118 struct intel_vgpu_opregion { 119 bool mapped; 120 void *va; 121 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 122 }; 123 124 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 125 126 struct intel_vgpu_display { 127 struct intel_vgpu_i2c_edid i2c_edid; 128 struct intel_vgpu_port ports[I915_MAX_PORTS]; 129 struct intel_vgpu_sbi sbi; 130 enum port port_num; 131 }; 132 133 struct vgpu_sched_ctl { 134 int weight; 135 }; 136 137 enum { 138 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 139 INTEL_VGPU_GUC_SUBMISSION, 140 }; 141 142 struct intel_vgpu_submission_ops { 143 const char *name; 144 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 145 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 146 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 147 }; 148 149 struct intel_vgpu_submission { 150 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 151 struct list_head workload_q_head[I915_NUM_ENGINES]; 152 struct intel_context *shadow[I915_NUM_ENGINES]; 153 struct kmem_cache *workloads; 154 atomic_t running_workload_num; 155 union { 156 u64 i915_context_pml4; 157 u64 i915_context_pdps[GEN8_3LVL_PDPES]; 158 }; 159 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 160 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 161 void *ring_scan_buffer[I915_NUM_ENGINES]; 162 int ring_scan_buffer_size[I915_NUM_ENGINES]; 163 const struct intel_vgpu_submission_ops *ops; 164 int virtual_submission_interface; 165 bool active; 166 struct { 167 u32 lrca; 168 bool valid; 169 u64 ring_context_gpa; 170 } last_ctx[I915_NUM_ENGINES]; 171 }; 172 173 #define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries" 174 175 struct intel_vgpu { 176 struct vfio_device vfio_device; 177 struct intel_gvt *gvt; 178 struct mutex vgpu_lock; 179 int id; 180 bool active; 181 bool attached; 182 bool pv_notified; 183 bool failsafe; 184 unsigned int resetting_eng; 185 186 /* Both sched_data and sched_ctl can be seen a part of the global gvt 187 * scheduler structure. So below 2 vgpu data are protected 188 * by sched_lock, not vgpu_lock. 189 */ 190 void *sched_data; 191 struct vgpu_sched_ctl sched_ctl; 192 193 struct intel_vgpu_fence fence; 194 struct intel_vgpu_gm gm; 195 struct intel_vgpu_cfg_space cfg_space; 196 struct intel_vgpu_mmio mmio; 197 struct intel_vgpu_irq irq; 198 struct intel_vgpu_gtt gtt; 199 struct intel_vgpu_opregion opregion; 200 struct intel_vgpu_display display; 201 struct intel_vgpu_submission submission; 202 struct radix_tree_root page_track_tree; 203 u32 hws_pga[I915_NUM_ENGINES]; 204 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */ 205 bool d3_entered; 206 207 struct dentry *debugfs; 208 209 struct list_head dmabuf_obj_list_head; 210 struct mutex dmabuf_lock; 211 struct idr object_idr; 212 struct intel_vgpu_vblank_timer vblank_timer; 213 214 u32 scan_nonprivbb; 215 216 struct vfio_region *region; 217 int num_regions; 218 struct eventfd_ctx *intx_trigger; 219 struct eventfd_ctx *msi_trigger; 220 221 /* 222 * Two caches are used to avoid mapping duplicated pages (eg. 223 * scratch pages). This help to reduce dma setup overhead. 224 */ 225 struct rb_root gfn_cache; 226 struct rb_root dma_addr_cache; 227 unsigned long nr_cache_entries; 228 struct mutex cache_lock; 229 230 atomic_t released; 231 232 struct kvm_page_track_notifier_node track_node; 233 #define NR_BKT (1 << 18) 234 struct hlist_head ptable[NR_BKT]; 235 #undef NR_BKT 236 }; 237 238 /* validating GM healthy status*/ 239 #define vgpu_is_vm_unhealthy(ret_val) \ 240 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 241 242 struct intel_gvt_gm { 243 unsigned long vgpu_allocated_low_gm_size; 244 unsigned long vgpu_allocated_high_gm_size; 245 }; 246 247 struct intel_gvt_fence { 248 unsigned long vgpu_allocated_fence_num; 249 }; 250 251 /* Special MMIO blocks. */ 252 struct gvt_mmio_block { 253 unsigned int device; 254 i915_reg_t offset; 255 unsigned int size; 256 gvt_mmio_func read; 257 gvt_mmio_func write; 258 }; 259 260 #define INTEL_GVT_MMIO_HASH_BITS 11 261 262 struct intel_gvt_mmio { 263 u16 *mmio_attribute; 264 /* Register contains RO bits */ 265 #define F_RO (1 << 0) 266 /* Register contains graphics address */ 267 #define F_GMADR (1 << 1) 268 /* Mode mask registers with high 16 bits as the mask bits */ 269 #define F_MODE_MASK (1 << 2) 270 /* This reg can be accessed by GPU commands */ 271 #define F_CMD_ACCESS (1 << 3) 272 /* This reg has been accessed by a VM */ 273 #define F_ACCESSED (1 << 4) 274 /* This reg requires save & restore during host PM suspend/resume */ 275 #define F_PM_SAVE (1 << 5) 276 /* This reg could be accessed by unaligned address */ 277 #define F_UNALIGN (1 << 6) 278 /* This reg is in GVT's mmio save-restor list and in hardware 279 * logical context image 280 */ 281 #define F_SR_IN_CTX (1 << 7) 282 /* Value of command write of this reg needs to be patched */ 283 #define F_CMD_WRITE_PATCH (1 << 8) 284 285 struct gvt_mmio_block *mmio_block; 286 unsigned int num_mmio_block; 287 288 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 289 unsigned long num_tracked_mmio; 290 }; 291 292 struct intel_gvt_firmware { 293 void *cfg_space; 294 void *mmio; 295 bool firmware_loaded; 296 }; 297 298 struct intel_vgpu_config { 299 unsigned int low_mm; 300 unsigned int high_mm; 301 unsigned int fence; 302 303 /* 304 * A vGPU with a weight of 8 will get twice as much GPU as a vGPU with 305 * a weight of 4 on a contended host, different vGPU type has different 306 * weight set. Legal weights range from 1 to 16. 307 */ 308 unsigned int weight; 309 enum intel_vgpu_edid edid; 310 const char *name; 311 }; 312 313 struct intel_vgpu_type { 314 struct mdev_type type; 315 char name[16]; 316 const struct intel_vgpu_config *conf; 317 }; 318 319 struct intel_gvt { 320 /* GVT scope lock, protect GVT itself, and all resource currently 321 * not yet protected by special locks(vgpu and scheduler lock). 322 */ 323 struct mutex lock; 324 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 325 struct mutex sched_lock; 326 327 struct intel_gt *gt; 328 struct idr vgpu_idr; /* vGPU IDR pool */ 329 330 struct intel_gvt_device_info device_info; 331 struct intel_gvt_gm gm; 332 struct intel_gvt_fence fence; 333 struct intel_gvt_mmio mmio; 334 struct intel_gvt_firmware firmware; 335 struct intel_gvt_irq irq; 336 struct intel_gvt_gtt gtt; 337 struct intel_gvt_workload_scheduler scheduler; 338 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 339 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 340 struct mdev_parent parent; 341 struct mdev_type **mdev_types; 342 struct intel_vgpu_type *types; 343 unsigned int num_types; 344 struct intel_vgpu *idle_vgpu; 345 346 struct task_struct *service_thread; 347 wait_queue_head_t service_thread_wq; 348 349 /* service_request is always used in bit operation, we should always 350 * use it with atomic bit ops so that no need to use gvt big lock. 351 */ 352 unsigned long service_request; 353 354 struct { 355 struct engine_mmio *mmio; 356 int ctx_mmio_count[I915_NUM_ENGINES]; 357 u32 *tlb_mmio_offset_list; 358 u32 tlb_mmio_offset_list_cnt; 359 u32 *mocs_mmio_offset_list; 360 u32 mocs_mmio_offset_list_cnt; 361 } engine_mmio_list; 362 bool is_reg_whitelist_updated; 363 364 struct dentry *debugfs_root; 365 }; 366 367 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 368 { 369 return i915->gvt; 370 } 371 372 enum { 373 /* Scheduling trigger by timer */ 374 INTEL_GVT_REQUEST_SCHED = 0, 375 376 /* Scheduling trigger by event */ 377 INTEL_GVT_REQUEST_EVENT_SCHED = 1, 378 379 /* per-vGPU vblank emulation request */ 380 INTEL_GVT_REQUEST_EMULATE_VBLANK = 2, 381 INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK 382 + GVT_MAX_VGPU, 383 }; 384 385 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 386 int service) 387 { 388 set_bit(service, (void *)&gvt->service_request); 389 wake_up(&gvt->service_thread_wq); 390 } 391 392 void intel_gvt_free_firmware(struct intel_gvt *gvt); 393 int intel_gvt_load_firmware(struct intel_gvt *gvt); 394 395 /* Aperture/GM space definitions for GVT device */ 396 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 397 #define BYTES_TO_MB(b) ((b) >> 20ULL) 398 399 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 400 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 401 #define HOST_FENCE 4 402 403 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) 404 405 /* Aperture/GM space definitions for GVT device */ 406 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end 407 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start 408 409 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total 410 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3) 411 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 412 413 #define gvt_aperture_gmadr_base(gvt) (0) 414 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 415 + gvt_aperture_sz(gvt) - 1) 416 417 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 418 + gvt_aperture_sz(gvt)) 419 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 420 + gvt_hidden_sz(gvt) - 1) 421 422 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences) 423 424 /* Aperture/GM space definitions for vGPU */ 425 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 426 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 427 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 428 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 429 430 #define vgpu_aperture_pa_base(vgpu) \ 431 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 432 433 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 434 435 #define vgpu_aperture_pa_end(vgpu) \ 436 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 437 438 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 439 #define vgpu_aperture_gmadr_end(vgpu) \ 440 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 441 442 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 443 #define vgpu_hidden_gmadr_end(vgpu) \ 444 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 445 446 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 447 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 448 449 /* ring context size i.e. the first 0x50 dwords*/ 450 #define RING_CTX_SIZE 320 451 452 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 453 const struct intel_vgpu_config *conf); 454 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 455 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 456 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 457 u32 fence, u64 value); 458 459 /* Macros for easily accessing vGPU virtual/shadow register. 460 Explicitly seperate use for typed MMIO reg or real offset.*/ 461 #define vgpu_vreg_t(vgpu, reg) \ 462 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 463 #define vgpu_vreg(vgpu, offset) \ 464 (*(u32 *)(vgpu->mmio.vreg + (offset))) 465 #define vgpu_vreg64_t(vgpu, reg) \ 466 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 467 #define vgpu_vreg64(vgpu, offset) \ 468 (*(u64 *)(vgpu->mmio.vreg + (offset))) 469 470 #define for_each_active_vgpu(gvt, vgpu, id) \ 471 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 472 for_each_if(vgpu->active) 473 474 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 475 u32 offset, u32 val, bool low) 476 { 477 u32 *pval; 478 479 /* BAR offset should be 32 bits algiend */ 480 offset = rounddown(offset, 4); 481 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 482 483 if (low) { 484 /* 485 * only update bit 31 - bit 4, 486 * leave the bit 3 - bit 0 unchanged. 487 */ 488 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 489 } else { 490 *pval = val; 491 } 492 } 493 494 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 495 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 496 497 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 498 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 499 int intel_gvt_create_vgpu(struct intel_vgpu *vgpu, 500 const struct intel_vgpu_config *conf); 501 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 502 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); 503 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 504 intel_engine_mask_t engine_mask); 505 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 506 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 507 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 508 509 int intel_gvt_set_opregion(struct intel_vgpu *vgpu); 510 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num); 511 512 /* validating GM functions */ 513 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 514 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 515 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 516 517 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 518 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 519 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 520 521 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 522 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 523 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 524 525 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 526 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 527 (gmadr <= gvt_aperture_gmadr_end(gvt))) 528 529 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 530 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 531 (gmadr <= gvt_hidden_gmadr_end(gvt))) 532 533 #define gvt_gmadr_is_valid(gvt, gmadr) \ 534 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 535 gvt_gmadr_is_hidden(gvt, gmadr)) 536 537 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 538 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 539 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 540 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 541 unsigned long *h_index); 542 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 543 unsigned long *g_index); 544 545 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 546 bool primary); 547 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 548 549 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 550 void *p_data, unsigned int bytes); 551 552 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 553 void *p_data, unsigned int bytes); 554 555 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected); 556 557 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 558 { 559 /* We are 64bit bar. */ 560 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 561 PCI_BASE_ADDRESS_MEM_MASK; 562 } 563 564 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 565 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 566 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 567 568 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 569 void populate_pvinfo_page(struct intel_vgpu *vgpu); 570 571 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 572 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 573 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu); 574 575 enum { 576 GVT_FAILSAFE_UNSUPPORTED_GUEST, 577 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 578 GVT_FAILSAFE_GUEST_ERR, 579 }; 580 581 static inline void mmio_hw_access_pre(struct intel_gt *gt) 582 { 583 intel_runtime_pm_get(gt->uncore->rpm); 584 } 585 586 static inline void mmio_hw_access_post(struct intel_gt *gt) 587 { 588 intel_runtime_pm_put_unchecked(gt->uncore->rpm); 589 } 590 591 /** 592 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 593 * @gvt: a GVT device 594 * @offset: register offset 595 * 596 */ 597 static inline void intel_gvt_mmio_set_accessed( 598 struct intel_gvt *gvt, unsigned int offset) 599 { 600 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 601 } 602 603 /** 604 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command 605 * @gvt: a GVT device 606 * @offset: register offset 607 * 608 * Returns: 609 * True if an MMIO is able to be accessed by GPU commands 610 */ 611 static inline bool intel_gvt_mmio_is_cmd_accessible( 612 struct intel_gvt *gvt, unsigned int offset) 613 { 614 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 615 } 616 617 /** 618 * intel_gvt_mmio_set_cmd_accessible - 619 * mark a MMIO could be accessible by command 620 * @gvt: a GVT device 621 * @offset: register offset 622 * 623 */ 624 static inline void intel_gvt_mmio_set_cmd_accessible( 625 struct intel_gvt *gvt, unsigned int offset) 626 { 627 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS; 628 } 629 630 /** 631 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 632 * @gvt: a GVT device 633 * @offset: register offset 634 * 635 */ 636 static inline bool intel_gvt_mmio_is_unalign( 637 struct intel_gvt *gvt, unsigned int offset) 638 { 639 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 640 } 641 642 /** 643 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 644 * @gvt: a GVT device 645 * @offset: register offset 646 * 647 * Returns: 648 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 649 * 650 */ 651 static inline bool intel_gvt_mmio_has_mode_mask( 652 struct intel_gvt *gvt, unsigned int offset) 653 { 654 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 655 } 656 657 /** 658 * intel_gvt_mmio_is_sr_in_ctx - 659 * check if an MMIO has F_SR_IN_CTX mask 660 * @gvt: a GVT device 661 * @offset: register offset 662 * 663 * Returns: 664 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't. 665 * 666 */ 667 static inline bool intel_gvt_mmio_is_sr_in_ctx( 668 struct intel_gvt *gvt, unsigned int offset) 669 { 670 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX; 671 } 672 673 /** 674 * intel_gvt_mmio_set_sr_in_ctx - 675 * mask an MMIO in GVT's mmio save-restore list and also 676 * in hardware logical context image 677 * @gvt: a GVT device 678 * @offset: register offset 679 * 680 */ 681 static inline void intel_gvt_mmio_set_sr_in_ctx( 682 struct intel_gvt *gvt, unsigned int offset) 683 { 684 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX; 685 } 686 687 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 688 /** 689 * intel_gvt_mmio_set_cmd_write_patch - 690 * mark an MMIO if its cmd write needs to be 691 * patched 692 * @gvt: a GVT device 693 * @offset: register offset 694 * 695 */ 696 static inline void intel_gvt_mmio_set_cmd_write_patch( 697 struct intel_gvt *gvt, unsigned int offset) 698 { 699 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH; 700 } 701 702 /** 703 * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to 704 * be patched 705 * @gvt: a GVT device 706 * @offset: register offset 707 * 708 * Returns: 709 * True if GPU commmand write to an MMIO should be patched 710 */ 711 static inline bool intel_gvt_mmio_is_cmd_write_patch( 712 struct intel_gvt *gvt, unsigned int offset) 713 { 714 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH; 715 } 716 717 /** 718 * intel_gvt_read_gpa - copy data from GPA to host data buffer 719 * @vgpu: a vGPU 720 * @gpa: guest physical address 721 * @buf: host data buffer 722 * @len: data length 723 * 724 * Returns: 725 * Zero on success, negative error code if failed. 726 */ 727 static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa, 728 void *buf, unsigned long len) 729 { 730 if (!vgpu->attached) 731 return -ESRCH; 732 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false); 733 } 734 735 /** 736 * intel_gvt_write_gpa - copy data from host data buffer to GPA 737 * @vgpu: a vGPU 738 * @gpa: guest physical address 739 * @buf: host data buffer 740 * @len: data length 741 * 742 * Returns: 743 * Zero on success, negative error code if failed. 744 */ 745 static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu, 746 unsigned long gpa, void *buf, unsigned long len) 747 { 748 if (!vgpu->attached) 749 return -ESRCH; 750 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true); 751 } 752 753 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 754 void intel_gvt_debugfs_init(struct intel_gvt *gvt); 755 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 756 757 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn); 758 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn); 759 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr); 760 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 761 unsigned long size, dma_addr_t *dma_addr); 762 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, 763 dma_addr_t dma_addr); 764 765 #include "trace.h" 766 767 #endif 768