1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * 26 * Contributors: 27 * Bing Niu <bing.niu@intel.com> 28 * Xu Han <xu.han@intel.com> 29 * Ping Gao <ping.a.gao@intel.com> 30 * Xiaoguang Chen <xiaoguang.chen@intel.com> 31 * Yang Liu <yang2.liu@intel.com> 32 * Tina Zhang <tina.zhang@intel.com> 33 * 34 */ 35 36 #include <uapi/drm/drm_fourcc.h> 37 38 #include "gvt.h" 39 #include "i915_drv.h" 40 #include "i915_pvinfo.h" 41 #include "i915_reg.h" 42 43 #include "display/intel_sprite_regs.h" 44 45 #define PRIMARY_FORMAT_NUM 16 46 struct pixel_format { 47 int drm_format; /* Pixel format in DRM definition */ 48 int bpp; /* Bits per pixel, 0 indicates invalid */ 49 const char *desc; /* The description */ 50 }; 51 52 static const struct pixel_format bdw_pixel_formats[] = { 53 {DRM_FORMAT_C8, 8, "8-bit Indexed"}, 54 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, 55 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, 56 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, 57 58 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, 59 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, 60 61 /* non-supported format has bpp default to 0 */ 62 {} 63 }; 64 65 static const struct pixel_format skl_pixel_formats[] = { 66 {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"}, 67 {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"}, 68 {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"}, 69 {DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"}, 70 71 {DRM_FORMAT_C8, 8, "8-bit Indexed"}, 72 {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"}, 73 {DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"}, 74 {DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, 75 76 {DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"}, 77 {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"}, 78 {DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"}, 79 {DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"}, 80 81 /* non-supported format has bpp default to 0 */ 82 {} 83 }; 84 85 static int bdw_format_to_drm(int format) 86 { 87 int bdw_pixel_formats_index = 6; 88 89 switch (format) { 90 case DISP_FORMAT_8BPP: 91 bdw_pixel_formats_index = 0; 92 break; 93 case DISP_FORMAT_BGRX565: 94 bdw_pixel_formats_index = 1; 95 break; 96 case DISP_FORMAT_BGRX888: 97 bdw_pixel_formats_index = 2; 98 break; 99 case DISP_FORMAT_RGBX101010: 100 bdw_pixel_formats_index = 3; 101 break; 102 case DISP_FORMAT_BGRX101010: 103 bdw_pixel_formats_index = 4; 104 break; 105 case DISP_FORMAT_RGBX888: 106 bdw_pixel_formats_index = 5; 107 break; 108 109 default: 110 break; 111 } 112 113 return bdw_pixel_formats_index; 114 } 115 116 static int skl_format_to_drm(int format, bool rgb_order, bool alpha, 117 int yuv_order) 118 { 119 int skl_pixel_formats_index = 12; 120 121 switch (format) { 122 case PLANE_CTL_FORMAT_INDEXED: 123 skl_pixel_formats_index = 4; 124 break; 125 case PLANE_CTL_FORMAT_RGB_565: 126 skl_pixel_formats_index = 5; 127 break; 128 case PLANE_CTL_FORMAT_XRGB_8888: 129 if (rgb_order) 130 skl_pixel_formats_index = alpha ? 6 : 7; 131 else 132 skl_pixel_formats_index = alpha ? 8 : 9; 133 break; 134 case PLANE_CTL_FORMAT_XRGB_2101010: 135 skl_pixel_formats_index = rgb_order ? 10 : 11; 136 break; 137 case PLANE_CTL_FORMAT_YUV422: 138 skl_pixel_formats_index = yuv_order >> 16; 139 if (skl_pixel_formats_index > 3) 140 return -EINVAL; 141 break; 142 143 default: 144 break; 145 } 146 147 return skl_pixel_formats_index; 148 } 149 150 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, 151 u32 tiled, int stride_mask, int bpp) 152 { 153 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 154 155 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; 156 u32 stride = stride_reg; 157 158 if (GRAPHICS_VER(dev_priv) >= 9) { 159 switch (tiled) { 160 case PLANE_CTL_TILED_LINEAR: 161 stride = stride_reg * 64; 162 break; 163 case PLANE_CTL_TILED_X: 164 stride = stride_reg * 512; 165 break; 166 case PLANE_CTL_TILED_Y: 167 stride = stride_reg * 128; 168 break; 169 case PLANE_CTL_TILED_YF: 170 if (bpp == 8) 171 stride = stride_reg * 64; 172 else if (bpp == 16 || bpp == 32 || bpp == 64) 173 stride = stride_reg * 128; 174 else 175 gvt_dbg_core("skl: unsupported bpp:%d\n", bpp); 176 break; 177 default: 178 gvt_dbg_core("skl: unsupported tile format:%x\n", 179 tiled); 180 } 181 } 182 183 return stride; 184 } 185 186 static int get_active_pipe(struct intel_vgpu *vgpu) 187 { 188 int i; 189 190 for (i = 0; i < I915_MAX_PIPES; i++) 191 if (pipe_is_enabled(vgpu, i)) 192 break; 193 194 return i; 195 } 196 197 /** 198 * intel_vgpu_decode_primary_plane - Decode primary plane 199 * @vgpu: input vgpu 200 * @plane: primary plane to save decoded info 201 * This function is called for decoding plane 202 * 203 * Returns: 204 * 0 on success, non-zero if failed. 205 */ 206 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 207 struct intel_vgpu_primary_plane_format *plane) 208 { 209 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 210 u32 val, fmt; 211 int pipe; 212 213 pipe = get_active_pipe(vgpu); 214 if (pipe >= I915_MAX_PIPES) 215 return -ENODEV; 216 217 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); 218 plane->enabled = !!(val & DISP_ENABLE); 219 if (!plane->enabled) 220 return -ENODEV; 221 222 if (GRAPHICS_VER(dev_priv) >= 9) { 223 plane->tiled = val & PLANE_CTL_TILED_MASK; 224 fmt = skl_format_to_drm( 225 val & PLANE_CTL_FORMAT_MASK_SKL, 226 val & PLANE_CTL_ORDER_RGBX, 227 val & PLANE_CTL_ALPHA_MASK, 228 val & PLANE_CTL_YUV422_ORDER_MASK); 229 230 if (fmt >= ARRAY_SIZE(skl_pixel_formats)) { 231 gvt_vgpu_err("Out-of-bounds pixel format index\n"); 232 return -EINVAL; 233 } 234 235 plane->bpp = skl_pixel_formats[fmt].bpp; 236 plane->drm_format = skl_pixel_formats[fmt].drm_format; 237 } else { 238 plane->tiled = val & DISP_TILED; 239 fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK); 240 plane->bpp = bdw_pixel_formats[fmt].bpp; 241 plane->drm_format = bdw_pixel_formats[fmt].drm_format; 242 } 243 244 if (!plane->bpp) { 245 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); 246 return -EINVAL; 247 } 248 249 plane->hw_format = fmt; 250 251 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; 252 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 253 return -EINVAL; 254 255 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 256 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 257 gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n", 258 plane->base); 259 return -EINVAL; 260 } 261 262 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, 263 (GRAPHICS_VER(dev_priv) >= 9) ? 264 (_PRI_PLANE_STRIDE_MASK >> 6) : 265 _PRI_PLANE_STRIDE_MASK, plane->bpp); 266 267 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> 268 _PIPE_H_SRCSZ_SHIFT; 269 plane->width += 1; 270 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & 271 _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; 272 plane->height += 1; /* raw height is one minus the real value */ 273 274 val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); 275 plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> 276 _PRI_PLANE_X_OFF_SHIFT; 277 plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> 278 _PRI_PLANE_Y_OFF_SHIFT; 279 280 return 0; 281 } 282 283 #define CURSOR_FORMAT_NUM (1 << 6) 284 struct cursor_mode_format { 285 int drm_format; /* Pixel format in DRM definition */ 286 u8 bpp; /* Bits per pixel; 0 indicates invalid */ 287 u32 width; /* In pixel */ 288 u32 height; /* In lines */ 289 const char *desc; /* The description */ 290 }; 291 292 static const struct cursor_mode_format cursor_pixel_formats[] = { 293 {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"}, 294 {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"}, 295 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, 296 {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, 297 298 /* non-supported format has bpp default to 0 */ 299 {} 300 }; 301 302 static int cursor_mode_to_drm(int mode) 303 { 304 int cursor_pixel_formats_index = 4; 305 306 switch (mode) { 307 case MCURSOR_MODE_128_ARGB_AX: 308 cursor_pixel_formats_index = 0; 309 break; 310 case MCURSOR_MODE_256_ARGB_AX: 311 cursor_pixel_formats_index = 1; 312 break; 313 case MCURSOR_MODE_64_ARGB_AX: 314 cursor_pixel_formats_index = 2; 315 break; 316 case MCURSOR_MODE_64_32B_AX: 317 cursor_pixel_formats_index = 3; 318 break; 319 320 default: 321 break; 322 } 323 324 return cursor_pixel_formats_index; 325 } 326 327 /** 328 * intel_vgpu_decode_cursor_plane - Decode sprite plane 329 * @vgpu: input vgpu 330 * @plane: cursor plane to save decoded info 331 * This function is called for decoding plane 332 * 333 * Returns: 334 * 0 on success, non-zero if failed. 335 */ 336 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 337 struct intel_vgpu_cursor_plane_format *plane) 338 { 339 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 340 u32 val, mode, index; 341 u32 alpha_plane, alpha_force; 342 int pipe; 343 344 pipe = get_active_pipe(vgpu); 345 if (pipe >= I915_MAX_PIPES) 346 return -ENODEV; 347 348 val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); 349 mode = val & MCURSOR_MODE_MASK; 350 plane->enabled = (mode != MCURSOR_MODE_DISABLE); 351 if (!plane->enabled) 352 return -ENODEV; 353 354 index = cursor_mode_to_drm(mode); 355 356 if (!cursor_pixel_formats[index].bpp) { 357 gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode); 358 return -EINVAL; 359 } 360 plane->mode = mode; 361 plane->bpp = cursor_pixel_formats[index].bpp; 362 plane->drm_format = cursor_pixel_formats[index].drm_format; 363 plane->width = cursor_pixel_formats[index].width; 364 plane->height = cursor_pixel_formats[index].height; 365 366 alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >> 367 _CURSOR_ALPHA_PLANE_SHIFT; 368 alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >> 369 _CURSOR_ALPHA_FORCE_SHIFT; 370 if (alpha_plane || alpha_force) 371 gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", 372 alpha_plane, alpha_force); 373 374 plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; 375 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 376 return -EINVAL; 377 378 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 379 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 380 gvt_vgpu_err("Translate cursor plane gma 0x%x to gpa fail\n", 381 plane->base); 382 return -EINVAL; 383 } 384 385 val = vgpu_vreg_t(vgpu, CURPOS(pipe)); 386 plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; 387 plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; 388 plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; 389 plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT; 390 391 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); 392 plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)); 393 return 0; 394 } 395 396 #define SPRITE_FORMAT_NUM (1 << 3) 397 398 static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = { 399 [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"}, 400 [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"}, 401 [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"}, 402 [0x4] = {DRM_FORMAT_AYUV, 32, 403 "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"}, 404 }; 405 406 /** 407 * intel_vgpu_decode_sprite_plane - Decode sprite plane 408 * @vgpu: input vgpu 409 * @plane: sprite plane to save decoded info 410 * This function is called for decoding plane 411 * 412 * Returns: 413 * 0 on success, non-zero if failed. 414 */ 415 int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 416 struct intel_vgpu_sprite_plane_format *plane) 417 { 418 u32 val, fmt; 419 u32 color_order, yuv_order; 420 int drm_format; 421 int pipe; 422 423 pipe = get_active_pipe(vgpu); 424 if (pipe >= I915_MAX_PIPES) 425 return -ENODEV; 426 427 val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); 428 plane->enabled = !!(val & SPRITE_ENABLE); 429 if (!plane->enabled) 430 return -ENODEV; 431 432 plane->tiled = !!(val & SPRITE_TILED); 433 color_order = !!(val & SPRITE_RGB_ORDER_RGBX); 434 yuv_order = (val & SPRITE_YUV_ORDER_MASK) >> 435 _SPRITE_YUV_ORDER_SHIFT; 436 437 fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT; 438 if (!sprite_pixel_formats[fmt].bpp) { 439 gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); 440 return -EINVAL; 441 } 442 plane->hw_format = fmt; 443 plane->bpp = sprite_pixel_formats[fmt].bpp; 444 drm_format = sprite_pixel_formats[fmt].drm_format; 445 446 /* Order of RGB values in an RGBxxx buffer may be ordered RGB or 447 * BGR depending on the state of the color_order field 448 */ 449 if (!color_order) { 450 if (drm_format == DRM_FORMAT_XRGB2101010) 451 drm_format = DRM_FORMAT_XBGR2101010; 452 else if (drm_format == DRM_FORMAT_XRGB8888) 453 drm_format = DRM_FORMAT_XBGR8888; 454 } 455 456 if (drm_format == DRM_FORMAT_YUV422) { 457 switch (yuv_order) { 458 case 0: 459 drm_format = DRM_FORMAT_YUYV; 460 break; 461 case 1: 462 drm_format = DRM_FORMAT_UYVY; 463 break; 464 case 2: 465 drm_format = DRM_FORMAT_YVYU; 466 break; 467 case 3: 468 drm_format = DRM_FORMAT_VYUY; 469 break; 470 default: 471 /* yuv_order has only 2 bits */ 472 break; 473 } 474 } 475 476 plane->drm_format = drm_format; 477 478 plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; 479 if (!vgpu_gmadr_is_valid(vgpu, plane->base)) 480 return -EINVAL; 481 482 plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); 483 if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { 484 gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", 485 plane->base); 486 return -EINVAL; 487 } 488 489 plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) & 490 _SPRITE_STRIDE_MASK; 491 492 val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); 493 plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> 494 _SPRITE_SIZE_HEIGHT_SHIFT; 495 plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> 496 _SPRITE_SIZE_WIDTH_SHIFT; 497 plane->height += 1; /* raw height is one minus the real value */ 498 plane->width += 1; /* raw width is one minus the real value */ 499 500 val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); 501 plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; 502 plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; 503 504 val = vgpu_vreg_t(vgpu, SPROFFSET(pipe)); 505 plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> 506 _SPRITE_OFFSET_START_X_SHIFT; 507 plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> 508 _SPRITE_OFFSET_START_Y_SHIFT; 509 510 return 0; 511 } 512