1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "gvt.h" 38 39 #include "display/bxt_dpio_phy_regs.h" 40 #include "display/intel_display.h" 41 #include "display/intel_dpio_phy.h" 42 43 static int get_edp_pipe(struct intel_vgpu *vgpu) 44 { 45 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 46 int pipe = -1; 47 48 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 49 case TRANS_DDI_EDP_INPUT_A_ON: 50 case TRANS_DDI_EDP_INPUT_A_ONOFF: 51 pipe = PIPE_A; 52 break; 53 case TRANS_DDI_EDP_INPUT_B_ONOFF: 54 pipe = PIPE_B; 55 break; 56 case TRANS_DDI_EDP_INPUT_C_ONOFF: 57 pipe = PIPE_C; 58 break; 59 } 60 return pipe; 61 } 62 63 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 64 { 65 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 66 67 if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 68 return 0; 69 70 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 71 return 0; 72 return 1; 73 } 74 75 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 76 { 77 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 78 79 if (drm_WARN_ON(&dev_priv->drm, 80 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 81 return -EINVAL; 82 83 if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE) 84 return 1; 85 86 if (edp_pipe_is_enabled(vgpu) && 87 get_edp_pipe(vgpu) == pipe) 88 return 1; 89 return 0; 90 } 91 92 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 93 { 94 /* EDID with 1024x768 as its resolution */ 95 /*Header*/ 96 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 97 /* Vendor & Product Identification */ 98 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 99 /* Version & Revision */ 100 0x01, 0x04, 101 /* Basic Display Parameters & Features */ 102 0xa5, 0x34, 0x20, 0x78, 0x23, 103 /* Color Characteristics */ 104 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 105 /* Established Timings: maximum resolution is 1024x768 */ 106 0x21, 0x08, 0x00, 107 /* Standard Timings. All invalid */ 108 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 109 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 110 /* 18 Byte Data Blocks 1: invalid */ 111 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 112 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 113 /* 18 Byte Data Blocks 2: invalid */ 114 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 115 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 116 /* 18 Byte Data Blocks 3: invalid */ 117 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 118 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 119 /* 18 Byte Data Blocks 4: invalid */ 120 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 121 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 122 /* Extension Block Count */ 123 0x00, 124 /* Checksum */ 125 0xef, 126 }, 127 { 128 /* EDID with 1920x1200 as its resolution */ 129 /*Header*/ 130 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 131 /* Vendor & Product Identification */ 132 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 133 /* Version & Revision */ 134 0x01, 0x04, 135 /* Basic Display Parameters & Features */ 136 0xa5, 0x34, 0x20, 0x78, 0x23, 137 /* Color Characteristics */ 138 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 139 /* Established Timings: maximum resolution is 1024x768 */ 140 0x21, 0x08, 0x00, 141 /* 142 * Standard Timings. 143 * below new resolutions can be supported: 144 * 1920x1080, 1280x720, 1280x960, 1280x1024, 145 * 1440x900, 1600x1200, 1680x1050 146 */ 147 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 148 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 149 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 150 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 151 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 152 /* 18 Byte Data Blocks 2: invalid */ 153 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 154 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 155 /* 18 Byte Data Blocks 3: invalid */ 156 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 157 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 158 /* 18 Byte Data Blocks 4: invalid */ 159 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 160 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 161 /* Extension Block Count */ 162 0x00, 163 /* Checksum */ 164 0x45, 165 }, 166 }; 167 168 #define DPCD_HEADER_SIZE 0xb 169 170 /* let the virtual display supports DP1.2 */ 171 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 172 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 173 }; 174 175 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 176 { 177 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 178 int pipe; 179 180 if (IS_BROXTON(dev_priv)) { 181 enum transcoder trans; 182 enum port port; 183 184 /* Clear PIPE, DDI, PHY, HPD before setting new */ 185 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 186 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 187 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 188 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 189 190 for_each_pipe(dev_priv, pipe) { 191 vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &= 192 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); 193 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; 194 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 195 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; 196 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 197 } 198 199 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 200 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= 201 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 202 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 203 } 204 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 205 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 206 TRANS_DDI_PORT_MASK); 207 208 for (port = PORT_A; port <= PORT_C; port++) { 209 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 210 ~BXT_PHY_LANE_ENABLED; 211 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 212 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 213 BXT_PHY_LANE_POWERDOWN_ACK); 214 215 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 216 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 217 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 218 PORT_PLL_ENABLE); 219 220 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 221 ~(DDI_INIT_DISPLAY_DETECTED | 222 DDI_BUF_CTL_ENABLE); 223 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 224 } 225 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 226 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); 227 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 228 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); 229 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 230 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); 231 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ 232 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; 233 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; 234 235 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 236 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 237 ~PHY_POWER_GOOD; 238 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 239 ~PHY_POWER_GOOD; 240 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 241 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 242 243 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 244 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 245 246 /* 247 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 248 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 249 * TRANSCODER_A can be enabled. PORT_x depends on the input of 250 * setup_virtual_dp_monitor. 251 */ 252 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; 253 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 254 255 /* 256 * Golden M/N are calculated based on: 257 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 258 * DP link clk 1620 MHz and non-constant_n. 259 * TODO: calculate DP link symbol clk and stream clk m/n. 260 */ 261 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); 262 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 263 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 264 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 265 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 266 267 /* Enable per-DDI/PORT vreg */ 268 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 269 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 270 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 271 PHY_POWER_GOOD; 272 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 273 BIT(30); 274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 275 BXT_PHY_LANE_ENABLED; 276 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 277 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 278 BXT_PHY_LANE_POWERDOWN_ACK); 279 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 280 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 281 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 282 PORT_PLL_ENABLE); 283 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 284 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 285 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 286 ~DDI_BUF_IS_IDLE; 287 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= 288 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 289 TRANS_DDI_FUNC_ENABLE); 290 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 291 PORTA_HOTPLUG_ENABLE; 292 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 293 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 294 } 295 296 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 297 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 298 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 299 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 300 PHY_POWER_GOOD; 301 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 302 BIT(30); 303 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 304 BXT_PHY_LANE_ENABLED; 305 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 306 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 307 BXT_PHY_LANE_POWERDOWN_ACK); 308 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 309 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 310 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 311 PORT_PLL_ENABLE); 312 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 313 DDI_BUF_CTL_ENABLE; 314 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 315 ~DDI_BUF_IS_IDLE; 316 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 317 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 318 (PORT_B << TRANS_DDI_PORT_SHIFT) | 319 TRANS_DDI_FUNC_ENABLE); 320 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 321 PORTB_HOTPLUG_ENABLE; 322 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 323 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 324 } 325 326 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 327 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 328 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 329 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 330 PHY_POWER_GOOD; 331 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 332 BIT(30); 333 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 334 BXT_PHY_LANE_ENABLED; 335 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 336 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 337 BXT_PHY_LANE_POWERDOWN_ACK); 338 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 339 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 340 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 341 PORT_PLL_ENABLE); 342 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 343 DDI_BUF_CTL_ENABLE; 344 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 345 ~DDI_BUF_IS_IDLE; 346 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 347 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 348 (PORT_B << TRANS_DDI_PORT_SHIFT) | 349 TRANS_DDI_FUNC_ENABLE); 350 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 351 PORTC_HOTPLUG_ENABLE; 352 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 353 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 354 } 355 356 return; 357 } 358 359 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 360 SDE_PORTC_HOTPLUG_CPT | 361 SDE_PORTD_HOTPLUG_CPT); 362 363 if (IS_SKYLAKE(dev_priv) || 364 IS_KABYLAKE(dev_priv) || 365 IS_COFFEELAKE(dev_priv) || 366 IS_COMETLAKE(dev_priv)) { 367 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 368 SDE_PORTE_HOTPLUG_SPT); 369 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 370 SKL_FUSE_DOWNLOAD_STATUS | 371 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 372 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 373 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 374 /* 375 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 376 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 377 * TRANSCODER_A can be enabled. PORT_x depends on the input of 378 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 379 * so we fixed to DPLL0 here. 380 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 381 */ 382 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 383 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 384 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 385 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 386 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 387 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 388 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 389 /* 390 * Golden M/N are calculated based on: 391 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 392 * DP link clk 1620 MHz and non-constant_n. 393 * TODO: calculate DP link symbol clk and stream clk m/n. 394 */ 395 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); 396 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 397 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 398 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 399 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 400 } 401 402 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 403 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 404 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 405 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 406 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 407 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 408 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 409 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 410 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 411 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 412 TRANS_DDI_PORT_MASK); 413 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 414 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 415 (PORT_B << TRANS_DDI_PORT_SHIFT) | 416 TRANS_DDI_FUNC_ENABLE); 417 if (IS_BROADWELL(dev_priv)) { 418 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 419 ~PORT_CLK_SEL_MASK; 420 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 421 PORT_CLK_SEL_LCPLL_810; 422 } 423 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 424 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 425 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 426 } 427 428 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 429 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 430 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 431 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 432 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 433 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 434 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 435 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 436 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 437 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 438 TRANS_DDI_PORT_MASK); 439 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 440 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 441 (PORT_C << TRANS_DDI_PORT_SHIFT) | 442 TRANS_DDI_FUNC_ENABLE); 443 if (IS_BROADWELL(dev_priv)) { 444 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 445 ~PORT_CLK_SEL_MASK; 446 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 447 PORT_CLK_SEL_LCPLL_810; 448 } 449 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 450 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 451 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 452 } 453 454 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 455 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 456 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 457 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 458 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 459 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 460 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 461 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 462 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 463 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 464 TRANS_DDI_PORT_MASK); 465 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 466 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 467 (PORT_D << TRANS_DDI_PORT_SHIFT) | 468 TRANS_DDI_FUNC_ENABLE); 469 if (IS_BROADWELL(dev_priv)) { 470 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 471 ~PORT_CLK_SEL_MASK; 472 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 473 PORT_CLK_SEL_LCPLL_810; 474 } 475 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 476 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 477 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 478 } 479 480 if ((IS_SKYLAKE(dev_priv) || 481 IS_KABYLAKE(dev_priv) || 482 IS_COFFEELAKE(dev_priv) || 483 IS_COMETLAKE(dev_priv)) && 484 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 485 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 486 } 487 488 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 489 if (IS_BROADWELL(dev_priv)) 490 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 491 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 492 else 493 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 494 495 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 496 } 497 498 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 499 if (IS_BROADWELL(dev_priv)) 500 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 501 502 /* Disable Primary/Sprite/Cursor plane */ 503 for_each_pipe(dev_priv, pipe) { 504 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; 505 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 506 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; 507 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 508 } 509 510 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; 511 } 512 513 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 514 { 515 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 516 517 kfree(port->edid); 518 port->edid = NULL; 519 520 kfree(port->dpcd); 521 port->dpcd = NULL; 522 } 523 524 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 525 { 526 struct intel_vgpu_vblank_timer *vblank_timer; 527 struct intel_vgpu *vgpu; 528 529 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); 530 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); 531 532 /* Set vblank emulation request per-vGPU bit */ 533 intel_gvt_request_service(vgpu->gvt, 534 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); 535 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 536 return HRTIMER_RESTART; 537 } 538 539 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 540 int type, unsigned int resolution) 541 { 542 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 543 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 544 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 545 546 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 547 return -EINVAL; 548 549 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 550 if (!port->edid) 551 return -ENOMEM; 552 553 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 554 if (!port->dpcd) { 555 kfree(port->edid); 556 return -ENOMEM; 557 } 558 559 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 560 EDID_SIZE); 561 port->edid->data_valid = true; 562 563 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 564 port->dpcd->data_valid = true; 565 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 566 port->type = type; 567 port->id = resolution; 568 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; 569 vgpu->display.port_num = port_num; 570 571 /* Init hrtimer based on default refresh rate */ 572 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 573 vblank_timer->timer.function = vblank_timer_fn; 574 vblank_timer->vrefresh_k = port->vrefresh_k; 575 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 576 577 emulate_monitor_status_change(vgpu); 578 579 return 0; 580 } 581 582 /** 583 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer 584 * @vgpu: vGPU operated 585 * @turnon: Turn ON/OFF vblank_timer 586 * 587 * This function is used to turn on/off or update the per-vGPU vblank_timer 588 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated 589 * if guest changed the refresh rate. 590 * 591 */ 592 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) 593 { 594 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 595 struct intel_vgpu_port *port = 596 intel_vgpu_port(vgpu, vgpu->display.port_num); 597 598 if (turnon) { 599 /* 600 * Skip the re-enable if already active and vrefresh unchanged. 601 * Otherwise, stop timer if already active and restart with new 602 * period. 603 */ 604 if (vblank_timer->vrefresh_k != port->vrefresh_k || 605 !hrtimer_active(&vblank_timer->timer)) { 606 /* Stop timer before start with new period if active */ 607 if (hrtimer_active(&vblank_timer->timer)) 608 hrtimer_cancel(&vblank_timer->timer); 609 610 /* Make sure new refresh rate updated to timer period */ 611 vblank_timer->vrefresh_k = port->vrefresh_k; 612 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 613 hrtimer_start(&vblank_timer->timer, 614 ktime_add_ns(ktime_get(), vblank_timer->period), 615 HRTIMER_MODE_ABS); 616 } 617 } else { 618 /* Caller request to stop vblank */ 619 hrtimer_cancel(&vblank_timer->timer); 620 } 621 } 622 623 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 624 { 625 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 626 struct intel_vgpu_irq *irq = &vgpu->irq; 627 int vblank_event[] = { 628 [PIPE_A] = PIPE_A_VBLANK, 629 [PIPE_B] = PIPE_B_VBLANK, 630 [PIPE_C] = PIPE_C_VBLANK, 631 }; 632 int event; 633 634 if (pipe < PIPE_A || pipe > PIPE_C) 635 return; 636 637 for_each_set_bit(event, irq->flip_done_event[pipe], 638 INTEL_GVT_EVENT_MAX) { 639 clear_bit(event, irq->flip_done_event[pipe]); 640 if (!pipe_is_enabled(vgpu, pipe)) 641 continue; 642 643 intel_vgpu_trigger_virtual_event(vgpu, event); 644 } 645 646 if (pipe_is_enabled(vgpu, pipe)) { 647 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 648 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 649 } 650 } 651 652 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 653 { 654 int pipe; 655 656 mutex_lock(&vgpu->vgpu_lock); 657 for_each_pipe(vgpu->gvt->gt->i915, pipe) 658 emulate_vblank_on_pipe(vgpu, pipe); 659 mutex_unlock(&vgpu->vgpu_lock); 660 } 661 662 /** 663 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 664 * @vgpu: a vGPU 665 * @connected: link state 666 * 667 * This function is used to trigger hotplug interrupt for vGPU 668 * 669 */ 670 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 671 { 672 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 673 674 /* TODO: add more platforms support */ 675 if (IS_SKYLAKE(i915) || 676 IS_KABYLAKE(i915) || 677 IS_COFFEELAKE(i915) || 678 IS_COMETLAKE(i915)) { 679 if (connected) { 680 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 681 SFUSE_STRAP_DDID_DETECTED; 682 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 683 } else { 684 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 685 ~SFUSE_STRAP_DDID_DETECTED; 686 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 687 } 688 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 689 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 690 PORTD_HOTPLUG_STATUS_MASK; 691 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 692 } else if (IS_BROXTON(i915)) { 693 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 694 if (connected) { 695 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 696 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 697 } else { 698 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 699 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 700 } 701 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 702 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 703 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 704 ~PORTA_HOTPLUG_STATUS_MASK; 705 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 706 PORTA_HOTPLUG_LONG_DETECT; 707 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); 708 } 709 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 710 if (connected) { 711 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 712 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 713 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 714 SFUSE_STRAP_DDIB_DETECTED; 715 } else { 716 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 717 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 718 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 719 ~SFUSE_STRAP_DDIB_DETECTED; 720 } 721 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 722 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 723 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 724 ~PORTB_HOTPLUG_STATUS_MASK; 725 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 726 PORTB_HOTPLUG_LONG_DETECT; 727 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 728 } 729 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 730 if (connected) { 731 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 732 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 733 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 734 SFUSE_STRAP_DDIC_DETECTED; 735 } else { 736 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 737 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 738 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 739 ~SFUSE_STRAP_DDIC_DETECTED; 740 } 741 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 742 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 743 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 744 ~PORTC_HOTPLUG_STATUS_MASK; 745 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 746 PORTC_HOTPLUG_LONG_DETECT; 747 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); 748 } 749 } 750 } 751 752 /** 753 * intel_vgpu_clean_display - clean vGPU virtual display emulation 754 * @vgpu: a vGPU 755 * 756 * This function is used to clean vGPU virtual display emulation stuffs 757 * 758 */ 759 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 760 { 761 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 762 763 if (IS_SKYLAKE(dev_priv) || 764 IS_KABYLAKE(dev_priv) || 765 IS_COFFEELAKE(dev_priv) || 766 IS_COMETLAKE(dev_priv)) 767 clean_virtual_dp_monitor(vgpu, PORT_D); 768 else 769 clean_virtual_dp_monitor(vgpu, PORT_B); 770 771 vgpu_update_vblank_emulation(vgpu, false); 772 } 773 774 /** 775 * intel_vgpu_init_display- initialize vGPU virtual display emulation 776 * @vgpu: a vGPU 777 * @resolution: resolution index for intel_vgpu_edid 778 * 779 * This function is used to initialize vGPU virtual display emulation stuffs 780 * 781 * Returns: 782 * Zero on success, negative error code if failed. 783 * 784 */ 785 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 786 { 787 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 788 789 intel_vgpu_init_i2c_edid(vgpu); 790 791 if (IS_SKYLAKE(dev_priv) || 792 IS_KABYLAKE(dev_priv) || 793 IS_COFFEELAKE(dev_priv) || 794 IS_COMETLAKE(dev_priv)) 795 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 796 resolution); 797 else 798 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 799 resolution); 800 } 801 802 /** 803 * intel_vgpu_reset_display- reset vGPU virtual display emulation 804 * @vgpu: a vGPU 805 * 806 * This function is used to reset vGPU virtual display emulation stuffs 807 * 808 */ 809 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 810 { 811 emulate_monitor_status_change(vgpu); 812 } 813