1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include <drm/display/drm_dp.h> 36 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "gvt.h" 40 41 #include "display/bxt_dpio_phy_regs.h" 42 #include "display/i9xx_plane_regs.h" 43 #include "display/intel_cursor_regs.h" 44 #include "display/intel_display.h" 45 #include "display/intel_dpio_phy.h" 46 #include "display/intel_sprite_regs.h" 47 48 static int get_edp_pipe(struct intel_vgpu *vgpu) 49 { 50 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 51 int pipe = -1; 52 53 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 54 case TRANS_DDI_EDP_INPUT_A_ON: 55 case TRANS_DDI_EDP_INPUT_A_ONOFF: 56 pipe = PIPE_A; 57 break; 58 case TRANS_DDI_EDP_INPUT_B_ONOFF: 59 pipe = PIPE_B; 60 break; 61 case TRANS_DDI_EDP_INPUT_C_ONOFF: 62 pipe = PIPE_C; 63 break; 64 } 65 return pipe; 66 } 67 68 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 69 { 70 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 71 72 if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 73 return 0; 74 75 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 76 return 0; 77 return 1; 78 } 79 80 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 81 { 82 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 83 84 if (drm_WARN_ON(&dev_priv->drm, 85 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 86 return -EINVAL; 87 88 if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE) 89 return 1; 90 91 if (edp_pipe_is_enabled(vgpu) && 92 get_edp_pipe(vgpu) == pipe) 93 return 1; 94 return 0; 95 } 96 97 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 98 { 99 /* EDID with 1024x768 as its resolution */ 100 /*Header*/ 101 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 102 /* Vendor & Product Identification */ 103 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 104 /* Version & Revision */ 105 0x01, 0x04, 106 /* Basic Display Parameters & Features */ 107 0xa5, 0x34, 0x20, 0x78, 0x23, 108 /* Color Characteristics */ 109 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 110 /* Established Timings: maximum resolution is 1024x768 */ 111 0x21, 0x08, 0x00, 112 /* Standard Timings. All invalid */ 113 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 114 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 115 /* 18 Byte Data Blocks 1: invalid */ 116 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 117 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 118 /* 18 Byte Data Blocks 2: invalid */ 119 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 120 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 121 /* 18 Byte Data Blocks 3: invalid */ 122 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 123 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 124 /* 18 Byte Data Blocks 4: invalid */ 125 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 126 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 127 /* Extension Block Count */ 128 0x00, 129 /* Checksum */ 130 0xef, 131 }, 132 { 133 /* EDID with 1920x1200 as its resolution */ 134 /*Header*/ 135 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 136 /* Vendor & Product Identification */ 137 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 138 /* Version & Revision */ 139 0x01, 0x04, 140 /* Basic Display Parameters & Features */ 141 0xa5, 0x34, 0x20, 0x78, 0x23, 142 /* Color Characteristics */ 143 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 144 /* Established Timings: maximum resolution is 1024x768 */ 145 0x21, 0x08, 0x00, 146 /* 147 * Standard Timings. 148 * below new resolutions can be supported: 149 * 1920x1080, 1280x720, 1280x960, 1280x1024, 150 * 1440x900, 1600x1200, 1680x1050 151 */ 152 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 153 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 154 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 155 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 156 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 157 /* 18 Byte Data Blocks 2: invalid */ 158 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 159 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 160 /* 18 Byte Data Blocks 3: invalid */ 161 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 162 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 163 /* 18 Byte Data Blocks 4: invalid */ 164 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 165 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 166 /* Extension Block Count */ 167 0x00, 168 /* Checksum */ 169 0x45, 170 }, 171 }; 172 173 #define DPCD_HEADER_SIZE 0xb 174 175 /* let the virtual display supports DP1.2 */ 176 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 177 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 178 }; 179 180 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 181 { 182 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 183 int pipe; 184 185 if (IS_BROXTON(dev_priv)) { 186 enum transcoder trans; 187 enum port port; 188 189 /* Clear PIPE, DDI, PHY, HPD before setting new */ 190 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 191 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 192 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 193 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 194 195 for_each_pipe(dev_priv, pipe) { 196 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &= 197 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); 198 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; 199 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 200 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; 201 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; 202 } 203 204 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 205 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &= 206 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 207 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 208 } 209 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 210 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 211 TRANS_DDI_PORT_MASK); 212 213 for (port = PORT_A; port <= PORT_C; port++) { 214 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 215 ~BXT_PHY_LANE_ENABLED; 216 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 217 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 218 BXT_PHY_LANE_POWERDOWN_ACK); 219 220 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 221 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 222 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 223 PORT_PLL_ENABLE); 224 225 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 226 ~(DDI_INIT_DISPLAY_DETECTED | 227 DDI_BUF_CTL_ENABLE); 228 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 229 } 230 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 231 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); 232 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 233 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); 234 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 235 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); 236 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ 237 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; 238 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; 239 240 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 241 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 242 ~PHY_POWER_GOOD; 243 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 244 ~PHY_POWER_GOOD; 245 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 246 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 247 248 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 249 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 250 251 /* 252 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 253 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 254 * TRANSCODER_A can be enabled. PORT_x depends on the input of 255 * setup_virtual_dp_monitor. 256 */ 257 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; 258 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 259 260 /* 261 * Golden M/N are calculated based on: 262 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 263 * DP link clk 1620 MHz and non-constant_n. 264 * TODO: calculate DP link symbol clk and stream clk m/n. 265 */ 266 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); 267 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; 268 vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; 269 vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; 270 vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; 271 272 /* Enable per-DDI/PORT vreg */ 273 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 274 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 275 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 276 PHY_POWER_GOOD; 277 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 278 BIT(30); 279 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 280 BXT_PHY_LANE_ENABLED; 281 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 282 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 283 BXT_PHY_LANE_POWERDOWN_ACK); 284 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 285 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 286 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 287 PORT_PLL_ENABLE); 288 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 289 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 290 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 291 ~DDI_BUF_IS_IDLE; 292 vgpu_vreg_t(vgpu, 293 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)) |= 294 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 295 TRANS_DDI_FUNC_ENABLE); 296 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 297 PORTA_HOTPLUG_ENABLE; 298 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 299 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 300 } 301 302 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 303 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 304 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 305 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 306 PHY_POWER_GOOD; 307 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 308 BIT(30); 309 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 310 BXT_PHY_LANE_ENABLED; 311 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 312 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 313 BXT_PHY_LANE_POWERDOWN_ACK); 314 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 315 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 316 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 317 PORT_PLL_ENABLE); 318 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 319 DDI_BUF_CTL_ENABLE; 320 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 321 ~DDI_BUF_IS_IDLE; 322 vgpu_vreg_t(vgpu, 323 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 324 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 325 (PORT_B << TRANS_DDI_PORT_SHIFT) | 326 TRANS_DDI_FUNC_ENABLE); 327 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 328 PORTB_HOTPLUG_ENABLE; 329 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 330 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 331 } 332 333 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 334 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 335 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 336 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 337 PHY_POWER_GOOD; 338 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 339 BIT(30); 340 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 341 BXT_PHY_LANE_ENABLED; 342 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 343 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 344 BXT_PHY_LANE_POWERDOWN_ACK); 345 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 346 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 347 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 348 PORT_PLL_ENABLE); 349 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 350 DDI_BUF_CTL_ENABLE; 351 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 352 ~DDI_BUF_IS_IDLE; 353 vgpu_vreg_t(vgpu, 354 TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 355 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 356 (PORT_B << TRANS_DDI_PORT_SHIFT) | 357 TRANS_DDI_FUNC_ENABLE); 358 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 359 PORTC_HOTPLUG_ENABLE; 360 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 361 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 362 } 363 364 return; 365 } 366 367 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 368 SDE_PORTC_HOTPLUG_CPT | 369 SDE_PORTD_HOTPLUG_CPT); 370 371 if (IS_SKYLAKE(dev_priv) || 372 IS_KABYLAKE(dev_priv) || 373 IS_COFFEELAKE(dev_priv) || 374 IS_COMETLAKE(dev_priv)) { 375 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 376 SDE_PORTE_HOTPLUG_SPT); 377 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 378 SKL_FUSE_DOWNLOAD_STATUS | 379 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 380 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 381 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 382 /* 383 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 384 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 385 * TRANSCODER_A can be enabled. PORT_x depends on the input of 386 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 387 * so we fixed to DPLL0 here. 388 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 389 */ 390 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 391 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 392 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 393 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 394 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 395 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 396 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 397 /* 398 * Golden M/N are calculated based on: 399 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 400 * DP link clk 1620 MHz and non-constant_n. 401 * TODO: calculate DP link symbol clk and stream clk m/n. 402 */ 403 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); 404 vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; 405 vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; 406 vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; 407 vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; 408 } 409 410 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 411 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 412 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 413 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 414 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 415 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 416 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 417 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 418 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 419 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 420 TRANS_DDI_PORT_MASK); 421 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 422 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 423 (PORT_B << TRANS_DDI_PORT_SHIFT) | 424 TRANS_DDI_FUNC_ENABLE); 425 if (IS_BROADWELL(dev_priv)) { 426 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 427 ~PORT_CLK_SEL_MASK; 428 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 429 PORT_CLK_SEL_LCPLL_810; 430 } 431 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 432 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 433 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 434 } 435 436 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 437 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 438 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 439 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 440 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 441 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 442 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 443 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 444 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 445 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 446 TRANS_DDI_PORT_MASK); 447 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 448 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 449 (PORT_C << TRANS_DDI_PORT_SHIFT) | 450 TRANS_DDI_FUNC_ENABLE); 451 if (IS_BROADWELL(dev_priv)) { 452 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 453 ~PORT_CLK_SEL_MASK; 454 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 455 PORT_CLK_SEL_LCPLL_810; 456 } 457 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 458 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 459 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 460 } 461 462 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 463 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 464 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 465 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 466 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 467 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 468 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 469 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 470 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= 471 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 472 TRANS_DDI_PORT_MASK); 473 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= 474 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 475 (PORT_D << TRANS_DDI_PORT_SHIFT) | 476 TRANS_DDI_FUNC_ENABLE); 477 if (IS_BROADWELL(dev_priv)) { 478 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 479 ~PORT_CLK_SEL_MASK; 480 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 481 PORT_CLK_SEL_LCPLL_810; 482 } 483 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 484 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 485 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 486 } 487 488 if ((IS_SKYLAKE(dev_priv) || 489 IS_KABYLAKE(dev_priv) || 490 IS_COFFEELAKE(dev_priv) || 491 IS_COMETLAKE(dev_priv)) && 492 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 493 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 494 } 495 496 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 497 if (IS_BROADWELL(dev_priv)) 498 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 499 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 500 else 501 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 502 503 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 504 } 505 506 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 507 if (IS_BROADWELL(dev_priv)) 508 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 509 510 /* Disable Primary/Sprite/Cursor plane */ 511 for_each_pipe(dev_priv, pipe) { 512 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; 513 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 514 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; 515 vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; 516 } 517 518 vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; 519 } 520 521 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 522 { 523 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 524 525 kfree(port->edid); 526 port->edid = NULL; 527 528 kfree(port->dpcd); 529 port->dpcd = NULL; 530 } 531 532 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 533 { 534 struct intel_vgpu_vblank_timer *vblank_timer; 535 struct intel_vgpu *vgpu; 536 537 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); 538 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); 539 540 /* Set vblank emulation request per-vGPU bit */ 541 intel_gvt_request_service(vgpu->gvt, 542 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); 543 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 544 return HRTIMER_RESTART; 545 } 546 547 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 548 int type, unsigned int resolution) 549 { 550 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 551 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 552 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 553 554 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 555 return -EINVAL; 556 557 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 558 if (!port->edid) 559 return -ENOMEM; 560 561 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 562 if (!port->dpcd) { 563 kfree(port->edid); 564 return -ENOMEM; 565 } 566 567 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 568 EDID_SIZE); 569 port->edid->data_valid = true; 570 571 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 572 port->dpcd->data_valid = true; 573 port->dpcd->data[DP_SINK_COUNT] = 0x1; 574 port->type = type; 575 port->id = resolution; 576 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; 577 vgpu->display.port_num = port_num; 578 579 /* Init hrtimer based on default refresh rate */ 580 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 581 vblank_timer->timer.function = vblank_timer_fn; 582 vblank_timer->vrefresh_k = port->vrefresh_k; 583 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 584 585 emulate_monitor_status_change(vgpu); 586 587 return 0; 588 } 589 590 /** 591 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer 592 * @vgpu: vGPU operated 593 * @turnon: Turn ON/OFF vblank_timer 594 * 595 * This function is used to turn on/off or update the per-vGPU vblank_timer 596 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated 597 * if guest changed the refresh rate. 598 * 599 */ 600 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) 601 { 602 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 603 struct intel_vgpu_port *port = 604 intel_vgpu_port(vgpu, vgpu->display.port_num); 605 606 if (turnon) { 607 /* 608 * Skip the re-enable if already active and vrefresh unchanged. 609 * Otherwise, stop timer if already active and restart with new 610 * period. 611 */ 612 if (vblank_timer->vrefresh_k != port->vrefresh_k || 613 !hrtimer_active(&vblank_timer->timer)) { 614 /* Stop timer before start with new period if active */ 615 if (hrtimer_active(&vblank_timer->timer)) 616 hrtimer_cancel(&vblank_timer->timer); 617 618 /* Make sure new refresh rate updated to timer period */ 619 vblank_timer->vrefresh_k = port->vrefresh_k; 620 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 621 hrtimer_start(&vblank_timer->timer, 622 ktime_add_ns(ktime_get(), vblank_timer->period), 623 HRTIMER_MODE_ABS); 624 } 625 } else { 626 /* Caller request to stop vblank */ 627 hrtimer_cancel(&vblank_timer->timer); 628 } 629 } 630 631 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 632 { 633 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 634 struct intel_vgpu_irq *irq = &vgpu->irq; 635 int vblank_event[] = { 636 [PIPE_A] = PIPE_A_VBLANK, 637 [PIPE_B] = PIPE_B_VBLANK, 638 [PIPE_C] = PIPE_C_VBLANK, 639 }; 640 int event; 641 642 if (pipe < PIPE_A || pipe > PIPE_C) 643 return; 644 645 for_each_set_bit(event, irq->flip_done_event[pipe], 646 INTEL_GVT_EVENT_MAX) { 647 clear_bit(event, irq->flip_done_event[pipe]); 648 if (!pipe_is_enabled(vgpu, pipe)) 649 continue; 650 651 intel_vgpu_trigger_virtual_event(vgpu, event); 652 } 653 654 if (pipe_is_enabled(vgpu, pipe)) { 655 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++; 656 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 657 } 658 } 659 660 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 661 { 662 int pipe; 663 664 mutex_lock(&vgpu->vgpu_lock); 665 for_each_pipe(vgpu->gvt->gt->i915, pipe) 666 emulate_vblank_on_pipe(vgpu, pipe); 667 mutex_unlock(&vgpu->vgpu_lock); 668 } 669 670 /** 671 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 672 * @vgpu: a vGPU 673 * @connected: link state 674 * 675 * This function is used to trigger hotplug interrupt for vGPU 676 * 677 */ 678 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 679 { 680 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 681 682 /* TODO: add more platforms support */ 683 if (IS_SKYLAKE(i915) || 684 IS_KABYLAKE(i915) || 685 IS_COFFEELAKE(i915) || 686 IS_COMETLAKE(i915)) { 687 if (connected) { 688 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 689 SFUSE_STRAP_DDID_DETECTED; 690 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 691 } else { 692 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 693 ~SFUSE_STRAP_DDID_DETECTED; 694 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 695 } 696 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 697 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 698 PORTD_HOTPLUG_STATUS_MASK; 699 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 700 } else if (IS_BROXTON(i915)) { 701 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 702 if (connected) { 703 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 704 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 705 } else { 706 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 707 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 708 } 709 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 710 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 711 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 712 ~PORTA_HOTPLUG_STATUS_MASK; 713 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 714 PORTA_HOTPLUG_LONG_DETECT; 715 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); 716 } 717 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 718 if (connected) { 719 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 720 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 721 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 722 SFUSE_STRAP_DDIB_DETECTED; 723 } else { 724 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 725 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 726 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 727 ~SFUSE_STRAP_DDIB_DETECTED; 728 } 729 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 730 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 731 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 732 ~PORTB_HOTPLUG_STATUS_MASK; 733 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 734 PORTB_HOTPLUG_LONG_DETECT; 735 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 736 } 737 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 738 if (connected) { 739 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 740 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 741 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 742 SFUSE_STRAP_DDIC_DETECTED; 743 } else { 744 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 745 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 746 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 747 ~SFUSE_STRAP_DDIC_DETECTED; 748 } 749 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 750 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 751 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 752 ~PORTC_HOTPLUG_STATUS_MASK; 753 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 754 PORTC_HOTPLUG_LONG_DETECT; 755 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); 756 } 757 } 758 } 759 760 /** 761 * intel_vgpu_clean_display - clean vGPU virtual display emulation 762 * @vgpu: a vGPU 763 * 764 * This function is used to clean vGPU virtual display emulation stuffs 765 * 766 */ 767 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 768 { 769 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 770 771 if (IS_SKYLAKE(dev_priv) || 772 IS_KABYLAKE(dev_priv) || 773 IS_COFFEELAKE(dev_priv) || 774 IS_COMETLAKE(dev_priv)) 775 clean_virtual_dp_monitor(vgpu, PORT_D); 776 else 777 clean_virtual_dp_monitor(vgpu, PORT_B); 778 779 vgpu_update_vblank_emulation(vgpu, false); 780 } 781 782 /** 783 * intel_vgpu_init_display- initialize vGPU virtual display emulation 784 * @vgpu: a vGPU 785 * @resolution: resolution index for intel_vgpu_edid 786 * 787 * This function is used to initialize vGPU virtual display emulation stuffs 788 * 789 * Returns: 790 * Zero on success, negative error code if failed. 791 * 792 */ 793 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 794 { 795 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 796 797 intel_vgpu_init_i2c_edid(vgpu); 798 799 if (IS_SKYLAKE(dev_priv) || 800 IS_KABYLAKE(dev_priv) || 801 IS_COFFEELAKE(dev_priv) || 802 IS_COMETLAKE(dev_priv)) 803 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 804 resolution); 805 else 806 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 807 resolution); 808 } 809 810 /** 811 * intel_vgpu_reset_display- reset vGPU virtual display emulation 812 * @vgpu: a vGPU 813 * 814 * This function is used to reset vGPU virtual display emulation stuffs 815 * 816 */ 817 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 818 { 819 emulate_monitor_status_change(vgpu); 820 } 821