1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "gvt.h" 37 38 static int get_edp_pipe(struct intel_vgpu *vgpu) 39 { 40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 41 int pipe = -1; 42 43 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 44 case TRANS_DDI_EDP_INPUT_A_ON: 45 case TRANS_DDI_EDP_INPUT_A_ONOFF: 46 pipe = PIPE_A; 47 break; 48 case TRANS_DDI_EDP_INPUT_B_ONOFF: 49 pipe = PIPE_B; 50 break; 51 case TRANS_DDI_EDP_INPUT_C_ONOFF: 52 pipe = PIPE_C; 53 break; 54 } 55 return pipe; 56 } 57 58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 59 { 60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 61 62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) 63 return 0; 64 65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 66 return 0; 67 return 1; 68 } 69 70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 71 { 72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 73 74 if (drm_WARN_ON(&dev_priv->drm, 75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 76 return -EINVAL; 77 78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) 79 return 1; 80 81 if (edp_pipe_is_enabled(vgpu) && 82 get_edp_pipe(vgpu) == pipe) 83 return 1; 84 return 0; 85 } 86 87 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 88 { 89 /* EDID with 1024x768 as its resolution */ 90 /*Header*/ 91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 92 /* Vendor & Product Identification */ 93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 94 /* Version & Revision */ 95 0x01, 0x04, 96 /* Basic Display Parameters & Features */ 97 0xa5, 0x34, 0x20, 0x78, 0x23, 98 /* Color Characteristics */ 99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 100 /* Established Timings: maximum resolution is 1024x768 */ 101 0x21, 0x08, 0x00, 102 /* Standard Timings. All invalid */ 103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 105 /* 18 Byte Data Blocks 1: invalid */ 106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 108 /* 18 Byte Data Blocks 2: invalid */ 109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 111 /* 18 Byte Data Blocks 3: invalid */ 112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 114 /* 18 Byte Data Blocks 4: invalid */ 115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 117 /* Extension Block Count */ 118 0x00, 119 /* Checksum */ 120 0xef, 121 }, 122 { 123 /* EDID with 1920x1200 as its resolution */ 124 /*Header*/ 125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 126 /* Vendor & Product Identification */ 127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 128 /* Version & Revision */ 129 0x01, 0x04, 130 /* Basic Display Parameters & Features */ 131 0xa5, 0x34, 0x20, 0x78, 0x23, 132 /* Color Characteristics */ 133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 134 /* Established Timings: maximum resolution is 1024x768 */ 135 0x21, 0x08, 0x00, 136 /* 137 * Standard Timings. 138 * below new resolutions can be supported: 139 * 1920x1080, 1280x720, 1280x960, 1280x1024, 140 * 1440x900, 1600x1200, 1680x1050 141 */ 142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 144 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 147 /* 18 Byte Data Blocks 2: invalid */ 148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 150 /* 18 Byte Data Blocks 3: invalid */ 151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 153 /* 18 Byte Data Blocks 4: invalid */ 154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 156 /* Extension Block Count */ 157 0x00, 158 /* Checksum */ 159 0x45, 160 }, 161 }; 162 163 #define DPCD_HEADER_SIZE 0xb 164 165 /* let the virtual display supports DP1.2 */ 166 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 167 0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 168 }; 169 170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 171 { 172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 173 int pipe; 174 175 if (IS_BROXTON(dev_priv)) { 176 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA | 177 BXT_DE_PORT_HP_DDIB | 178 BXT_DE_PORT_HP_DDIC); 179 180 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 181 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 182 BXT_DE_PORT_HP_DDIA; 183 } 184 185 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 186 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 187 BXT_DE_PORT_HP_DDIB; 188 } 189 190 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 191 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 192 BXT_DE_PORT_HP_DDIC; 193 } 194 195 return; 196 } 197 198 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 199 SDE_PORTC_HOTPLUG_CPT | 200 SDE_PORTD_HOTPLUG_CPT); 201 202 if (IS_SKYLAKE(dev_priv) || 203 IS_KABYLAKE(dev_priv) || 204 IS_COFFEELAKE(dev_priv) || 205 IS_COMETLAKE(dev_priv)) { 206 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 207 SDE_PORTE_HOTPLUG_SPT); 208 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 209 SKL_FUSE_DOWNLOAD_STATUS | 210 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 211 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 212 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 213 vgpu_vreg_t(vgpu, LCPLL1_CTL) |= 214 LCPLL_PLL_ENABLE | 215 LCPLL_PLL_LOCK; 216 vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE; 217 218 } 219 220 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 221 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 222 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 223 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 224 TRANS_DDI_PORT_MASK); 225 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 226 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 227 (PORT_B << TRANS_DDI_PORT_SHIFT) | 228 TRANS_DDI_FUNC_ENABLE); 229 if (IS_BROADWELL(dev_priv)) { 230 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 231 ~PORT_CLK_SEL_MASK; 232 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 233 PORT_CLK_SEL_LCPLL_810; 234 } 235 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 236 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 237 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 238 } 239 240 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 241 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 242 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 243 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 244 TRANS_DDI_PORT_MASK); 245 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 246 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 247 (PORT_C << TRANS_DDI_PORT_SHIFT) | 248 TRANS_DDI_FUNC_ENABLE); 249 if (IS_BROADWELL(dev_priv)) { 250 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 251 ~PORT_CLK_SEL_MASK; 252 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 253 PORT_CLK_SEL_LCPLL_810; 254 } 255 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 256 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 257 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 258 } 259 260 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 261 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 262 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 263 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 264 TRANS_DDI_PORT_MASK); 265 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 266 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 267 (PORT_D << TRANS_DDI_PORT_SHIFT) | 268 TRANS_DDI_FUNC_ENABLE); 269 if (IS_BROADWELL(dev_priv)) { 270 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 271 ~PORT_CLK_SEL_MASK; 272 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 273 PORT_CLK_SEL_LCPLL_810; 274 } 275 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 276 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 277 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 278 } 279 280 if ((IS_SKYLAKE(dev_priv) || 281 IS_KABYLAKE(dev_priv) || 282 IS_COFFEELAKE(dev_priv) || 283 IS_COMETLAKE(dev_priv)) && 284 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 285 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 286 } 287 288 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 289 if (IS_BROADWELL(dev_priv)) 290 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 291 GEN8_PORT_DP_A_HOTPLUG; 292 else 293 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 294 295 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 296 } 297 298 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 299 if (IS_BROADWELL(dev_priv)) 300 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 301 302 /* Disable Primary/Sprite/Cursor plane */ 303 for_each_pipe(dev_priv, pipe) { 304 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; 305 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 306 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE; 307 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 308 } 309 310 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; 311 } 312 313 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 314 { 315 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 316 317 kfree(port->edid); 318 port->edid = NULL; 319 320 kfree(port->dpcd); 321 port->dpcd = NULL; 322 } 323 324 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 325 int type, unsigned int resolution) 326 { 327 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 328 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 329 330 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 331 return -EINVAL; 332 333 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 334 if (!port->edid) 335 return -ENOMEM; 336 337 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 338 if (!port->dpcd) { 339 kfree(port->edid); 340 return -ENOMEM; 341 } 342 343 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 344 EDID_SIZE); 345 port->edid->data_valid = true; 346 347 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 348 port->dpcd->data_valid = true; 349 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 350 port->type = type; 351 port->id = resolution; 352 353 emulate_monitor_status_change(vgpu); 354 355 return 0; 356 } 357 358 /** 359 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should 360 * be turned on/off when a virtual pipe is enabled/disabled. 361 * @gvt: a GVT device 362 * 363 * This function is used to turn on/off vblank timer according to currently 364 * enabled/disabled virtual pipes. 365 * 366 */ 367 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt) 368 { 369 struct intel_gvt_irq *irq = &gvt->irq; 370 struct intel_vgpu *vgpu; 371 int pipe, id; 372 int found = false; 373 374 mutex_lock(&gvt->lock); 375 for_each_active_vgpu(gvt, vgpu, id) { 376 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { 377 if (pipe_is_enabled(vgpu, pipe)) { 378 found = true; 379 break; 380 } 381 } 382 if (found) 383 break; 384 } 385 386 /* all the pipes are disabled */ 387 if (!found) 388 hrtimer_cancel(&irq->vblank_timer.timer); 389 else 390 hrtimer_start(&irq->vblank_timer.timer, 391 ktime_add_ns(ktime_get(), irq->vblank_timer.period), 392 HRTIMER_MODE_ABS); 393 mutex_unlock(&gvt->lock); 394 } 395 396 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 397 { 398 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 399 struct intel_vgpu_irq *irq = &vgpu->irq; 400 int vblank_event[] = { 401 [PIPE_A] = PIPE_A_VBLANK, 402 [PIPE_B] = PIPE_B_VBLANK, 403 [PIPE_C] = PIPE_C_VBLANK, 404 }; 405 int event; 406 407 if (pipe < PIPE_A || pipe > PIPE_C) 408 return; 409 410 for_each_set_bit(event, irq->flip_done_event[pipe], 411 INTEL_GVT_EVENT_MAX) { 412 clear_bit(event, irq->flip_done_event[pipe]); 413 if (!pipe_is_enabled(vgpu, pipe)) 414 continue; 415 416 intel_vgpu_trigger_virtual_event(vgpu, event); 417 } 418 419 if (pipe_is_enabled(vgpu, pipe)) { 420 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 421 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 422 } 423 } 424 425 static void emulate_vblank(struct intel_vgpu *vgpu) 426 { 427 int pipe; 428 429 mutex_lock(&vgpu->vgpu_lock); 430 for_each_pipe(vgpu->gvt->gt->i915, pipe) 431 emulate_vblank_on_pipe(vgpu, pipe); 432 mutex_unlock(&vgpu->vgpu_lock); 433 } 434 435 /** 436 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device 437 * @gvt: a GVT device 438 * 439 * This function is used to trigger vblank interrupts for vGPUs on GVT device 440 * 441 */ 442 void intel_gvt_emulate_vblank(struct intel_gvt *gvt) 443 { 444 struct intel_vgpu *vgpu; 445 int id; 446 447 mutex_lock(&gvt->lock); 448 for_each_active_vgpu(gvt, vgpu, id) 449 emulate_vblank(vgpu); 450 mutex_unlock(&gvt->lock); 451 } 452 453 /** 454 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 455 * @vgpu: a vGPU 456 * @connected: link state 457 * 458 * This function is used to trigger hotplug interrupt for vGPU 459 * 460 */ 461 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 462 { 463 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 464 465 /* TODO: add more platforms support */ 466 if (IS_SKYLAKE(i915) || 467 IS_KABYLAKE(i915) || 468 IS_COFFEELAKE(i915) || 469 IS_COMETLAKE(i915)) { 470 if (connected) { 471 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 472 SFUSE_STRAP_DDID_DETECTED; 473 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 474 } else { 475 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 476 ~SFUSE_STRAP_DDID_DETECTED; 477 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 478 } 479 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 480 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 481 PORTD_HOTPLUG_STATUS_MASK; 482 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 483 } 484 } 485 486 /** 487 * intel_vgpu_clean_display - clean vGPU virtual display emulation 488 * @vgpu: a vGPU 489 * 490 * This function is used to clean vGPU virtual display emulation stuffs 491 * 492 */ 493 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 494 { 495 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 496 497 if (IS_SKYLAKE(dev_priv) || 498 IS_KABYLAKE(dev_priv) || 499 IS_COFFEELAKE(dev_priv) || 500 IS_COMETLAKE(dev_priv)) 501 clean_virtual_dp_monitor(vgpu, PORT_D); 502 else 503 clean_virtual_dp_monitor(vgpu, PORT_B); 504 } 505 506 /** 507 * intel_vgpu_init_display- initialize vGPU virtual display emulation 508 * @vgpu: a vGPU 509 * @resolution: resolution index for intel_vgpu_edid 510 * 511 * This function is used to initialize vGPU virtual display emulation stuffs 512 * 513 * Returns: 514 * Zero on success, negative error code if failed. 515 * 516 */ 517 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 518 { 519 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 520 521 intel_vgpu_init_i2c_edid(vgpu); 522 523 if (IS_SKYLAKE(dev_priv) || 524 IS_KABYLAKE(dev_priv) || 525 IS_COFFEELAKE(dev_priv) || 526 IS_COMETLAKE(dev_priv)) 527 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 528 resolution); 529 else 530 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 531 resolution); 532 } 533 534 /** 535 * intel_vgpu_reset_display- reset vGPU virtual display emulation 536 * @vgpu: a vGPU 537 * 538 * This function is used to reset vGPU virtual display emulation stuffs 539 * 540 */ 541 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 542 { 543 emulate_monitor_status_change(vgpu); 544 } 545