1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "gvt.h" 38 39 #include "display/bxt_dpio_phy_regs.h" 40 #include "display/intel_display.h" 41 #include "display/intel_dpio_phy.h" 42 #include "display/intel_sprite_regs.h" 43 44 static int get_edp_pipe(struct intel_vgpu *vgpu) 45 { 46 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 47 int pipe = -1; 48 49 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 50 case TRANS_DDI_EDP_INPUT_A_ON: 51 case TRANS_DDI_EDP_INPUT_A_ONOFF: 52 pipe = PIPE_A; 53 break; 54 case TRANS_DDI_EDP_INPUT_B_ONOFF: 55 pipe = PIPE_B; 56 break; 57 case TRANS_DDI_EDP_INPUT_C_ONOFF: 58 pipe = PIPE_C; 59 break; 60 } 61 return pipe; 62 } 63 64 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 65 { 66 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 67 68 if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 69 return 0; 70 71 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 72 return 0; 73 return 1; 74 } 75 76 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 77 { 78 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 79 80 if (drm_WARN_ON(&dev_priv->drm, 81 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 82 return -EINVAL; 83 84 if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE) 85 return 1; 86 87 if (edp_pipe_is_enabled(vgpu) && 88 get_edp_pipe(vgpu) == pipe) 89 return 1; 90 return 0; 91 } 92 93 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 94 { 95 /* EDID with 1024x768 as its resolution */ 96 /*Header*/ 97 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 98 /* Vendor & Product Identification */ 99 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 100 /* Version & Revision */ 101 0x01, 0x04, 102 /* Basic Display Parameters & Features */ 103 0xa5, 0x34, 0x20, 0x78, 0x23, 104 /* Color Characteristics */ 105 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 106 /* Established Timings: maximum resolution is 1024x768 */ 107 0x21, 0x08, 0x00, 108 /* Standard Timings. All invalid */ 109 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 110 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 111 /* 18 Byte Data Blocks 1: invalid */ 112 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 113 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 114 /* 18 Byte Data Blocks 2: invalid */ 115 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 116 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 117 /* 18 Byte Data Blocks 3: invalid */ 118 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 119 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 120 /* 18 Byte Data Blocks 4: invalid */ 121 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 122 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 123 /* Extension Block Count */ 124 0x00, 125 /* Checksum */ 126 0xef, 127 }, 128 { 129 /* EDID with 1920x1200 as its resolution */ 130 /*Header*/ 131 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 132 /* Vendor & Product Identification */ 133 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 134 /* Version & Revision */ 135 0x01, 0x04, 136 /* Basic Display Parameters & Features */ 137 0xa5, 0x34, 0x20, 0x78, 0x23, 138 /* Color Characteristics */ 139 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 140 /* Established Timings: maximum resolution is 1024x768 */ 141 0x21, 0x08, 0x00, 142 /* 143 * Standard Timings. 144 * below new resolutions can be supported: 145 * 1920x1080, 1280x720, 1280x960, 1280x1024, 146 * 1440x900, 1600x1200, 1680x1050 147 */ 148 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 149 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 150 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 151 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 152 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 153 /* 18 Byte Data Blocks 2: invalid */ 154 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 155 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 156 /* 18 Byte Data Blocks 3: invalid */ 157 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 158 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 159 /* 18 Byte Data Blocks 4: invalid */ 160 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 161 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 162 /* Extension Block Count */ 163 0x00, 164 /* Checksum */ 165 0x45, 166 }, 167 }; 168 169 #define DPCD_HEADER_SIZE 0xb 170 171 /* let the virtual display supports DP1.2 */ 172 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 173 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 174 }; 175 176 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 177 { 178 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 179 int pipe; 180 181 if (IS_BROXTON(dev_priv)) { 182 enum transcoder trans; 183 enum port port; 184 185 /* Clear PIPE, DDI, PHY, HPD before setting new */ 186 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 187 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 188 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 189 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 190 191 for_each_pipe(dev_priv, pipe) { 192 vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &= 193 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); 194 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; 195 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 196 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; 197 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 198 } 199 200 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 201 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= 202 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 203 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 204 } 205 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 206 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 207 TRANS_DDI_PORT_MASK); 208 209 for (port = PORT_A; port <= PORT_C; port++) { 210 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 211 ~BXT_PHY_LANE_ENABLED; 212 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 213 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 214 BXT_PHY_LANE_POWERDOWN_ACK); 215 216 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 217 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 218 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 219 PORT_PLL_ENABLE); 220 221 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 222 ~(DDI_INIT_DISPLAY_DETECTED | 223 DDI_BUF_CTL_ENABLE); 224 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 225 } 226 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 227 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); 228 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 229 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); 230 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 231 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); 232 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ 233 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; 234 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; 235 236 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 237 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 238 ~PHY_POWER_GOOD; 239 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 240 ~PHY_POWER_GOOD; 241 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 242 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 243 244 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 245 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 246 247 /* 248 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 249 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 250 * TRANSCODER_A can be enabled. PORT_x depends on the input of 251 * setup_virtual_dp_monitor. 252 */ 253 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; 254 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 255 256 /* 257 * Golden M/N are calculated based on: 258 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 259 * DP link clk 1620 MHz and non-constant_n. 260 * TODO: calculate DP link symbol clk and stream clk m/n. 261 */ 262 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); 263 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 264 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 265 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 266 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 267 268 /* Enable per-DDI/PORT vreg */ 269 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 270 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 271 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 272 PHY_POWER_GOOD; 273 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 274 BIT(30); 275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 276 BXT_PHY_LANE_ENABLED; 277 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 278 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 279 BXT_PHY_LANE_POWERDOWN_ACK); 280 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 281 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 282 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 283 PORT_PLL_ENABLE); 284 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 285 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 286 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 287 ~DDI_BUF_IS_IDLE; 288 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= 289 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 290 TRANS_DDI_FUNC_ENABLE); 291 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 292 PORTA_HOTPLUG_ENABLE; 293 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 294 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 295 } 296 297 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 298 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 299 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 300 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 301 PHY_POWER_GOOD; 302 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 303 BIT(30); 304 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 305 BXT_PHY_LANE_ENABLED; 306 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 307 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 308 BXT_PHY_LANE_POWERDOWN_ACK); 309 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 310 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 311 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 312 PORT_PLL_ENABLE); 313 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 314 DDI_BUF_CTL_ENABLE; 315 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 316 ~DDI_BUF_IS_IDLE; 317 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 318 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 319 (PORT_B << TRANS_DDI_PORT_SHIFT) | 320 TRANS_DDI_FUNC_ENABLE); 321 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 322 PORTB_HOTPLUG_ENABLE; 323 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 324 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 325 } 326 327 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 328 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 329 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 330 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 331 PHY_POWER_GOOD; 332 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 333 BIT(30); 334 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 335 BXT_PHY_LANE_ENABLED; 336 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 337 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 338 BXT_PHY_LANE_POWERDOWN_ACK); 339 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 340 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 341 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 342 PORT_PLL_ENABLE); 343 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 344 DDI_BUF_CTL_ENABLE; 345 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 346 ~DDI_BUF_IS_IDLE; 347 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 348 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 349 (PORT_B << TRANS_DDI_PORT_SHIFT) | 350 TRANS_DDI_FUNC_ENABLE); 351 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 352 PORTC_HOTPLUG_ENABLE; 353 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 354 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 355 } 356 357 return; 358 } 359 360 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 361 SDE_PORTC_HOTPLUG_CPT | 362 SDE_PORTD_HOTPLUG_CPT); 363 364 if (IS_SKYLAKE(dev_priv) || 365 IS_KABYLAKE(dev_priv) || 366 IS_COFFEELAKE(dev_priv) || 367 IS_COMETLAKE(dev_priv)) { 368 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 369 SDE_PORTE_HOTPLUG_SPT); 370 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 371 SKL_FUSE_DOWNLOAD_STATUS | 372 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 373 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 374 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 375 /* 376 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 377 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 378 * TRANSCODER_A can be enabled. PORT_x depends on the input of 379 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 380 * so we fixed to DPLL0 here. 381 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 382 */ 383 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 384 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 385 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 386 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 387 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 388 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 389 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 390 /* 391 * Golden M/N are calculated based on: 392 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 393 * DP link clk 1620 MHz and non-constant_n. 394 * TODO: calculate DP link symbol clk and stream clk m/n. 395 */ 396 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); 397 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; 398 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; 399 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; 400 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; 401 } 402 403 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 404 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 405 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 406 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 407 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 408 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 409 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 410 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 411 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 412 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 413 TRANS_DDI_PORT_MASK); 414 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 415 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 416 (PORT_B << TRANS_DDI_PORT_SHIFT) | 417 TRANS_DDI_FUNC_ENABLE); 418 if (IS_BROADWELL(dev_priv)) { 419 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 420 ~PORT_CLK_SEL_MASK; 421 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 422 PORT_CLK_SEL_LCPLL_810; 423 } 424 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 425 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 426 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 427 } 428 429 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 430 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 431 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 432 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 433 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 434 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 435 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 436 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 437 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 438 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 439 TRANS_DDI_PORT_MASK); 440 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 441 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 442 (PORT_C << TRANS_DDI_PORT_SHIFT) | 443 TRANS_DDI_FUNC_ENABLE); 444 if (IS_BROADWELL(dev_priv)) { 445 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 446 ~PORT_CLK_SEL_MASK; 447 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 448 PORT_CLK_SEL_LCPLL_810; 449 } 450 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 451 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 452 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 453 } 454 455 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 456 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 457 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 458 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 459 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 460 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 461 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 462 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 463 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= 464 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 465 TRANS_DDI_PORT_MASK); 466 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= 467 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 468 (PORT_D << TRANS_DDI_PORT_SHIFT) | 469 TRANS_DDI_FUNC_ENABLE); 470 if (IS_BROADWELL(dev_priv)) { 471 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 472 ~PORT_CLK_SEL_MASK; 473 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 474 PORT_CLK_SEL_LCPLL_810; 475 } 476 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 477 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 478 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 479 } 480 481 if ((IS_SKYLAKE(dev_priv) || 482 IS_KABYLAKE(dev_priv) || 483 IS_COFFEELAKE(dev_priv) || 484 IS_COMETLAKE(dev_priv)) && 485 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 486 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 487 } 488 489 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 490 if (IS_BROADWELL(dev_priv)) 491 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 492 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 493 else 494 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 495 496 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 497 } 498 499 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 500 if (IS_BROADWELL(dev_priv)) 501 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 502 503 /* Disable Primary/Sprite/Cursor plane */ 504 for_each_pipe(dev_priv, pipe) { 505 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; 506 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 507 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; 508 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; 509 } 510 511 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; 512 } 513 514 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 515 { 516 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 517 518 kfree(port->edid); 519 port->edid = NULL; 520 521 kfree(port->dpcd); 522 port->dpcd = NULL; 523 } 524 525 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 526 { 527 struct intel_vgpu_vblank_timer *vblank_timer; 528 struct intel_vgpu *vgpu; 529 530 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); 531 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); 532 533 /* Set vblank emulation request per-vGPU bit */ 534 intel_gvt_request_service(vgpu->gvt, 535 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); 536 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 537 return HRTIMER_RESTART; 538 } 539 540 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 541 int type, unsigned int resolution) 542 { 543 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 544 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 545 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 546 547 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 548 return -EINVAL; 549 550 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 551 if (!port->edid) 552 return -ENOMEM; 553 554 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 555 if (!port->dpcd) { 556 kfree(port->edid); 557 return -ENOMEM; 558 } 559 560 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 561 EDID_SIZE); 562 port->edid->data_valid = true; 563 564 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 565 port->dpcd->data_valid = true; 566 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; 567 port->type = type; 568 port->id = resolution; 569 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; 570 vgpu->display.port_num = port_num; 571 572 /* Init hrtimer based on default refresh rate */ 573 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 574 vblank_timer->timer.function = vblank_timer_fn; 575 vblank_timer->vrefresh_k = port->vrefresh_k; 576 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 577 578 emulate_monitor_status_change(vgpu); 579 580 return 0; 581 } 582 583 /** 584 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer 585 * @vgpu: vGPU operated 586 * @turnon: Turn ON/OFF vblank_timer 587 * 588 * This function is used to turn on/off or update the per-vGPU vblank_timer 589 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated 590 * if guest changed the refresh rate. 591 * 592 */ 593 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) 594 { 595 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 596 struct intel_vgpu_port *port = 597 intel_vgpu_port(vgpu, vgpu->display.port_num); 598 599 if (turnon) { 600 /* 601 * Skip the re-enable if already active and vrefresh unchanged. 602 * Otherwise, stop timer if already active and restart with new 603 * period. 604 */ 605 if (vblank_timer->vrefresh_k != port->vrefresh_k || 606 !hrtimer_active(&vblank_timer->timer)) { 607 /* Stop timer before start with new period if active */ 608 if (hrtimer_active(&vblank_timer->timer)) 609 hrtimer_cancel(&vblank_timer->timer); 610 611 /* Make sure new refresh rate updated to timer period */ 612 vblank_timer->vrefresh_k = port->vrefresh_k; 613 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 614 hrtimer_start(&vblank_timer->timer, 615 ktime_add_ns(ktime_get(), vblank_timer->period), 616 HRTIMER_MODE_ABS); 617 } 618 } else { 619 /* Caller request to stop vblank */ 620 hrtimer_cancel(&vblank_timer->timer); 621 } 622 } 623 624 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 625 { 626 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 627 struct intel_vgpu_irq *irq = &vgpu->irq; 628 int vblank_event[] = { 629 [PIPE_A] = PIPE_A_VBLANK, 630 [PIPE_B] = PIPE_B_VBLANK, 631 [PIPE_C] = PIPE_C_VBLANK, 632 }; 633 int event; 634 635 if (pipe < PIPE_A || pipe > PIPE_C) 636 return; 637 638 for_each_set_bit(event, irq->flip_done_event[pipe], 639 INTEL_GVT_EVENT_MAX) { 640 clear_bit(event, irq->flip_done_event[pipe]); 641 if (!pipe_is_enabled(vgpu, pipe)) 642 continue; 643 644 intel_vgpu_trigger_virtual_event(vgpu, event); 645 } 646 647 if (pipe_is_enabled(vgpu, pipe)) { 648 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; 649 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 650 } 651 } 652 653 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 654 { 655 int pipe; 656 657 mutex_lock(&vgpu->vgpu_lock); 658 for_each_pipe(vgpu->gvt->gt->i915, pipe) 659 emulate_vblank_on_pipe(vgpu, pipe); 660 mutex_unlock(&vgpu->vgpu_lock); 661 } 662 663 /** 664 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 665 * @vgpu: a vGPU 666 * @connected: link state 667 * 668 * This function is used to trigger hotplug interrupt for vGPU 669 * 670 */ 671 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 672 { 673 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 674 675 /* TODO: add more platforms support */ 676 if (IS_SKYLAKE(i915) || 677 IS_KABYLAKE(i915) || 678 IS_COFFEELAKE(i915) || 679 IS_COMETLAKE(i915)) { 680 if (connected) { 681 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 682 SFUSE_STRAP_DDID_DETECTED; 683 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 684 } else { 685 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 686 ~SFUSE_STRAP_DDID_DETECTED; 687 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 688 } 689 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 690 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 691 PORTD_HOTPLUG_STATUS_MASK; 692 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 693 } else if (IS_BROXTON(i915)) { 694 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 695 if (connected) { 696 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 697 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 698 } else { 699 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 700 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 701 } 702 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 703 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 704 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 705 ~PORTA_HOTPLUG_STATUS_MASK; 706 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 707 PORTA_HOTPLUG_LONG_DETECT; 708 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); 709 } 710 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 711 if (connected) { 712 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 713 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 714 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 715 SFUSE_STRAP_DDIB_DETECTED; 716 } else { 717 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 718 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 719 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 720 ~SFUSE_STRAP_DDIB_DETECTED; 721 } 722 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 723 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 724 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 725 ~PORTB_HOTPLUG_STATUS_MASK; 726 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 727 PORTB_HOTPLUG_LONG_DETECT; 728 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 729 } 730 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 731 if (connected) { 732 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 733 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 734 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 735 SFUSE_STRAP_DDIC_DETECTED; 736 } else { 737 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 738 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 739 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 740 ~SFUSE_STRAP_DDIC_DETECTED; 741 } 742 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 743 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 744 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 745 ~PORTC_HOTPLUG_STATUS_MASK; 746 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 747 PORTC_HOTPLUG_LONG_DETECT; 748 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); 749 } 750 } 751 } 752 753 /** 754 * intel_vgpu_clean_display - clean vGPU virtual display emulation 755 * @vgpu: a vGPU 756 * 757 * This function is used to clean vGPU virtual display emulation stuffs 758 * 759 */ 760 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 761 { 762 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 763 764 if (IS_SKYLAKE(dev_priv) || 765 IS_KABYLAKE(dev_priv) || 766 IS_COFFEELAKE(dev_priv) || 767 IS_COMETLAKE(dev_priv)) 768 clean_virtual_dp_monitor(vgpu, PORT_D); 769 else 770 clean_virtual_dp_monitor(vgpu, PORT_B); 771 772 vgpu_update_vblank_emulation(vgpu, false); 773 } 774 775 /** 776 * intel_vgpu_init_display- initialize vGPU virtual display emulation 777 * @vgpu: a vGPU 778 * @resolution: resolution index for intel_vgpu_edid 779 * 780 * This function is used to initialize vGPU virtual display emulation stuffs 781 * 782 * Returns: 783 * Zero on success, negative error code if failed. 784 * 785 */ 786 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 787 { 788 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 789 790 intel_vgpu_init_i2c_edid(vgpu); 791 792 if (IS_SKYLAKE(dev_priv) || 793 IS_KABYLAKE(dev_priv) || 794 IS_COFFEELAKE(dev_priv) || 795 IS_COMETLAKE(dev_priv)) 796 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 797 resolution); 798 else 799 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 800 resolution); 801 } 802 803 /** 804 * intel_vgpu_reset_display- reset vGPU virtual display emulation 805 * @vgpu: a vGPU 806 * 807 * This function is used to reset vGPU virtual display emulation stuffs 808 * 809 */ 810 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 811 { 812 emulate_monitor_status_change(vgpu); 813 } 814