1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include <drm/display/drm_dp.h> 36 37 #include "i915_drv.h" 38 #include "i915_reg.h" 39 #include "display/intel_display_regs.h" 40 #include "gvt.h" 41 42 #include "display/bxt_dpio_phy_regs.h" 43 #include "display/i9xx_plane_regs.h" 44 #include "display/intel_crt_regs.h" 45 #include "display/intel_cursor_regs.h" 46 #include "display/intel_display.h" 47 #include "display/intel_display_core.h" 48 #include "display/intel_dpio_phy.h" 49 #include "display/intel_sprite_regs.h" 50 51 static int get_edp_pipe(struct intel_vgpu *vgpu) 52 { 53 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 54 int pipe = -1; 55 56 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 57 case TRANS_DDI_EDP_INPUT_A_ON: 58 case TRANS_DDI_EDP_INPUT_A_ONOFF: 59 pipe = PIPE_A; 60 break; 61 case TRANS_DDI_EDP_INPUT_B_ONOFF: 62 pipe = PIPE_B; 63 break; 64 case TRANS_DDI_EDP_INPUT_C_ONOFF: 65 pipe = PIPE_C; 66 break; 67 } 68 return pipe; 69 } 70 71 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 72 { 73 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 74 struct intel_display *display = dev_priv->display; 75 76 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 77 return 0; 78 79 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 80 return 0; 81 return 1; 82 } 83 84 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 85 { 86 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 87 struct intel_display *display = dev_priv->display; 88 89 if (drm_WARN_ON(&dev_priv->drm, 90 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 91 return -EINVAL; 92 93 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) 94 return 1; 95 96 if (edp_pipe_is_enabled(vgpu) && 97 get_edp_pipe(vgpu) == pipe) 98 return 1; 99 return 0; 100 } 101 102 static const unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 103 { 104 /* EDID with 1024x768 as its resolution */ 105 /*Header*/ 106 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 107 /* Vendor & Product Identification */ 108 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 109 /* Version & Revision */ 110 0x01, 0x04, 111 /* Basic Display Parameters & Features */ 112 0xa5, 0x34, 0x20, 0x78, 0x23, 113 /* Color Characteristics */ 114 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 115 /* Established Timings: maximum resolution is 1024x768 */ 116 0x21, 0x08, 0x00, 117 /* Standard Timings. All invalid */ 118 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 119 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 120 /* 18 Byte Data Blocks 1: invalid */ 121 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 122 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 123 /* 18 Byte Data Blocks 2: invalid */ 124 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 125 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 126 /* 18 Byte Data Blocks 3: invalid */ 127 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 128 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 129 /* 18 Byte Data Blocks 4: invalid */ 130 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 131 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 132 /* Extension Block Count */ 133 0x00, 134 /* Checksum */ 135 0xef, 136 }, 137 { 138 /* EDID with 1920x1200 as its resolution */ 139 /*Header*/ 140 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 141 /* Vendor & Product Identification */ 142 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 143 /* Version & Revision */ 144 0x01, 0x04, 145 /* Basic Display Parameters & Features */ 146 0xa5, 0x34, 0x20, 0x78, 0x23, 147 /* Color Characteristics */ 148 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 149 /* Established Timings: maximum resolution is 1024x768 */ 150 0x21, 0x08, 0x00, 151 /* 152 * Standard Timings. 153 * below new resolutions can be supported: 154 * 1920x1080, 1280x720, 1280x960, 1280x1024, 155 * 1440x900, 1600x1200, 1680x1050 156 */ 157 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 158 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 159 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 160 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 161 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 162 /* 18 Byte Data Blocks 2: invalid */ 163 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 164 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 165 /* 18 Byte Data Blocks 3: invalid */ 166 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 167 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 168 /* 18 Byte Data Blocks 4: invalid */ 169 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 170 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 171 /* Extension Block Count */ 172 0x00, 173 /* Checksum */ 174 0x45, 175 }, 176 }; 177 178 #define DPCD_HEADER_SIZE 0xb 179 180 /* let the virtual display supports DP1.2 */ 181 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 182 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 183 }; 184 185 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 186 { 187 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 188 struct intel_display *display = dev_priv->display; 189 int pipe; 190 191 if (IS_BROXTON(dev_priv)) { 192 enum transcoder trans; 193 enum port port; 194 195 /* Clear PIPE, DDI, PHY, HPD before setting new */ 196 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 197 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 198 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 199 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 200 201 for_each_pipe(display, pipe) { 202 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &= 203 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); 204 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 205 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 206 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 207 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 208 } 209 210 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 211 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &= 212 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 213 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 214 } 215 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 216 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 217 TRANS_DDI_PORT_MASK); 218 219 for (port = PORT_A; port <= PORT_C; port++) { 220 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 221 ~BXT_PHY_LANE_ENABLED; 222 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 223 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 224 BXT_PHY_LANE_POWERDOWN_ACK); 225 226 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 227 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 228 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 229 PORT_PLL_ENABLE); 230 231 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 232 ~(DDI_INIT_DISPLAY_DETECTED | 233 DDI_BUF_CTL_ENABLE); 234 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 235 } 236 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 237 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); 238 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 239 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); 240 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 241 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); 242 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ 243 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; 244 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; 245 246 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 247 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 248 ~PHY_POWER_GOOD; 249 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 250 ~PHY_POWER_GOOD; 251 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 252 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 253 254 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 255 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 256 257 /* 258 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 259 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 260 * TRANSCODER_A can be enabled. PORT_x depends on the input of 261 * setup_virtual_dp_monitor. 262 */ 263 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 264 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 265 266 /* 267 * Golden M/N are calculated based on: 268 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 269 * DP link clk 1620 MHz and non-constant_n. 270 * TODO: calculate DP link symbol clk and stream clk m/n. 271 */ 272 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 273 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 274 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 275 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 276 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 277 278 /* Enable per-DDI/PORT vreg */ 279 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 280 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 281 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 282 PHY_POWER_GOOD; 283 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 284 BIT(30); 285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 286 BXT_PHY_LANE_ENABLED; 287 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 288 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 289 BXT_PHY_LANE_POWERDOWN_ACK); 290 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 291 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 292 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 293 PORT_PLL_ENABLE); 294 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 295 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 296 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 297 ~DDI_BUF_IS_IDLE; 298 vgpu_vreg_t(vgpu, 299 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |= 300 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 301 TRANS_DDI_FUNC_ENABLE); 302 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 303 PORTA_HOTPLUG_ENABLE; 304 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 305 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 306 } 307 308 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 309 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 310 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 311 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 312 PHY_POWER_GOOD; 313 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 314 BIT(30); 315 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 316 BXT_PHY_LANE_ENABLED; 317 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 318 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 319 BXT_PHY_LANE_POWERDOWN_ACK); 320 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 321 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 322 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 323 PORT_PLL_ENABLE); 324 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 325 DDI_BUF_CTL_ENABLE; 326 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 327 ~DDI_BUF_IS_IDLE; 328 vgpu_vreg_t(vgpu, 329 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 330 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 331 (PORT_B << TRANS_DDI_PORT_SHIFT) | 332 TRANS_DDI_FUNC_ENABLE); 333 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 334 PORTB_HOTPLUG_ENABLE; 335 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 336 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 337 } 338 339 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 340 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 341 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 342 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 343 PHY_POWER_GOOD; 344 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 345 BIT(30); 346 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 347 BXT_PHY_LANE_ENABLED; 348 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 349 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 350 BXT_PHY_LANE_POWERDOWN_ACK); 351 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 352 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 353 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 354 PORT_PLL_ENABLE); 355 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 356 DDI_BUF_CTL_ENABLE; 357 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 358 ~DDI_BUF_IS_IDLE; 359 vgpu_vreg_t(vgpu, 360 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 361 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 362 (PORT_B << TRANS_DDI_PORT_SHIFT) | 363 TRANS_DDI_FUNC_ENABLE); 364 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 365 PORTC_HOTPLUG_ENABLE; 366 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 367 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 368 } 369 370 return; 371 } 372 373 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 374 SDE_PORTC_HOTPLUG_CPT | 375 SDE_PORTD_HOTPLUG_CPT); 376 377 if (IS_SKYLAKE(dev_priv) || 378 IS_KABYLAKE(dev_priv) || 379 IS_COFFEELAKE(dev_priv) || 380 IS_COMETLAKE(dev_priv)) { 381 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 382 SDE_PORTE_HOTPLUG_SPT); 383 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 384 SKL_FUSE_DOWNLOAD_STATUS | 385 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 386 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 387 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 388 /* 389 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 390 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 391 * TRANSCODER_A can be enabled. PORT_x depends on the input of 392 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 393 * so we fixed to DPLL0 here. 394 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 395 */ 396 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 397 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 398 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 399 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 400 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 401 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 402 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 403 /* 404 * Golden M/N are calculated based on: 405 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 406 * DP link clk 1620 MHz and non-constant_n. 407 * TODO: calculate DP link symbol clk and stream clk m/n. 408 */ 409 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 410 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 411 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 412 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 413 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 414 } 415 416 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 417 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 418 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 419 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 420 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 421 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 422 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 423 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 424 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 425 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 426 TRANS_DDI_PORT_MASK); 427 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 428 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 429 (PORT_B << TRANS_DDI_PORT_SHIFT) | 430 TRANS_DDI_FUNC_ENABLE); 431 if (IS_BROADWELL(dev_priv)) { 432 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 433 ~PORT_CLK_SEL_MASK; 434 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 435 PORT_CLK_SEL_LCPLL_810; 436 } 437 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 438 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 439 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 440 } 441 442 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 443 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 444 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 445 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 446 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 447 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 448 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 449 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 450 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 451 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 452 TRANS_DDI_PORT_MASK); 453 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 454 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 455 (PORT_C << TRANS_DDI_PORT_SHIFT) | 456 TRANS_DDI_FUNC_ENABLE); 457 if (IS_BROADWELL(dev_priv)) { 458 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 459 ~PORT_CLK_SEL_MASK; 460 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 461 PORT_CLK_SEL_LCPLL_810; 462 } 463 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 464 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 465 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 466 } 467 468 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 469 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 470 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 471 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 472 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 473 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 474 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 475 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 476 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 477 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 478 TRANS_DDI_PORT_MASK); 479 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 480 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 481 (PORT_D << TRANS_DDI_PORT_SHIFT) | 482 TRANS_DDI_FUNC_ENABLE); 483 if (IS_BROADWELL(dev_priv)) { 484 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 485 ~PORT_CLK_SEL_MASK; 486 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 487 PORT_CLK_SEL_LCPLL_810; 488 } 489 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 491 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 492 } 493 494 if ((IS_SKYLAKE(dev_priv) || 495 IS_KABYLAKE(dev_priv) || 496 IS_COFFEELAKE(dev_priv) || 497 IS_COMETLAKE(dev_priv)) && 498 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 499 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 500 } 501 502 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 503 if (IS_BROADWELL(dev_priv)) 504 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 505 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 506 else 507 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 508 509 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 510 } 511 512 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 513 if (IS_BROADWELL(dev_priv)) 514 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 515 516 /* Disable Primary/Sprite/Cursor plane */ 517 for_each_pipe(display, pipe) { 518 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 519 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 520 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 521 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 522 } 523 524 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 525 } 526 527 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 528 { 529 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 530 531 kfree(port->edid); 532 port->edid = NULL; 533 534 kfree(port->dpcd); 535 port->dpcd = NULL; 536 } 537 538 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 539 { 540 struct intel_vgpu_vblank_timer *vblank_timer; 541 struct intel_vgpu *vgpu; 542 543 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); 544 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); 545 546 /* Set vblank emulation request per-vGPU bit */ 547 intel_gvt_request_service(vgpu->gvt, 548 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); 549 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 550 return HRTIMER_RESTART; 551 } 552 553 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 554 int type, unsigned int resolution) 555 { 556 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 557 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 558 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 559 560 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 561 return -EINVAL; 562 563 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL); 564 if (!port->edid) 565 return -ENOMEM; 566 567 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); 568 if (!port->dpcd) { 569 kfree(port->edid); 570 return -ENOMEM; 571 } 572 573 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 574 EDID_SIZE); 575 port->edid->data_valid = true; 576 577 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 578 port->dpcd->data_valid = true; 579 port->dpcd->data[DP_SINK_COUNT] = 0x1; 580 port->type = type; 581 port->id = resolution; 582 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; 583 vgpu->display.port_num = port_num; 584 585 /* Init hrtimer based on default refresh rate */ 586 hrtimer_setup(&vblank_timer->timer, vblank_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 587 vblank_timer->vrefresh_k = port->vrefresh_k; 588 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 589 590 emulate_monitor_status_change(vgpu); 591 592 return 0; 593 } 594 595 /** 596 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer 597 * @vgpu: vGPU operated 598 * @turnon: Turn ON/OFF vblank_timer 599 * 600 * This function is used to turn on/off or update the per-vGPU vblank_timer 601 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated 602 * if guest changed the refresh rate. 603 * 604 */ 605 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) 606 { 607 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 608 struct intel_vgpu_port *port = 609 intel_vgpu_port(vgpu, vgpu->display.port_num); 610 611 if (turnon) { 612 /* 613 * Skip the re-enable if already active and vrefresh unchanged. 614 * Otherwise, stop timer if already active and restart with new 615 * period. 616 */ 617 if (vblank_timer->vrefresh_k != port->vrefresh_k || 618 !hrtimer_active(&vblank_timer->timer)) { 619 /* Stop timer before start with new period if active */ 620 if (hrtimer_active(&vblank_timer->timer)) 621 hrtimer_cancel(&vblank_timer->timer); 622 623 /* Make sure new refresh rate updated to timer period */ 624 vblank_timer->vrefresh_k = port->vrefresh_k; 625 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 626 hrtimer_start(&vblank_timer->timer, 627 ktime_add_ns(ktime_get(), vblank_timer->period), 628 HRTIMER_MODE_ABS); 629 } 630 } else { 631 /* Caller request to stop vblank */ 632 hrtimer_cancel(&vblank_timer->timer); 633 } 634 } 635 636 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 637 { 638 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 639 struct intel_display *display = dev_priv->display; 640 struct intel_vgpu_irq *irq = &vgpu->irq; 641 int vblank_event[] = { 642 [PIPE_A] = PIPE_A_VBLANK, 643 [PIPE_B] = PIPE_B_VBLANK, 644 [PIPE_C] = PIPE_C_VBLANK, 645 }; 646 int event; 647 648 if (pipe < PIPE_A || pipe > PIPE_C) 649 return; 650 651 for_each_set_bit(event, irq->flip_done_event[pipe], 652 INTEL_GVT_EVENT_MAX) { 653 clear_bit(event, irq->flip_done_event[pipe]); 654 if (!pipe_is_enabled(vgpu, pipe)) 655 continue; 656 657 intel_vgpu_trigger_virtual_event(vgpu, event); 658 } 659 660 if (pipe_is_enabled(vgpu, pipe)) { 661 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++; 662 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 663 } 664 } 665 666 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 667 { 668 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 669 struct intel_display *display = i915->display; 670 int pipe; 671 672 mutex_lock(&vgpu->vgpu_lock); 673 for_each_pipe(display, pipe) 674 emulate_vblank_on_pipe(vgpu, pipe); 675 mutex_unlock(&vgpu->vgpu_lock); 676 } 677 678 /** 679 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 680 * @vgpu: a vGPU 681 * @connected: link state 682 * 683 * This function is used to trigger hotplug interrupt for vGPU 684 * 685 */ 686 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 687 { 688 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 689 690 /* TODO: add more platforms support */ 691 if (IS_SKYLAKE(i915) || 692 IS_KABYLAKE(i915) || 693 IS_COFFEELAKE(i915) || 694 IS_COMETLAKE(i915)) { 695 if (connected) { 696 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 697 SFUSE_STRAP_DDID_DETECTED; 698 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 699 } else { 700 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 701 ~SFUSE_STRAP_DDID_DETECTED; 702 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 703 } 704 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 705 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 706 PORTD_HOTPLUG_STATUS_MASK; 707 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 708 } else if (IS_BROXTON(i915)) { 709 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 710 if (connected) { 711 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 712 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 713 } else { 714 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 715 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 716 } 717 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 718 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 719 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 720 ~PORTA_HOTPLUG_STATUS_MASK; 721 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 722 PORTA_HOTPLUG_LONG_DETECT; 723 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); 724 } 725 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 726 if (connected) { 727 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 728 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 729 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 730 SFUSE_STRAP_DDIB_DETECTED; 731 } else { 732 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 733 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 734 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 735 ~SFUSE_STRAP_DDIB_DETECTED; 736 } 737 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 738 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 739 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 740 ~PORTB_HOTPLUG_STATUS_MASK; 741 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 742 PORTB_HOTPLUG_LONG_DETECT; 743 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 744 } 745 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 746 if (connected) { 747 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 748 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 749 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 750 SFUSE_STRAP_DDIC_DETECTED; 751 } else { 752 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 753 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 754 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 755 ~SFUSE_STRAP_DDIC_DETECTED; 756 } 757 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 758 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 759 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 760 ~PORTC_HOTPLUG_STATUS_MASK; 761 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 762 PORTC_HOTPLUG_LONG_DETECT; 763 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); 764 } 765 } 766 } 767 768 /** 769 * intel_vgpu_clean_display - clean vGPU virtual display emulation 770 * @vgpu: a vGPU 771 * 772 * This function is used to clean vGPU virtual display emulation stuffs 773 * 774 */ 775 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 776 { 777 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 778 779 if (IS_SKYLAKE(dev_priv) || 780 IS_KABYLAKE(dev_priv) || 781 IS_COFFEELAKE(dev_priv) || 782 IS_COMETLAKE(dev_priv)) 783 clean_virtual_dp_monitor(vgpu, PORT_D); 784 else 785 clean_virtual_dp_monitor(vgpu, PORT_B); 786 787 vgpu_update_vblank_emulation(vgpu, false); 788 } 789 790 /** 791 * intel_vgpu_init_display- initialize vGPU virtual display emulation 792 * @vgpu: a vGPU 793 * @resolution: resolution index for intel_vgpu_edid 794 * 795 * This function is used to initialize vGPU virtual display emulation stuffs 796 * 797 * Returns: 798 * Zero on success, negative error code if failed. 799 * 800 */ 801 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 802 { 803 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 804 805 intel_vgpu_init_i2c_edid(vgpu); 806 807 if (IS_SKYLAKE(dev_priv) || 808 IS_KABYLAKE(dev_priv) || 809 IS_COFFEELAKE(dev_priv) || 810 IS_COMETLAKE(dev_priv)) 811 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 812 resolution); 813 else 814 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 815 resolution); 816 } 817 818 /** 819 * intel_vgpu_reset_display- reset vGPU virtual display emulation 820 * @vgpu: a vGPU 821 * 822 * This function is used to reset vGPU virtual display emulation stuffs 823 * 824 */ 825 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 826 { 827 emulate_monitor_status_change(vgpu); 828 } 829