1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Ke Yu 25 * Zhiyuan Lv <zhiyuan.lv@intel.com> 26 * 27 * Contributors: 28 * Terrence Xu <terrence.xu@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Bing Niu <bing.niu@intel.com> 31 * Zhi Wang <zhi.a.wang@intel.com> 32 * 33 */ 34 35 #include <drm/display/drm_dp.h> 36 #include <drm/drm_print.h> 37 38 #include "display/bxt_dpio_phy_regs.h" 39 #include "display/i9xx_plane_regs.h" 40 #include "display/intel_crt_regs.h" 41 #include "display/intel_cursor_regs.h" 42 #include "display/intel_display.h" 43 #include "display/intel_display_regs.h" 44 #include "display/intel_dpio_phy.h" 45 #include "display/intel_dpll_mgr.h" 46 #include "display/intel_sprite_regs.h" 47 48 #include "display_helpers.h" 49 #include "gvt.h" 50 #include "i915_drv.h" 51 #include "i915_reg.h" 52 53 static int get_edp_pipe(struct intel_vgpu *vgpu) 54 { 55 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); 56 int pipe = -1; 57 58 switch (data & TRANS_DDI_EDP_INPUT_MASK) { 59 case TRANS_DDI_EDP_INPUT_A_ON: 60 case TRANS_DDI_EDP_INPUT_A_ONOFF: 61 pipe = PIPE_A; 62 break; 63 case TRANS_DDI_EDP_INPUT_B_ONOFF: 64 pipe = PIPE_B; 65 break; 66 case TRANS_DDI_EDP_INPUT_C_ONOFF: 67 pipe = PIPE_C; 68 break; 69 } 70 return pipe; 71 } 72 73 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 74 { 75 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 76 struct intel_display *display = dev_priv->display; 77 78 if (!(vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) 79 return 0; 80 81 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) 82 return 0; 83 return 1; 84 } 85 86 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 87 { 88 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 89 struct intel_display *display = dev_priv->display; 90 91 if (drm_WARN_ON(&dev_priv->drm, 92 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) 93 return -EINVAL; 94 95 if (vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) & TRANSCONF_ENABLE) 96 return 1; 97 98 if (edp_pipe_is_enabled(vgpu) && 99 get_edp_pipe(vgpu) == pipe) 100 return 1; 101 return 0; 102 } 103 104 static const unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 105 { 106 /* EDID with 1024x768 as its resolution */ 107 /*Header*/ 108 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 109 /* Vendor & Product Identification */ 110 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 111 /* Version & Revision */ 112 0x01, 0x04, 113 /* Basic Display Parameters & Features */ 114 0xa5, 0x34, 0x20, 0x78, 0x23, 115 /* Color Characteristics */ 116 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 117 /* Established Timings: maximum resolution is 1024x768 */ 118 0x21, 0x08, 0x00, 119 /* Standard Timings. All invalid */ 120 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, 121 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, 122 /* 18 Byte Data Blocks 1: invalid */ 123 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, 124 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 125 /* 18 Byte Data Blocks 2: invalid */ 126 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 127 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 128 /* 18 Byte Data Blocks 3: invalid */ 129 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 130 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 131 /* 18 Byte Data Blocks 4: invalid */ 132 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 133 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 134 /* Extension Block Count */ 135 0x00, 136 /* Checksum */ 137 0xef, 138 }, 139 { 140 /* EDID with 1920x1200 as its resolution */ 141 /*Header*/ 142 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 143 /* Vendor & Product Identification */ 144 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, 145 /* Version & Revision */ 146 0x01, 0x04, 147 /* Basic Display Parameters & Features */ 148 0xa5, 0x34, 0x20, 0x78, 0x23, 149 /* Color Characteristics */ 150 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, 151 /* Established Timings: maximum resolution is 1024x768 */ 152 0x21, 0x08, 0x00, 153 /* 154 * Standard Timings. 155 * below new resolutions can be supported: 156 * 1920x1080, 1280x720, 1280x960, 1280x1024, 157 * 1440x900, 1600x1200, 1680x1050 158 */ 159 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 160 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, 161 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ 162 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 163 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, 164 /* 18 Byte Data Blocks 2: invalid */ 165 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, 166 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 167 /* 18 Byte Data Blocks 3: invalid */ 168 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, 169 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, 170 /* 18 Byte Data Blocks 4: invalid */ 171 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, 172 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, 173 /* Extension Block Count */ 174 0x00, 175 /* Checksum */ 176 0x45, 177 }, 178 }; 179 180 #define DPCD_HEADER_SIZE 0xb 181 182 /* let the virtual display supports DP1.2 */ 183 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 184 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 185 }; 186 187 static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 188 { 189 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 190 struct intel_display *display = dev_priv->display; 191 enum pipe pipe; 192 193 if (IS_BROXTON(dev_priv)) { 194 enum transcoder trans; 195 enum port port; 196 197 /* Clear PIPE, DDI, PHY, HPD before setting new */ 198 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 199 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | 200 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | 201 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); 202 203 gvt_for_each_pipe(display, pipe) { 204 vgpu_vreg_t(vgpu, TRANSCONF(display, pipe)) &= 205 ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); 206 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 207 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 208 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 209 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 210 } 211 212 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { 213 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, trans)) &= 214 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 215 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); 216 } 217 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 218 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 219 TRANS_DDI_PORT_MASK); 220 221 for (port = PORT_A; port <= PORT_C; port++) { 222 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= 223 ~BXT_PHY_LANE_ENABLED; 224 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= 225 (BXT_PHY_CMNLANE_POWERDOWN_ACK | 226 BXT_PHY_LANE_POWERDOWN_ACK); 227 228 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= 229 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 230 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 231 PORT_PLL_ENABLE); 232 233 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= 234 ~(DDI_INIT_DISPLAY_DETECTED | 235 DDI_BUF_CTL_ENABLE); 236 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; 237 } 238 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 239 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); 240 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 241 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); 242 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 243 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); 244 /* No hpd_invert set in vgpu vbt, need to clear invert mask */ 245 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; 246 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; 247 248 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); 249 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 250 ~PHY_POWER_GOOD; 251 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 252 ~PHY_POWER_GOOD; 253 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); 254 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); 255 256 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; 257 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; 258 259 /* 260 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 261 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 262 * TRANSCODER_A can be enabled. PORT_x depends on the input of 263 * setup_virtual_dp_monitor. 264 */ 265 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 266 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; 267 268 /* 269 * Golden M/N are calculated based on: 270 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 271 * DP link clk 1620 MHz and non-constant_n. 272 * TODO: calculate DP link symbol clk and stream clk m/n. 273 */ 274 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 275 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 276 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 277 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 278 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 279 280 /* Enable per-DDI/PORT vreg */ 281 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 282 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); 283 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 284 PHY_POWER_GOOD; 285 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= 286 BIT(30); 287 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= 288 BXT_PHY_LANE_ENABLED; 289 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= 290 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 291 BXT_PHY_LANE_POWERDOWN_ACK); 292 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= 293 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 294 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 295 PORT_PLL_ENABLE); 296 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= 297 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); 298 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= 299 ~DDI_BUF_IS_IDLE; 300 vgpu_vreg_t(vgpu, 301 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)) |= 302 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 303 TRANS_DDI_FUNC_ENABLE); 304 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 305 PORTA_HOTPLUG_ENABLE; 306 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 307 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 308 } 309 310 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 311 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 312 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 313 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 314 PHY_POWER_GOOD; 315 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 316 BIT(30); 317 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= 318 BXT_PHY_LANE_ENABLED; 319 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= 320 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 321 BXT_PHY_LANE_POWERDOWN_ACK); 322 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= 323 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 324 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 325 PORT_PLL_ENABLE); 326 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= 327 DDI_BUF_CTL_ENABLE; 328 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= 329 ~DDI_BUF_IS_IDLE; 330 vgpu_vreg_t(vgpu, 331 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 332 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 333 (PORT_B << TRANS_DDI_PORT_SHIFT) | 334 TRANS_DDI_FUNC_ENABLE); 335 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 336 PORTB_HOTPLUG_ENABLE; 337 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 338 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 339 } 340 341 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 342 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 343 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); 344 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 345 PHY_POWER_GOOD; 346 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= 347 BIT(30); 348 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= 349 BXT_PHY_LANE_ENABLED; 350 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= 351 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | 352 BXT_PHY_LANE_POWERDOWN_ACK); 353 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= 354 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | 355 PORT_PLL_REF_SEL | PORT_PLL_LOCK | 356 PORT_PLL_ENABLE); 357 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= 358 DDI_BUF_CTL_ENABLE; 359 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= 360 ~DDI_BUF_IS_IDLE; 361 vgpu_vreg_t(vgpu, 362 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 363 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 364 (PORT_B << TRANS_DDI_PORT_SHIFT) | 365 TRANS_DDI_FUNC_ENABLE); 366 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 367 PORTC_HOTPLUG_ENABLE; 368 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 369 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 370 } 371 372 return; 373 } 374 375 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | 376 SDE_PORTC_HOTPLUG_CPT | 377 SDE_PORTD_HOTPLUG_CPT); 378 379 if (IS_SKYLAKE(dev_priv) || 380 IS_KABYLAKE(dev_priv) || 381 IS_COFFEELAKE(dev_priv) || 382 IS_COMETLAKE(dev_priv)) { 383 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | 384 SDE_PORTE_HOTPLUG_SPT); 385 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= 386 SKL_FUSE_DOWNLOAD_STATUS | 387 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | 388 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | 389 SKL_FUSE_PG_DIST_STATUS(SKL_PG2); 390 /* 391 * Only 1 PIPE enabled in current vGPU display and PIPE_A is 392 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, 393 * TRANSCODER_A can be enabled. PORT_x depends on the input of 394 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x 395 * so we fixed to DPLL0 here. 396 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode 397 */ 398 vgpu_vreg_t(vgpu, DPLL_CTRL1) = 399 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); 400 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= 401 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); 402 vgpu_vreg_t(vgpu, LCPLL1_CTL) = 403 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; 404 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); 405 /* 406 * Golden M/N are calculated based on: 407 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), 408 * DP link clk 1620 MHz and non-constant_n. 409 * TODO: calculate DP link symbol clk and stream clk m/n. 410 */ 411 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); 412 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; 413 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; 414 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; 415 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; 416 } 417 418 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 419 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 420 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); 421 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 422 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); 423 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 424 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); 425 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; 426 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 427 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 428 TRANS_DDI_PORT_MASK); 429 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 430 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 431 (PORT_B << TRANS_DDI_PORT_SHIFT) | 432 TRANS_DDI_FUNC_ENABLE); 433 if (IS_BROADWELL(dev_priv)) { 434 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= 435 ~PORT_CLK_SEL_MASK; 436 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= 437 PORT_CLK_SEL_LCPLL_810; 438 } 439 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; 440 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; 441 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; 442 } 443 444 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 445 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 446 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); 447 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 448 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); 449 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 450 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); 451 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; 452 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 453 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 454 TRANS_DDI_PORT_MASK); 455 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 456 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 457 (PORT_C << TRANS_DDI_PORT_SHIFT) | 458 TRANS_DDI_FUNC_ENABLE); 459 if (IS_BROADWELL(dev_priv)) { 460 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= 461 ~PORT_CLK_SEL_MASK; 462 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= 463 PORT_CLK_SEL_LCPLL_810; 464 } 465 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; 466 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; 467 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; 468 } 469 470 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { 471 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= 472 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); 473 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 474 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); 475 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= 476 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); 477 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 478 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= 479 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | 480 TRANS_DDI_PORT_MASK); 481 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= 482 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | 483 (PORT_D << TRANS_DDI_PORT_SHIFT) | 484 TRANS_DDI_FUNC_ENABLE); 485 if (IS_BROADWELL(dev_priv)) { 486 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= 487 ~PORT_CLK_SEL_MASK; 488 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= 489 PORT_CLK_SEL_LCPLL_810; 490 } 491 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; 492 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; 493 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; 494 } 495 496 if ((IS_SKYLAKE(dev_priv) || 497 IS_KABYLAKE(dev_priv) || 498 IS_COFFEELAKE(dev_priv) || 499 IS_COMETLAKE(dev_priv)) && 500 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { 501 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; 502 } 503 504 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 505 if (IS_BROADWELL(dev_priv)) 506 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 507 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 508 else 509 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; 510 511 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; 512 } 513 514 /* Clear host CRT status, so guest couldn't detect this host CRT. */ 515 if (IS_BROADWELL(dev_priv)) 516 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; 517 518 /* Disable Primary/Sprite/Cursor plane */ 519 gvt_for_each_pipe(display, pipe) { 520 vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE; 521 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; 522 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) &= ~MCURSOR_MODE_MASK; 523 vgpu_vreg_t(vgpu, CURCNTR(display, pipe)) |= MCURSOR_MODE_DISABLE; 524 } 525 526 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; 527 } 528 529 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 530 { 531 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 532 533 kfree(port->edid); 534 port->edid = NULL; 535 536 kfree(port->dpcd); 537 port->dpcd = NULL; 538 } 539 540 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) 541 { 542 struct intel_vgpu_vblank_timer *vblank_timer; 543 struct intel_vgpu *vgpu; 544 545 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); 546 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); 547 548 /* Set vblank emulation request per-vGPU bit */ 549 intel_gvt_request_service(vgpu->gvt, 550 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); 551 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period); 552 return HRTIMER_RESTART; 553 } 554 555 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 556 int type, unsigned int resolution) 557 { 558 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 559 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 560 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 561 562 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) 563 return -EINVAL; 564 565 port->edid = kzalloc_obj(*(port->edid)); 566 if (!port->edid) 567 return -ENOMEM; 568 569 port->dpcd = kzalloc_obj(*(port->dpcd)); 570 if (!port->dpcd) { 571 kfree(port->edid); 572 return -ENOMEM; 573 } 574 575 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], 576 EDID_SIZE); 577 port->edid->data_valid = true; 578 579 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); 580 port->dpcd->data_valid = true; 581 port->dpcd->data[DP_SINK_COUNT] = 0x1; 582 port->type = type; 583 port->id = resolution; 584 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; 585 vgpu->display.port_num = port_num; 586 587 /* Init hrtimer based on default refresh rate */ 588 hrtimer_setup(&vblank_timer->timer, vblank_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 589 vblank_timer->vrefresh_k = port->vrefresh_k; 590 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 591 592 emulate_monitor_status_change(vgpu); 593 594 return 0; 595 } 596 597 /** 598 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer 599 * @vgpu: vGPU operated 600 * @turnon: Turn ON/OFF vblank_timer 601 * 602 * This function is used to turn on/off or update the per-vGPU vblank_timer 603 * when TRANSCONF is enabled or disabled. vblank_timer period is also updated 604 * if guest changed the refresh rate. 605 * 606 */ 607 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) 608 { 609 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; 610 struct intel_vgpu_port *port = 611 intel_vgpu_port(vgpu, vgpu->display.port_num); 612 613 if (turnon) { 614 /* 615 * Skip the re-enable if already active and vrefresh unchanged. 616 * Otherwise, stop timer if already active and restart with new 617 * period. 618 */ 619 if (vblank_timer->vrefresh_k != port->vrefresh_k || 620 !hrtimer_active(&vblank_timer->timer)) { 621 /* Stop timer before start with new period if active */ 622 if (hrtimer_active(&vblank_timer->timer)) 623 hrtimer_cancel(&vblank_timer->timer); 624 625 /* Make sure new refresh rate updated to timer period */ 626 vblank_timer->vrefresh_k = port->vrefresh_k; 627 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); 628 hrtimer_start(&vblank_timer->timer, 629 ktime_add_ns(ktime_get(), vblank_timer->period), 630 HRTIMER_MODE_ABS); 631 } 632 } else { 633 /* Caller request to stop vblank */ 634 hrtimer_cancel(&vblank_timer->timer); 635 } 636 } 637 638 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 639 { 640 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 641 struct intel_display *display = dev_priv->display; 642 struct intel_vgpu_irq *irq = &vgpu->irq; 643 int vblank_event[] = { 644 [PIPE_A] = PIPE_A_VBLANK, 645 [PIPE_B] = PIPE_B_VBLANK, 646 [PIPE_C] = PIPE_C_VBLANK, 647 }; 648 int event; 649 650 if (pipe < PIPE_A || pipe > PIPE_C) 651 return; 652 653 for_each_set_bit(event, irq->flip_done_event[pipe], 654 INTEL_GVT_EVENT_MAX) { 655 clear_bit(event, irq->flip_done_event[pipe]); 656 if (!pipe_is_enabled(vgpu, pipe)) 657 continue; 658 659 intel_vgpu_trigger_virtual_event(vgpu, event); 660 } 661 662 if (pipe_is_enabled(vgpu, pipe)) { 663 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(display, pipe))++; 664 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); 665 } 666 } 667 668 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) 669 { 670 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 671 struct intel_display *display = i915->display; 672 enum pipe pipe; 673 674 mutex_lock(&vgpu->vgpu_lock); 675 gvt_for_each_pipe(display, pipe) 676 emulate_vblank_on_pipe(vgpu, pipe); 677 mutex_unlock(&vgpu->vgpu_lock); 678 } 679 680 /** 681 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU 682 * @vgpu: a vGPU 683 * @connected: link state 684 * 685 * This function is used to trigger hotplug interrupt for vGPU 686 * 687 */ 688 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 689 { 690 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 691 692 /* TODO: add more platforms support */ 693 if (IS_SKYLAKE(i915) || 694 IS_KABYLAKE(i915) || 695 IS_COFFEELAKE(i915) || 696 IS_COMETLAKE(i915)) { 697 if (connected) { 698 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 699 SFUSE_STRAP_DDID_DETECTED; 700 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; 701 } else { 702 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 703 ~SFUSE_STRAP_DDID_DETECTED; 704 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; 705 } 706 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; 707 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 708 PORTD_HOTPLUG_STATUS_MASK; 709 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG); 710 } else if (IS_BROXTON(i915)) { 711 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { 712 if (connected) { 713 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 714 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 715 } else { 716 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 717 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 718 } 719 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 720 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); 721 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 722 ~PORTA_HOTPLUG_STATUS_MASK; 723 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 724 PORTA_HOTPLUG_LONG_DETECT; 725 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG); 726 } 727 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { 728 if (connected) { 729 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 730 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 731 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 732 SFUSE_STRAP_DDIB_DETECTED; 733 } else { 734 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 735 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 736 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 737 ~SFUSE_STRAP_DDIB_DETECTED; 738 } 739 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 740 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); 741 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 742 ~PORTB_HOTPLUG_STATUS_MASK; 743 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 744 PORTB_HOTPLUG_LONG_DETECT; 745 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG); 746 } 747 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { 748 if (connected) { 749 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= 750 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 751 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= 752 SFUSE_STRAP_DDIC_DETECTED; 753 } else { 754 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= 755 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 756 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= 757 ~SFUSE_STRAP_DDIC_DETECTED; 758 } 759 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= 760 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); 761 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= 762 ~PORTC_HOTPLUG_STATUS_MASK; 763 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= 764 PORTC_HOTPLUG_LONG_DETECT; 765 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG); 766 } 767 } 768 } 769 770 /** 771 * intel_vgpu_clean_display - clean vGPU virtual display emulation 772 * @vgpu: a vGPU 773 * 774 * This function is used to clean vGPU virtual display emulation stuffs 775 * 776 */ 777 void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 778 { 779 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 780 781 if (IS_SKYLAKE(dev_priv) || 782 IS_KABYLAKE(dev_priv) || 783 IS_COFFEELAKE(dev_priv) || 784 IS_COMETLAKE(dev_priv)) 785 clean_virtual_dp_monitor(vgpu, PORT_D); 786 else 787 clean_virtual_dp_monitor(vgpu, PORT_B); 788 789 vgpu_update_vblank_emulation(vgpu, false); 790 } 791 792 /** 793 * intel_vgpu_init_display- initialize vGPU virtual display emulation 794 * @vgpu: a vGPU 795 * @resolution: resolution index for intel_vgpu_edid 796 * 797 * This function is used to initialize vGPU virtual display emulation stuffs 798 * 799 * Returns: 800 * Zero on success, negative error code if failed. 801 * 802 */ 803 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 804 { 805 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 806 807 intel_vgpu_init_i2c_edid(vgpu); 808 809 if (IS_SKYLAKE(dev_priv) || 810 IS_KABYLAKE(dev_priv) || 811 IS_COFFEELAKE(dev_priv) || 812 IS_COMETLAKE(dev_priv)) 813 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, 814 resolution); 815 else 816 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B, 817 resolution); 818 } 819 820 /** 821 * intel_vgpu_reset_display- reset vGPU virtual display emulation 822 * @vgpu: a vGPU 823 * 824 * This function is used to reset vGPU virtual display emulation stuffs 825 * 826 */ 827 void intel_vgpu_reset_display(struct intel_vgpu *vgpu) 828 { 829 emulate_monitor_status_change(vgpu); 830 } 831