xref: /linux/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c (revision 97ef3b7f4fdf8ad6818aa2c8201c3b72cc635e16)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2016-2019 Intel Corporation
4  */
5 
6 #include <linux/bitfield.h>
7 #include <linux/firmware.h>
8 #include <drm/drm_print.h>
9 
10 #include "intel_uc_fw.h"
11 #include "intel_uc_fw_abi.h"
12 #include "i915_drv.h"
13 
14 static inline struct intel_gt *
15 ____uc_fw_to_gt(struct intel_uc_fw *uc_fw, enum intel_uc_fw_type type)
16 {
17 	if (type == INTEL_UC_FW_TYPE_GUC)
18 		return container_of(uc_fw, struct intel_gt, uc.guc.fw);
19 
20 	GEM_BUG_ON(type != INTEL_UC_FW_TYPE_HUC);
21 	return container_of(uc_fw, struct intel_gt, uc.huc.fw);
22 }
23 
24 static inline struct intel_gt *__uc_fw_to_gt(struct intel_uc_fw *uc_fw)
25 {
26 	GEM_BUG_ON(uc_fw->status == INTEL_UC_FIRMWARE_UNINITIALIZED);
27 	return ____uc_fw_to_gt(uc_fw, uc_fw->type);
28 }
29 
30 #ifdef CONFIG_DRM_I915_DEBUG_GUC
31 void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
32 			       enum intel_uc_fw_status status)
33 {
34 	uc_fw->__status =  status;
35 	drm_dbg(&__uc_fw_to_gt(uc_fw)->i915->drm,
36 		"%s firmware -> %s\n",
37 		intel_uc_fw_type_repr(uc_fw->type),
38 		status == INTEL_UC_FIRMWARE_SELECTED ?
39 		uc_fw->path : intel_uc_fw_status_repr(status));
40 }
41 #endif
42 
43 /*
44  * List of required GuC and HuC binaries per-platform.
45  * Must be ordered based on platform + revid, from newer to older.
46  *
47  * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
48  * firmware as TGL.
49  */
50 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
51 	fw_def(ALDERLAKE_P, 0, guc_def(adlp, 62, 0, 3), huc_def(tgl, 7, 9, 3)) \
52 	fw_def(ALDERLAKE_S, 0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 9, 3)) \
53 	fw_def(ROCKETLAKE,  0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 9, 3)) \
54 	fw_def(TIGERLAKE,   0, guc_def(tgl, 62, 0, 0), huc_def(tgl,  7, 9, 3)) \
55 	fw_def(JASPERLAKE,  0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
56 	fw_def(ELKHARTLAKE, 0, guc_def(ehl, 62, 0, 0), huc_def(ehl,  9, 0, 0)) \
57 	fw_def(ICELAKE,     0, guc_def(icl, 62, 0, 0), huc_def(icl,  9, 0, 0)) \
58 	fw_def(COMETLAKE,   5, guc_def(cml, 62, 0, 0), huc_def(cml,  4, 0, 0)) \
59 	fw_def(COMETLAKE,   0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
60 	fw_def(COFFEELAKE,  0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
61 	fw_def(GEMINILAKE,  0, guc_def(glk, 62, 0, 0), huc_def(glk,  4, 0, 0)) \
62 	fw_def(KABYLAKE,    0, guc_def(kbl, 62, 0, 0), huc_def(kbl,  4, 0, 0)) \
63 	fw_def(BROXTON,     0, guc_def(bxt, 62, 0, 0), huc_def(bxt,  2, 0, 0)) \
64 	fw_def(SKYLAKE,     0, guc_def(skl, 62, 0, 0), huc_def(skl,  2, 0, 0))
65 
66 #define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \
67 	"i915/" \
68 	__stringify(prefix_) name_ \
69 	__stringify(major_) "." \
70 	__stringify(minor_) "." \
71 	__stringify(patch_) ".bin"
72 
73 #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
74 	__MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_)
75 
76 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
77 	__MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_)
78 
79 /* All blobs need to be declared via MODULE_FIRMWARE() */
80 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
81 	MODULE_FIRMWARE(guc_); \
82 	MODULE_FIRMWARE(huc_);
83 
84 INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH)
85 
86 /* The below structs and macros are used to iterate across the list of blobs */
87 struct __packed uc_fw_blob {
88 	u8 major;
89 	u8 minor;
90 	const char *path;
91 };
92 
93 #define UC_FW_BLOB(major_, minor_, path_) \
94 	{ .major = major_, .minor = minor_, .path = path_ }
95 
96 #define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
97 	UC_FW_BLOB(major_, minor_, \
98 		   MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_))
99 
100 #define HUC_FW_BLOB(prefix_, major_, minor_, bld_num_) \
101 	UC_FW_BLOB(major_, minor_, \
102 		   MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_))
103 
104 struct __packed uc_fw_platform_requirement {
105 	enum intel_platform p;
106 	u8 rev; /* first platform rev using this FW */
107 	const struct uc_fw_blob blobs[INTEL_UC_FW_NUM_TYPES];
108 };
109 
110 #define MAKE_FW_LIST(platform_, revid_, guc_, huc_) \
111 { \
112 	.p = INTEL_##platform_, \
113 	.rev = revid_, \
114 	.blobs[INTEL_UC_FW_TYPE_GUC] = guc_, \
115 	.blobs[INTEL_UC_FW_TYPE_HUC] = huc_, \
116 },
117 
118 static void
119 __uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
120 {
121 	static const struct uc_fw_platform_requirement fw_blobs[] = {
122 		INTEL_UC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, HUC_FW_BLOB)
123 	};
124 	enum intel_platform p = INTEL_INFO(i915)->platform;
125 	u8 rev = INTEL_REVID(i915);
126 	int i;
127 
128 	for (i = 0; i < ARRAY_SIZE(fw_blobs) && p <= fw_blobs[i].p; i++) {
129 		if (p == fw_blobs[i].p && rev >= fw_blobs[i].rev) {
130 			const struct uc_fw_blob *blob =
131 					&fw_blobs[i].blobs[uc_fw->type];
132 			uc_fw->path = blob->path;
133 			uc_fw->major_ver_wanted = blob->major;
134 			uc_fw->minor_ver_wanted = blob->minor;
135 			break;
136 		}
137 	}
138 
139 	/* make sure the list is ordered as expected */
140 	if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST)) {
141 		for (i = 1; i < ARRAY_SIZE(fw_blobs); i++) {
142 			if (fw_blobs[i].p < fw_blobs[i - 1].p)
143 				continue;
144 
145 			if (fw_blobs[i].p == fw_blobs[i - 1].p &&
146 			    fw_blobs[i].rev < fw_blobs[i - 1].rev)
147 				continue;
148 
149 			pr_err("invalid FW blob order: %s r%u comes before %s r%u\n",
150 			       intel_platform_name(fw_blobs[i - 1].p),
151 			       fw_blobs[i - 1].rev,
152 			       intel_platform_name(fw_blobs[i].p),
153 			       fw_blobs[i].rev);
154 
155 			uc_fw->path = NULL;
156 		}
157 	}
158 }
159 
160 static const char *__override_guc_firmware_path(struct drm_i915_private *i915)
161 {
162 	if (i915->params.enable_guc & ENABLE_GUC_MASK)
163 		return i915->params.guc_firmware_path;
164 	return "";
165 }
166 
167 static const char *__override_huc_firmware_path(struct drm_i915_private *i915)
168 {
169 	if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC)
170 		return i915->params.huc_firmware_path;
171 	return "";
172 }
173 
174 static void __uc_fw_user_override(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw)
175 {
176 	const char *path = NULL;
177 
178 	switch (uc_fw->type) {
179 	case INTEL_UC_FW_TYPE_GUC:
180 		path = __override_guc_firmware_path(i915);
181 		break;
182 	case INTEL_UC_FW_TYPE_HUC:
183 		path = __override_huc_firmware_path(i915);
184 		break;
185 	}
186 
187 	if (unlikely(path)) {
188 		uc_fw->path = path;
189 		uc_fw->user_overridden = true;
190 	}
191 }
192 
193 /**
194  * intel_uc_fw_init_early - initialize the uC object and select the firmware
195  * @uc_fw: uC firmware
196  * @type: type of uC
197  *
198  * Initialize the state of our uC object and relevant tracking and select the
199  * firmware to fetch and load.
200  */
201 void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
202 			    enum intel_uc_fw_type type)
203 {
204 	struct drm_i915_private *i915 = ____uc_fw_to_gt(uc_fw, type)->i915;
205 
206 	/*
207 	 * we use FIRMWARE_UNINITIALIZED to detect checks against uc_fw->status
208 	 * before we're looked at the HW caps to see if we have uc support
209 	 */
210 	BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED);
211 	GEM_BUG_ON(uc_fw->status);
212 	GEM_BUG_ON(uc_fw->path);
213 
214 	uc_fw->type = type;
215 
216 	if (HAS_GT_UC(i915)) {
217 		__uc_fw_auto_select(i915, uc_fw);
218 		__uc_fw_user_override(i915, uc_fw);
219 	}
220 
221 	intel_uc_fw_change_status(uc_fw, uc_fw->path ? *uc_fw->path ?
222 				  INTEL_UC_FIRMWARE_SELECTED :
223 				  INTEL_UC_FIRMWARE_DISABLED :
224 				  INTEL_UC_FIRMWARE_NOT_SUPPORTED);
225 }
226 
227 static void __force_fw_fetch_failures(struct intel_uc_fw *uc_fw, int e)
228 {
229 	struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915;
230 	bool user = e == -EINVAL;
231 
232 	if (i915_inject_probe_error(i915, e)) {
233 		/* non-existing blob */
234 		uc_fw->path = "<invalid>";
235 		uc_fw->user_overridden = user;
236 	} else if (i915_inject_probe_error(i915, e)) {
237 		/* require next major version */
238 		uc_fw->major_ver_wanted += 1;
239 		uc_fw->minor_ver_wanted = 0;
240 		uc_fw->user_overridden = user;
241 	} else if (i915_inject_probe_error(i915, e)) {
242 		/* require next minor version */
243 		uc_fw->minor_ver_wanted += 1;
244 		uc_fw->user_overridden = user;
245 	} else if (uc_fw->major_ver_wanted &&
246 		   i915_inject_probe_error(i915, e)) {
247 		/* require prev major version */
248 		uc_fw->major_ver_wanted -= 1;
249 		uc_fw->minor_ver_wanted = 0;
250 		uc_fw->user_overridden = user;
251 	} else if (uc_fw->minor_ver_wanted &&
252 		   i915_inject_probe_error(i915, e)) {
253 		/* require prev minor version - hey, this should work! */
254 		uc_fw->minor_ver_wanted -= 1;
255 		uc_fw->user_overridden = user;
256 	} else if (user && i915_inject_probe_error(i915, e)) {
257 		/* officially unsupported platform */
258 		uc_fw->major_ver_wanted = 0;
259 		uc_fw->minor_ver_wanted = 0;
260 		uc_fw->user_overridden = true;
261 	}
262 }
263 
264 /**
265  * intel_uc_fw_fetch - fetch uC firmware
266  * @uc_fw: uC firmware
267  *
268  * Fetch uC firmware into GEM obj.
269  *
270  * Return: 0 on success, a negative errno code on failure.
271  */
272 int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
273 {
274 	struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915;
275 	struct device *dev = i915->drm.dev;
276 	struct drm_i915_gem_object *obj;
277 	const struct firmware *fw = NULL;
278 	struct uc_css_header *css;
279 	size_t size;
280 	int err;
281 
282 	GEM_BUG_ON(!i915->wopcm.size);
283 	GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw));
284 
285 	err = i915_inject_probe_error(i915, -ENXIO);
286 	if (err)
287 		goto fail;
288 
289 	__force_fw_fetch_failures(uc_fw, -EINVAL);
290 	__force_fw_fetch_failures(uc_fw, -ESTALE);
291 
292 	err = request_firmware(&fw, uc_fw->path, dev);
293 	if (err)
294 		goto fail;
295 
296 	/* Check the size of the blob before examining buffer contents */
297 	if (unlikely(fw->size < sizeof(struct uc_css_header))) {
298 		drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
299 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
300 			 fw->size, sizeof(struct uc_css_header));
301 		err = -ENODATA;
302 		goto fail;
303 	}
304 
305 	css = (struct uc_css_header *)fw->data;
306 
307 	/* Check integrity of size values inside CSS header */
308 	size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw -
309 		css->exponent_size_dw) * sizeof(u32);
310 	if (unlikely(size != sizeof(struct uc_css_header))) {
311 		drm_warn(&i915->drm,
312 			 "%s firmware %s: unexpected header size: %zu != %zu\n",
313 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
314 			 fw->size, sizeof(struct uc_css_header));
315 		err = -EPROTO;
316 		goto fail;
317 	}
318 
319 	/* uCode size must calculated from other sizes */
320 	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
321 
322 	/* now RSA */
323 	if (unlikely(css->key_size_dw != UOS_RSA_SCRATCH_COUNT)) {
324 		drm_warn(&i915->drm, "%s firmware %s: unexpected key size: %u != %u\n",
325 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
326 			 css->key_size_dw, UOS_RSA_SCRATCH_COUNT);
327 		err = -EPROTO;
328 		goto fail;
329 	}
330 	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
331 
332 	/* At least, it should have header, uCode and RSA. Size of all three. */
333 	size = sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->rsa_size;
334 	if (unlikely(fw->size < size)) {
335 		drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu < %zu\n",
336 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
337 			 fw->size, size);
338 		err = -ENOEXEC;
339 		goto fail;
340 	}
341 
342 	/* Sanity check whether this fw is not larger than whole WOPCM memory */
343 	size = __intel_uc_fw_get_upload_size(uc_fw);
344 	if (unlikely(size >= i915->wopcm.size)) {
345 		drm_warn(&i915->drm, "%s firmware %s: invalid size: %zu > %zu\n",
346 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
347 			 size, (size_t)i915->wopcm.size);
348 		err = -E2BIG;
349 		goto fail;
350 	}
351 
352 	/* Get version numbers from the CSS header */
353 	uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MAJOR,
354 					   css->sw_version);
355 	uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MINOR,
356 					   css->sw_version);
357 
358 	if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
359 	    uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
360 		drm_notice(&i915->drm, "%s firmware %s: unexpected version: %u.%u != %u.%u\n",
361 			   intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
362 			   uc_fw->major_ver_found, uc_fw->minor_ver_found,
363 			   uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
364 		if (!intel_uc_fw_is_overridden(uc_fw)) {
365 			err = -ENOEXEC;
366 			goto fail;
367 		}
368 	}
369 
370 	if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
371 		uc_fw->private_data_size = css->private_data_size;
372 
373 	obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
374 	if (IS_ERR(obj)) {
375 		err = PTR_ERR(obj);
376 		goto fail;
377 	}
378 
379 	uc_fw->obj = obj;
380 	uc_fw->size = fw->size;
381 	intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE);
382 
383 	release_firmware(fw);
384 	return 0;
385 
386 fail:
387 	intel_uc_fw_change_status(uc_fw, err == -ENOENT ?
388 				  INTEL_UC_FIRMWARE_MISSING :
389 				  INTEL_UC_FIRMWARE_ERROR);
390 
391 	drm_notice(&i915->drm, "%s firmware %s: fetch failed with error %d\n",
392 		   intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err);
393 	drm_info(&i915->drm, "%s firmware(s) can be downloaded from %s\n",
394 		 intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL);
395 
396 	release_firmware(fw);		/* OK even if fw is NULL */
397 	return err;
398 }
399 
400 static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw)
401 {
402 	struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt;
403 	struct drm_mm_node *node = &ggtt->uc_fw;
404 
405 	GEM_BUG_ON(!drm_mm_node_allocated(node));
406 	GEM_BUG_ON(upper_32_bits(node->start));
407 	GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
408 
409 	return lower_32_bits(node->start);
410 }
411 
412 static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw)
413 {
414 	struct drm_i915_gem_object *obj = uc_fw->obj;
415 	struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt;
416 	struct i915_vma dummy = {
417 		.node.start = uc_fw_ggtt_offset(uc_fw),
418 		.node.size = obj->base.size,
419 		.pages = obj->mm.pages,
420 		.vm = &ggtt->vm,
421 	};
422 
423 	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
424 	GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size);
425 
426 	/* uc_fw->obj cache domains were not controlled across suspend */
427 	drm_clflush_sg(dummy.pages);
428 
429 	ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, 0);
430 }
431 
432 static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)
433 {
434 	struct drm_i915_gem_object *obj = uc_fw->obj;
435 	struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt;
436 	u64 start = uc_fw_ggtt_offset(uc_fw);
437 
438 	ggtt->vm.clear_range(&ggtt->vm, start, obj->base.size);
439 }
440 
441 static int uc_fw_xfer(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
442 {
443 	struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
444 	struct intel_uncore *uncore = gt->uncore;
445 	u64 offset;
446 	int ret;
447 
448 	ret = i915_inject_probe_error(gt->i915, -ETIMEDOUT);
449 	if (ret)
450 		return ret;
451 
452 	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
453 
454 	/* Set the source address for the uCode */
455 	offset = uc_fw_ggtt_offset(uc_fw);
456 	GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000);
457 	intel_uncore_write_fw(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
458 	intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset));
459 
460 	/* Set the DMA destination */
461 	intel_uncore_write_fw(uncore, DMA_ADDR_1_LOW, dst_offset);
462 	intel_uncore_write_fw(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
463 
464 	/*
465 	 * Set the transfer size. The header plus uCode will be copied to WOPCM
466 	 * via DMA, excluding any other components
467 	 */
468 	intel_uncore_write_fw(uncore, DMA_COPY_SIZE,
469 			      sizeof(struct uc_css_header) + uc_fw->ucode_size);
470 
471 	/* Start the DMA */
472 	intel_uncore_write_fw(uncore, DMA_CTRL,
473 			      _MASKED_BIT_ENABLE(dma_flags | START_DMA));
474 
475 	/* Wait for DMA to finish */
476 	ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
477 	if (ret)
478 		drm_err(&gt->i915->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
479 			intel_uc_fw_type_repr(uc_fw->type),
480 			intel_uncore_read_fw(uncore, DMA_CTRL));
481 
482 	/* Disable the bits once DMA is over */
483 	intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
484 
485 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
486 
487 	return ret;
488 }
489 
490 /**
491  * intel_uc_fw_upload - load uC firmware using custom loader
492  * @uc_fw: uC firmware
493  * @dst_offset: destination offset
494  * @dma_flags: flags for flags for dma ctrl
495  *
496  * Loads uC firmware and updates internal flags.
497  *
498  * Return: 0 on success, non-zero on failure.
499  */
500 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags)
501 {
502 	struct intel_gt *gt = __uc_fw_to_gt(uc_fw);
503 	int err;
504 
505 	/* make sure the status was cleared the last time we reset the uc */
506 	GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw));
507 
508 	err = i915_inject_probe_error(gt->i915, -ENOEXEC);
509 	if (err)
510 		return err;
511 
512 	if (!intel_uc_fw_is_loadable(uc_fw))
513 		return -ENOEXEC;
514 
515 	/* Call custom loader */
516 	uc_fw_bind_ggtt(uc_fw);
517 	err = uc_fw_xfer(uc_fw, dst_offset, dma_flags);
518 	uc_fw_unbind_ggtt(uc_fw);
519 	if (err)
520 		goto fail;
521 
522 	intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_TRANSFERRED);
523 	return 0;
524 
525 fail:
526 	i915_probe_error(gt->i915, "Failed to load %s firmware %s (%d)\n",
527 			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path,
528 			 err);
529 	intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_FAIL);
530 	return err;
531 }
532 
533 int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
534 {
535 	int err;
536 
537 	/* this should happen before the load! */
538 	GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw));
539 
540 	if (!intel_uc_fw_is_available(uc_fw))
541 		return -ENOEXEC;
542 
543 	err = i915_gem_object_pin_pages_unlocked(uc_fw->obj);
544 	if (err) {
545 		DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n",
546 				 intel_uc_fw_type_repr(uc_fw->type), err);
547 		intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_FAIL);
548 	}
549 
550 	return err;
551 }
552 
553 void intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
554 {
555 	if (i915_gem_object_has_pinned_pages(uc_fw->obj))
556 		i915_gem_object_unpin_pages(uc_fw->obj);
557 
558 	intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE);
559 }
560 
561 /**
562  * intel_uc_fw_cleanup_fetch - cleanup uC firmware
563  * @uc_fw: uC firmware
564  *
565  * Cleans up uC firmware by releasing the firmware GEM obj.
566  */
567 void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw)
568 {
569 	if (!intel_uc_fw_is_available(uc_fw))
570 		return;
571 
572 	i915_gem_object_put(fetch_and_zero(&uc_fw->obj));
573 
574 	intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_SELECTED);
575 }
576 
577 /**
578  * intel_uc_fw_copy_rsa - copy fw RSA to buffer
579  *
580  * @uc_fw: uC firmware
581  * @dst: dst buffer
582  * @max_len: max number of bytes to copy
583  *
584  * Return: number of copied bytes.
585  */
586 size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len)
587 {
588 	struct sg_table *pages = uc_fw->obj->mm.pages;
589 	u32 size = min_t(u32, uc_fw->rsa_size, max_len);
590 	u32 offset = sizeof(struct uc_css_header) + uc_fw->ucode_size;
591 
592 	GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw));
593 
594 	return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset);
595 }
596 
597 /**
598  * intel_uc_fw_dump - dump information about uC firmware
599  * @uc_fw: uC firmware
600  * @p: the &drm_printer
601  *
602  * Pretty printer for uC firmware.
603  */
604 void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p)
605 {
606 	drm_printf(p, "%s firmware: %s\n",
607 		   intel_uc_fw_type_repr(uc_fw->type), uc_fw->path);
608 	drm_printf(p, "\tstatus: %s\n",
609 		   intel_uc_fw_status_repr(uc_fw->status));
610 	drm_printf(p, "\tversion: wanted %u.%u, found %u.%u\n",
611 		   uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted,
612 		   uc_fw->major_ver_found, uc_fw->minor_ver_found);
613 	drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size);
614 	drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size);
615 }
616