1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2016-2019 Intel Corporation 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/firmware.h> 8 #include <drm/drm_print.h> 9 10 #include "intel_uc_fw.h" 11 #include "intel_uc_fw_abi.h" 12 #include "i915_drv.h" 13 14 #ifdef CONFIG_DRM_I915_DEBUG_GUC 15 static inline struct intel_gt *__uc_fw_to_gt(struct intel_uc_fw *uc_fw) 16 { 17 GEM_BUG_ON(uc_fw->status == INTEL_UC_FIRMWARE_UNINITIALIZED); 18 if (uc_fw->type == INTEL_UC_FW_TYPE_GUC) 19 return container_of(uc_fw, struct intel_gt, uc.guc.fw); 20 21 GEM_BUG_ON(uc_fw->type != INTEL_UC_FW_TYPE_HUC); 22 return container_of(uc_fw, struct intel_gt, uc.huc.fw); 23 } 24 25 void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, 26 enum intel_uc_fw_status status) 27 { 28 uc_fw->__status = status; 29 DRM_DEV_DEBUG_DRIVER(__uc_fw_to_gt(uc_fw)->i915->drm.dev, 30 "%s firmware -> %s\n", 31 intel_uc_fw_type_repr(uc_fw->type), 32 status == INTEL_UC_FIRMWARE_SELECTED ? 33 uc_fw->path : intel_uc_fw_status_repr(status)); 34 } 35 #endif 36 37 /* 38 * List of required GuC and HuC binaries per-platform. 39 * Must be ordered based on platform + revid, from newer to older. 40 * 41 * TGL 35.2 is interface-compatible with 33.0 for previous Gens. The deltas 42 * between 33.0 and 35.2 are only related to new additions to support new Gen12 43 * features. 44 */ 45 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \ 46 fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 3)) \ 47 fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ 48 fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ 49 fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ 50 fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ 51 fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ 52 fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ 53 fw_def(BROXTON, 0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 2, 0, 0)) \ 54 fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 2, 0, 0)) 55 56 #define __MAKE_UC_FW_PATH(prefix_, name_, major_, minor_, patch_) \ 57 "i915/" \ 58 __stringify(prefix_) name_ \ 59 __stringify(major_) "." \ 60 __stringify(minor_) "." \ 61 __stringify(patch_) ".bin" 62 63 #define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \ 64 __MAKE_UC_FW_PATH(prefix_, "_guc_", major_, minor_, patch_) 65 66 #define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \ 67 __MAKE_UC_FW_PATH(prefix_, "_huc_", major_, minor_, bld_num_) 68 69 /* All blobs need to be declared via MODULE_FIRMWARE() */ 70 #define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \ 71 MODULE_FIRMWARE(guc_); \ 72 MODULE_FIRMWARE(huc_); 73 74 INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH) 75 76 /* The below structs and macros are used to iterate across the list of blobs */ 77 struct __packed uc_fw_blob { 78 u8 major; 79 u8 minor; 80 const char *path; 81 }; 82 83 #define UC_FW_BLOB(major_, minor_, path_) \ 84 { .major = major_, .minor = minor_, .path = path_ } 85 86 #define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \ 87 UC_FW_BLOB(major_, minor_, \ 88 MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_)) 89 90 #define HUC_FW_BLOB(prefix_, major_, minor_, bld_num_) \ 91 UC_FW_BLOB(major_, minor_, \ 92 MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_)) 93 94 struct __packed uc_fw_platform_requirement { 95 enum intel_platform p; 96 u8 rev; /* first platform rev using this FW */ 97 const struct uc_fw_blob blobs[INTEL_UC_FW_NUM_TYPES]; 98 }; 99 100 #define MAKE_FW_LIST(platform_, revid_, guc_, huc_) \ 101 { \ 102 .p = INTEL_##platform_, \ 103 .rev = revid_, \ 104 .blobs[INTEL_UC_FW_TYPE_GUC] = guc_, \ 105 .blobs[INTEL_UC_FW_TYPE_HUC] = huc_, \ 106 }, 107 108 static void 109 __uc_fw_auto_select(struct intel_uc_fw *uc_fw, enum intel_platform p, u8 rev) 110 { 111 static const struct uc_fw_platform_requirement fw_blobs[] = { 112 INTEL_UC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, HUC_FW_BLOB) 113 }; 114 int i; 115 116 for (i = 0; i < ARRAY_SIZE(fw_blobs) && p <= fw_blobs[i].p; i++) { 117 if (p == fw_blobs[i].p && rev >= fw_blobs[i].rev) { 118 const struct uc_fw_blob *blob = 119 &fw_blobs[i].blobs[uc_fw->type]; 120 uc_fw->path = blob->path; 121 uc_fw->major_ver_wanted = blob->major; 122 uc_fw->minor_ver_wanted = blob->minor; 123 break; 124 } 125 } 126 127 /* make sure the list is ordered as expected */ 128 if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST)) { 129 for (i = 1; i < ARRAY_SIZE(fw_blobs); i++) { 130 if (fw_blobs[i].p < fw_blobs[i - 1].p) 131 continue; 132 133 if (fw_blobs[i].p == fw_blobs[i - 1].p && 134 fw_blobs[i].rev < fw_blobs[i - 1].rev) 135 continue; 136 137 pr_err("invalid FW blob order: %s r%u comes before %s r%u\n", 138 intel_platform_name(fw_blobs[i - 1].p), 139 fw_blobs[i - 1].rev, 140 intel_platform_name(fw_blobs[i].p), 141 fw_blobs[i].rev); 142 143 uc_fw->path = NULL; 144 } 145 } 146 147 /* We don't want to enable GuC/HuC on pre-Gen11 by default */ 148 if (i915_modparams.enable_guc == -1 && p < INTEL_ICELAKE) 149 uc_fw->path = NULL; 150 } 151 152 static const char *__override_guc_firmware_path(void) 153 { 154 if (i915_modparams.enable_guc & (ENABLE_GUC_SUBMISSION | 155 ENABLE_GUC_LOAD_HUC)) 156 return i915_modparams.guc_firmware_path; 157 return ""; 158 } 159 160 static const char *__override_huc_firmware_path(void) 161 { 162 if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC) 163 return i915_modparams.huc_firmware_path; 164 return ""; 165 } 166 167 static void __uc_fw_user_override(struct intel_uc_fw *uc_fw) 168 { 169 const char *path = NULL; 170 171 switch (uc_fw->type) { 172 case INTEL_UC_FW_TYPE_GUC: 173 path = __override_guc_firmware_path(); 174 break; 175 case INTEL_UC_FW_TYPE_HUC: 176 path = __override_huc_firmware_path(); 177 break; 178 } 179 180 if (unlikely(path)) { 181 uc_fw->path = path; 182 uc_fw->user_overridden = true; 183 } 184 } 185 186 /** 187 * intel_uc_fw_init_early - initialize the uC object and select the firmware 188 * @uc_fw: uC firmware 189 * @type: type of uC 190 * @supported: is uC support possible 191 * @platform: platform identifier 192 * @rev: hardware revision 193 * 194 * Initialize the state of our uC object and relevant tracking and select the 195 * firmware to fetch and load. 196 */ 197 void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw, 198 enum intel_uc_fw_type type, bool supported, 199 enum intel_platform platform, u8 rev) 200 { 201 /* 202 * we use FIRMWARE_UNINITIALIZED to detect checks against uc_fw->status 203 * before we're looked at the HW caps to see if we have uc support 204 */ 205 BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED); 206 GEM_BUG_ON(uc_fw->status); 207 GEM_BUG_ON(uc_fw->path); 208 209 uc_fw->type = type; 210 211 if (supported) { 212 __uc_fw_auto_select(uc_fw, platform, rev); 213 __uc_fw_user_override(uc_fw); 214 } 215 216 intel_uc_fw_change_status(uc_fw, uc_fw->path ? *uc_fw->path ? 217 INTEL_UC_FIRMWARE_SELECTED : 218 INTEL_UC_FIRMWARE_DISABLED : 219 INTEL_UC_FIRMWARE_NOT_SUPPORTED); 220 } 221 222 static void __force_fw_fetch_failures(struct intel_uc_fw *uc_fw, 223 struct drm_i915_private *i915, 224 int e) 225 { 226 bool user = e == -EINVAL; 227 228 if (i915_inject_probe_error(i915, e)) { 229 /* non-existing blob */ 230 uc_fw->path = "<invalid>"; 231 uc_fw->user_overridden = user; 232 } else if (i915_inject_probe_error(i915, e)) { 233 /* require next major version */ 234 uc_fw->major_ver_wanted += 1; 235 uc_fw->minor_ver_wanted = 0; 236 uc_fw->user_overridden = user; 237 } else if (i915_inject_probe_error(i915, e)) { 238 /* require next minor version */ 239 uc_fw->minor_ver_wanted += 1; 240 uc_fw->user_overridden = user; 241 } else if (uc_fw->major_ver_wanted && 242 i915_inject_probe_error(i915, e)) { 243 /* require prev major version */ 244 uc_fw->major_ver_wanted -= 1; 245 uc_fw->minor_ver_wanted = 0; 246 uc_fw->user_overridden = user; 247 } else if (uc_fw->minor_ver_wanted && 248 i915_inject_probe_error(i915, e)) { 249 /* require prev minor version - hey, this should work! */ 250 uc_fw->minor_ver_wanted -= 1; 251 uc_fw->user_overridden = user; 252 } else if (user && i915_inject_probe_error(i915, e)) { 253 /* officially unsupported platform */ 254 uc_fw->major_ver_wanted = 0; 255 uc_fw->minor_ver_wanted = 0; 256 uc_fw->user_overridden = true; 257 } 258 } 259 260 /** 261 * intel_uc_fw_fetch - fetch uC firmware 262 * @uc_fw: uC firmware 263 * @i915: device private 264 * 265 * Fetch uC firmware into GEM obj. 266 * 267 * Return: 0 on success, a negative errno code on failure. 268 */ 269 int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915) 270 { 271 struct device *dev = i915->drm.dev; 272 struct drm_i915_gem_object *obj; 273 const struct firmware *fw = NULL; 274 struct uc_css_header *css; 275 size_t size; 276 int err; 277 278 GEM_BUG_ON(!i915->wopcm.size); 279 GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw)); 280 281 err = i915_inject_probe_error(i915, -ENXIO); 282 if (err) 283 return err; 284 285 __force_fw_fetch_failures(uc_fw, i915, -EINVAL); 286 __force_fw_fetch_failures(uc_fw, i915, -ESTALE); 287 288 err = request_firmware(&fw, uc_fw->path, dev); 289 if (err) 290 goto fail; 291 292 /* Check the size of the blob before examining buffer contents */ 293 if (unlikely(fw->size < sizeof(struct uc_css_header))) { 294 dev_warn(dev, "%s firmware %s: invalid size: %zu < %zu\n", 295 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 296 fw->size, sizeof(struct uc_css_header)); 297 err = -ENODATA; 298 goto fail; 299 } 300 301 css = (struct uc_css_header *)fw->data; 302 303 /* Check integrity of size values inside CSS header */ 304 size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw - 305 css->exponent_size_dw) * sizeof(u32); 306 if (unlikely(size != sizeof(struct uc_css_header))) { 307 dev_warn(dev, 308 "%s firmware %s: unexpected header size: %zu != %zu\n", 309 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 310 fw->size, sizeof(struct uc_css_header)); 311 err = -EPROTO; 312 goto fail; 313 } 314 315 /* uCode size must calculated from other sizes */ 316 uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); 317 318 /* now RSA */ 319 if (unlikely(css->key_size_dw != UOS_RSA_SCRATCH_COUNT)) { 320 dev_warn(dev, "%s firmware %s: unexpected key size: %u != %u\n", 321 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 322 css->key_size_dw, UOS_RSA_SCRATCH_COUNT); 323 err = -EPROTO; 324 goto fail; 325 } 326 uc_fw->rsa_size = css->key_size_dw * sizeof(u32); 327 328 /* At least, it should have header, uCode and RSA. Size of all three. */ 329 size = sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->rsa_size; 330 if (unlikely(fw->size < size)) { 331 dev_warn(dev, "%s firmware %s: invalid size: %zu < %zu\n", 332 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 333 fw->size, size); 334 err = -ENOEXEC; 335 goto fail; 336 } 337 338 /* Sanity check whether this fw is not larger than whole WOPCM memory */ 339 size = __intel_uc_fw_get_upload_size(uc_fw); 340 if (unlikely(size >= i915->wopcm.size)) { 341 dev_warn(dev, "%s firmware %s: invalid size: %zu > %zu\n", 342 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 343 size, (size_t)i915->wopcm.size); 344 err = -E2BIG; 345 goto fail; 346 } 347 348 /* Get version numbers from the CSS header */ 349 uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MAJOR, 350 css->sw_version); 351 uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_UC_MINOR, 352 css->sw_version); 353 354 if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || 355 uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { 356 dev_notice(dev, "%s firmware %s: unexpected version: %u.%u != %u.%u\n", 357 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 358 uc_fw->major_ver_found, uc_fw->minor_ver_found, 359 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); 360 if (!intel_uc_fw_is_overridden(uc_fw)) { 361 err = -ENOEXEC; 362 goto fail; 363 } 364 } 365 366 obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size); 367 if (IS_ERR(obj)) { 368 err = PTR_ERR(obj); 369 goto fail; 370 } 371 372 uc_fw->obj = obj; 373 uc_fw->size = fw->size; 374 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE); 375 376 release_firmware(fw); 377 return 0; 378 379 fail: 380 intel_uc_fw_change_status(uc_fw, err == -ENOENT ? 381 INTEL_UC_FIRMWARE_MISSING : 382 INTEL_UC_FIRMWARE_ERROR); 383 384 dev_notice(dev, "%s firmware %s: fetch failed with error %d\n", 385 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err); 386 dev_info(dev, "%s firmware(s) can be downloaded from %s\n", 387 intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL); 388 389 release_firmware(fw); /* OK even if fw is NULL */ 390 return err; 391 } 392 393 static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw, struct i915_ggtt *ggtt) 394 { 395 struct drm_mm_node *node = &ggtt->uc_fw; 396 397 GEM_BUG_ON(!drm_mm_node_allocated(node)); 398 GEM_BUG_ON(upper_32_bits(node->start)); 399 GEM_BUG_ON(upper_32_bits(node->start + node->size - 1)); 400 401 return lower_32_bits(node->start); 402 } 403 404 static void intel_uc_fw_ggtt_bind(struct intel_uc_fw *uc_fw, 405 struct intel_gt *gt) 406 { 407 struct drm_i915_gem_object *obj = uc_fw->obj; 408 struct i915_ggtt *ggtt = gt->ggtt; 409 struct i915_vma dummy = { 410 .node.start = uc_fw_ggtt_offset(uc_fw, ggtt), 411 .node.size = obj->base.size, 412 .pages = obj->mm.pages, 413 .vm = &ggtt->vm, 414 }; 415 416 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); 417 GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size); 418 419 /* uc_fw->obj cache domains were not controlled across suspend */ 420 drm_clflush_sg(dummy.pages); 421 422 ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, 0); 423 } 424 425 static void intel_uc_fw_ggtt_unbind(struct intel_uc_fw *uc_fw, 426 struct intel_gt *gt) 427 { 428 struct drm_i915_gem_object *obj = uc_fw->obj; 429 struct i915_ggtt *ggtt = gt->ggtt; 430 u64 start = uc_fw_ggtt_offset(uc_fw, ggtt); 431 432 ggtt->vm.clear_range(&ggtt->vm, start, obj->base.size); 433 } 434 435 static int uc_fw_xfer(struct intel_uc_fw *uc_fw, struct intel_gt *gt, 436 u32 wopcm_offset, u32 dma_flags) 437 { 438 struct intel_uncore *uncore = gt->uncore; 439 u64 offset; 440 int ret; 441 442 ret = i915_inject_probe_error(gt->i915, -ETIMEDOUT); 443 if (ret) 444 return ret; 445 446 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 447 448 /* Set the source address for the uCode */ 449 offset = uc_fw_ggtt_offset(uc_fw, gt->ggtt); 450 GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000); 451 intel_uncore_write_fw(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset)); 452 intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset)); 453 454 /* Set the DMA destination */ 455 intel_uncore_write_fw(uncore, DMA_ADDR_1_LOW, wopcm_offset); 456 intel_uncore_write_fw(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); 457 458 /* 459 * Set the transfer size. The header plus uCode will be copied to WOPCM 460 * via DMA, excluding any other components 461 */ 462 intel_uncore_write_fw(uncore, DMA_COPY_SIZE, 463 sizeof(struct uc_css_header) + uc_fw->ucode_size); 464 465 /* Start the DMA */ 466 intel_uncore_write_fw(uncore, DMA_CTRL, 467 _MASKED_BIT_ENABLE(dma_flags | START_DMA)); 468 469 /* Wait for DMA to finish */ 470 ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100); 471 if (ret) 472 dev_err(gt->i915->drm.dev, "DMA for %s fw failed, DMA_CTRL=%u\n", 473 intel_uc_fw_type_repr(uc_fw->type), 474 intel_uncore_read_fw(uncore, DMA_CTRL)); 475 476 /* Disable the bits once DMA is over */ 477 intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); 478 479 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 480 481 return ret; 482 } 483 484 /** 485 * intel_uc_fw_upload - load uC firmware using custom loader 486 * @uc_fw: uC firmware 487 * @gt: the intel_gt structure 488 * @wopcm_offset: destination offset in wopcm 489 * @dma_flags: flags for flags for dma ctrl 490 * 491 * Loads uC firmware and updates internal flags. 492 * 493 * Return: 0 on success, non-zero on failure. 494 */ 495 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, struct intel_gt *gt, 496 u32 wopcm_offset, u32 dma_flags) 497 { 498 int err; 499 500 /* make sure the status was cleared the last time we reset the uc */ 501 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)); 502 503 err = i915_inject_probe_error(gt->i915, -ENOEXEC); 504 if (err) 505 return err; 506 507 if (!intel_uc_fw_is_available(uc_fw)) 508 return -ENOEXEC; 509 510 /* Call custom loader */ 511 intel_uc_fw_ggtt_bind(uc_fw, gt); 512 err = uc_fw_xfer(uc_fw, gt, wopcm_offset, dma_flags); 513 intel_uc_fw_ggtt_unbind(uc_fw, gt); 514 if (err) 515 goto fail; 516 517 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_TRANSFERRED); 518 return 0; 519 520 fail: 521 i915_probe_error(gt->i915, "Failed to load %s firmware %s (%d)\n", 522 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, 523 err); 524 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_FAIL); 525 return err; 526 } 527 528 int intel_uc_fw_init(struct intel_uc_fw *uc_fw) 529 { 530 int err; 531 532 /* this should happen before the load! */ 533 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)); 534 535 if (!intel_uc_fw_is_available(uc_fw)) 536 return -ENOEXEC; 537 538 err = i915_gem_object_pin_pages(uc_fw->obj); 539 if (err) { 540 DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n", 541 intel_uc_fw_type_repr(uc_fw->type), err); 542 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_FAIL); 543 } 544 545 return err; 546 } 547 548 void intel_uc_fw_fini(struct intel_uc_fw *uc_fw) 549 { 550 if (!intel_uc_fw_is_available(uc_fw)) 551 return; 552 553 i915_gem_object_unpin_pages(uc_fw->obj); 554 } 555 556 /** 557 * intel_uc_fw_cleanup_fetch - cleanup uC firmware 558 * @uc_fw: uC firmware 559 * 560 * Cleans up uC firmware by releasing the firmware GEM obj. 561 */ 562 void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw) 563 { 564 if (!intel_uc_fw_is_available(uc_fw)) 565 return; 566 567 i915_gem_object_put(fetch_and_zero(&uc_fw->obj)); 568 569 intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_SELECTED); 570 } 571 572 /** 573 * intel_uc_fw_copy_rsa - copy fw RSA to buffer 574 * 575 * @uc_fw: uC firmware 576 * @dst: dst buffer 577 * @max_len: max number of bytes to copy 578 * 579 * Return: number of copied bytes. 580 */ 581 size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len) 582 { 583 struct sg_table *pages = uc_fw->obj->mm.pages; 584 u32 size = min_t(u32, uc_fw->rsa_size, max_len); 585 u32 offset = sizeof(struct uc_css_header) + uc_fw->ucode_size; 586 587 GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw)); 588 589 return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset); 590 } 591 592 /** 593 * intel_uc_fw_dump - dump information about uC firmware 594 * @uc_fw: uC firmware 595 * @p: the &drm_printer 596 * 597 * Pretty printer for uC firmware. 598 */ 599 void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p) 600 { 601 drm_printf(p, "%s firmware: %s\n", 602 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path); 603 drm_printf(p, "\tstatus: %s\n", 604 intel_uc_fw_status_repr(uc_fw->status)); 605 drm_printf(p, "\tversion: wanted %u.%u, found %u.%u\n", 606 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted, 607 uc_fw->major_ver_found, uc_fw->minor_ver_found); 608 drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size); 609 drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size); 610 } 611