1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 * 5 * Authors: 6 * Vinit Azad <vinit.azad@intel.com> 7 * Ben Widawsky <ben@bwidawsk.net> 8 * Dave Gordon <david.s.gordon@intel.com> 9 * Alex Dai <yu.dai@intel.com> 10 */ 11 12 #include "gt/intel_gt.h" 13 #include "intel_guc_fw.h" 14 #include "i915_drv.h" 15 16 static void guc_prepare_xfer(struct intel_uncore *uncore) 17 { 18 u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES | 19 GUC_ENABLE_READ_CACHE_LOGIC | 20 GUC_ENABLE_MIA_CACHING | 21 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 22 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 23 GUC_ENABLE_MIA_CLOCK_GATING; 24 25 /* Must program this register before loading the ucode with DMA */ 26 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags); 27 28 if (IS_GEN9_LP(uncore->i915)) 29 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); 30 else 31 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); 32 33 if (GRAPHICS_VER(uncore->i915) == 9) { 34 /* DOP Clock Gating Enable for GuC clocks */ 35 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 36 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE); 37 38 /* allows for 5us (in 10ns units) before GT can go to RC6 */ 39 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF); 40 } 41 } 42 43 /* Copy RSA signature from the fw image to HW for verification */ 44 static void guc_xfer_rsa(struct intel_uc_fw *guc_fw, 45 struct intel_uncore *uncore) 46 { 47 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 48 size_t copied; 49 int i; 50 51 copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa)); 52 GEM_BUG_ON(copied < sizeof(rsa)); 53 54 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 55 intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]); 56 } 57 58 /* 59 * Read the GuC status register (GUC_STATUS) and store it in the 60 * specified location; then return a boolean indicating whether 61 * the value matches either of two values representing completion 62 * of the GuC boot process. 63 * 64 * This is used for polling the GuC status in a wait_for() 65 * loop below. 66 */ 67 static inline bool guc_ready(struct intel_uncore *uncore, u32 *status) 68 { 69 u32 val = intel_uncore_read(uncore, GUC_STATUS); 70 u32 uk_val = val & GS_UKERNEL_MASK; 71 72 *status = val; 73 return (uk_val == GS_UKERNEL_READY) || 74 ((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE)); 75 } 76 77 static int guc_wait_ucode(struct intel_uncore *uncore) 78 { 79 u32 status; 80 int ret; 81 82 /* 83 * Wait for the GuC to start up. 84 * NB: Docs recommend not using the interrupt for completion. 85 * Measurements indicate this should take no more than 20ms, so a 86 * timeout here indicates that the GuC has failed and is unusable. 87 * (Higher levels of the driver may decide to reset the GuC and 88 * attempt the ucode load again if this happens.) 89 */ 90 ret = wait_for(guc_ready(uncore, &status), 100); 91 if (ret) { 92 struct drm_device *drm = &uncore->i915->drm; 93 94 drm_dbg(drm, "GuC load failed: status = 0x%08X\n", status); 95 drm_dbg(drm, "GuC load failed: status: Reset = %d, " 96 "BootROM = 0x%02X, UKernel = 0x%02X, " 97 "MIA = 0x%02X, Auth = 0x%02X\n", 98 REG_FIELD_GET(GS_MIA_IN_RESET, status), 99 REG_FIELD_GET(GS_BOOTROM_MASK, status), 100 REG_FIELD_GET(GS_UKERNEL_MASK, status), 101 REG_FIELD_GET(GS_MIA_MASK, status), 102 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 103 104 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { 105 drm_dbg(drm, "GuC firmware signature verification failed\n"); 106 ret = -ENOEXEC; 107 } 108 109 if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) { 110 drm_dbg(drm, "GuC firmware exception. EIP: %#x\n", 111 intel_uncore_read(uncore, SOFT_SCRATCH(13))); 112 ret = -ENXIO; 113 } 114 } 115 116 return ret; 117 } 118 119 /** 120 * intel_guc_fw_upload() - load GuC uCode to device 121 * @guc: intel_guc structure 122 * 123 * Called from intel_uc_init_hw() during driver load, resume from sleep and 124 * after a GPU reset. 125 * 126 * The firmware image should have already been fetched into memory, so only 127 * check that fetch succeeded, and then transfer the image to the h/w. 128 * 129 * Return: non-zero code on error 130 */ 131 int intel_guc_fw_upload(struct intel_guc *guc) 132 { 133 struct intel_gt *gt = guc_to_gt(guc); 134 struct intel_uncore *uncore = gt->uncore; 135 int ret; 136 137 guc_prepare_xfer(uncore); 138 139 /* 140 * Note that GuC needs the CSS header plus uKernel code to be copied 141 * by the DMA engine in one operation, whereas the RSA signature is 142 * loaded via MMIO. 143 */ 144 guc_xfer_rsa(&guc->fw, uncore); 145 146 /* 147 * Current uCode expects the code to be loaded at 8k; locations below 148 * this are used for the stack. 149 */ 150 ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 151 if (ret) 152 goto out; 153 154 ret = guc_wait_ucode(uncore); 155 if (ret) 156 goto out; 157 158 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING); 159 return 0; 160 161 out: 162 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL); 163 return ret; 164 } 165