1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_H_ 7 #define _INTEL_GUC_H_ 8 9 #include <linux/delay.h> 10 #include <linux/iosys-map.h> 11 #include <linux/xarray.h> 12 13 #include "intel_guc_ct.h" 14 #include "intel_guc_fw.h" 15 #include "intel_guc_fwif.h" 16 #include "intel_guc_log.h" 17 #include "intel_guc_reg.h" 18 #include "intel_guc_slpc_types.h" 19 #include "intel_uc_fw.h" 20 #include "intel_uncore.h" 21 #include "i915_utils.h" 22 #include "i915_vma.h" 23 24 struct __guc_ads_blob; 25 struct intel_guc_state_capture; 26 27 /** 28 * struct intel_guc - Top level structure of GuC. 29 * 30 * It handles firmware loading and manages client pool. intel_guc owns an 31 * i915_sched_engine for submission. 32 */ 33 struct intel_guc { 34 /** @fw: the GuC firmware */ 35 struct intel_uc_fw fw; 36 /** @log: sub-structure containing GuC log related data and objects */ 37 struct intel_guc_log log; 38 /** @ct: the command transport communication channel */ 39 struct intel_guc_ct ct; 40 /** @slpc: sub-structure containing SLPC related data and objects */ 41 struct intel_guc_slpc slpc; 42 /** @capture: the error-state-capture module's data and objects */ 43 struct intel_guc_state_capture *capture; 44 45 /** @sched_engine: Global engine used to submit requests to GuC */ 46 struct i915_sched_engine *sched_engine; 47 /** 48 * @stalled_request: if GuC can't process a request for any reason, we 49 * save it until GuC restarts processing. No other request can be 50 * submitted until the stalled request is processed. 51 */ 52 struct i915_request *stalled_request; 53 /** 54 * @submission_stall_reason: reason why submission is stalled 55 */ 56 enum { 57 STALL_NONE, 58 STALL_REGISTER_CONTEXT, 59 STALL_MOVE_LRC_TAIL, 60 STALL_ADD_REQUEST, 61 } submission_stall_reason; 62 63 /* intel_guc_recv interrupt related state */ 64 /** @irq_lock: protects GuC irq state */ 65 spinlock_t irq_lock; 66 /** 67 * @msg_enabled_mask: mask of events that are processed when receiving 68 * an INTEL_GUC_ACTION_DEFAULT G2H message. 69 */ 70 unsigned int msg_enabled_mask; 71 72 /** 73 * @outstanding_submission_g2h: number of outstanding GuC to Host 74 * responses related to GuC submission, used to determine if the GT is 75 * idle 76 */ 77 atomic_t outstanding_submission_g2h; 78 79 /** @interrupts: pointers to GuC interrupt-managing functions. */ 80 struct { 81 bool enabled; 82 void (*reset)(struct intel_guc *guc); 83 void (*enable)(struct intel_guc *guc); 84 void (*disable)(struct intel_guc *guc); 85 } interrupts; 86 87 /** 88 * @submission_state: sub-structure for submission state protected by 89 * single lock 90 */ 91 struct { 92 /** 93 * @lock: protects everything in submission_state, 94 * ce->guc_id.id, and ce->guc_id.ref when transitioning in and 95 * out of zero 96 */ 97 spinlock_t lock; 98 /** 99 * @guc_ids: used to allocate new guc_ids, single-lrc 100 */ 101 struct ida guc_ids; 102 /** 103 * @num_guc_ids: Number of guc_ids, selftest feature to be able 104 * to reduce this number while testing. 105 */ 106 int num_guc_ids; 107 /** 108 * @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc 109 */ 110 unsigned long *guc_ids_bitmap; 111 /** 112 * @guc_id_list: list of intel_context with valid guc_ids but no 113 * refs 114 */ 115 struct list_head guc_id_list; 116 /** 117 * @guc_ids_in_use: Number single-lrc guc_ids in use 118 */ 119 unsigned int guc_ids_in_use; 120 /** 121 * @destroyed_contexts: list of contexts waiting to be destroyed 122 * (deregistered with the GuC) 123 */ 124 struct list_head destroyed_contexts; 125 /** 126 * @destroyed_worker: worker to deregister contexts, need as we 127 * need to take a GT PM reference and can't from destroy 128 * function as it might be in an atomic context (no sleeping) 129 */ 130 struct work_struct destroyed_worker; 131 /** 132 * @reset_fail_worker: worker to trigger a GT reset after an 133 * engine reset fails 134 */ 135 struct work_struct reset_fail_worker; 136 /** 137 * @reset_fail_mask: mask of engines that failed to reset 138 */ 139 intel_engine_mask_t reset_fail_mask; 140 /** 141 * @sched_disable_delay_ms: schedule disable delay, in ms, for 142 * contexts 143 */ 144 unsigned int sched_disable_delay_ms; 145 /** 146 * @sched_disable_gucid_threshold: threshold of min remaining available 147 * guc_ids before we start bypassing the schedule disable delay 148 */ 149 unsigned int sched_disable_gucid_threshold; 150 } submission_state; 151 152 /** 153 * @submission_supported: tracks whether we support GuC submission on 154 * the current platform 155 */ 156 bool submission_supported; 157 /** @submission_selected: tracks whether the user enabled GuC submission */ 158 bool submission_selected; 159 /** @submission_initialized: tracks whether GuC submission has been initialised */ 160 bool submission_initialized; 161 /** 162 * @rc_supported: tracks whether we support GuC rc on the current platform 163 */ 164 bool rc_supported; 165 /** @rc_selected: tracks whether the user enabled GuC rc */ 166 bool rc_selected; 167 168 /** @ads_vma: object allocated to hold the GuC ADS */ 169 struct i915_vma *ads_vma; 170 /** @ads_map: contents of the GuC ADS */ 171 struct iosys_map ads_map; 172 /** @ads_regset_size: size of the save/restore regsets in the ADS */ 173 u32 ads_regset_size; 174 /** 175 * @ads_regset_count: number of save/restore registers in the ADS for 176 * each engine 177 */ 178 u32 ads_regset_count[I915_NUM_ENGINES]; 179 /** @ads_regset: save/restore regsets in the ADS */ 180 struct guc_mmio_reg *ads_regset; 181 /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */ 182 u32 ads_golden_ctxt_size; 183 /** @ads_capture_size: size of register lists in the ADS used for error capture */ 184 u32 ads_capture_size; 185 /** @ads_engine_usage_size: size of engine usage in the ADS */ 186 u32 ads_engine_usage_size; 187 188 /** @lrc_desc_pool_v69: object allocated to hold the GuC LRC descriptor pool */ 189 struct i915_vma *lrc_desc_pool_v69; 190 /** @lrc_desc_pool_vaddr_v69: contents of the GuC LRC descriptor pool */ 191 void *lrc_desc_pool_vaddr_v69; 192 193 /** 194 * @context_lookup: used to resolve intel_context from guc_id, if a 195 * context is present in this structure it is registered with the GuC 196 */ 197 struct xarray context_lookup; 198 199 /** @params: Control params for fw initialization */ 200 u32 params[GUC_CTL_MAX_DWORDS]; 201 202 /** @send_regs: GuC's FW specific registers used for sending MMIO H2G */ 203 struct { 204 u32 base; 205 unsigned int count; 206 enum forcewake_domains fw_domains; 207 } send_regs; 208 209 /** @notify_reg: register used to send interrupts to the GuC FW */ 210 i915_reg_t notify_reg; 211 212 /** 213 * @mmio_msg: notification bitmask that the GuC writes in one of its 214 * registers when the CT channel is disabled, to be processed when the 215 * channel is back up. 216 */ 217 u32 mmio_msg; 218 219 /** @send_mutex: used to serialize the intel_guc_send actions */ 220 struct mutex send_mutex; 221 222 /** 223 * @timestamp: GT timestamp object that stores a copy of the timestamp 224 * and adjusts it for overflow using a worker. 225 */ 226 struct { 227 /** 228 * @lock: Lock protecting the below fields and the engine stats. 229 */ 230 spinlock_t lock; 231 232 /** 233 * @gt_stamp: 64 bit extended value of the GT timestamp. 234 */ 235 u64 gt_stamp; 236 237 /** 238 * @ping_delay: Period for polling the GT timestamp for 239 * overflow. 240 */ 241 unsigned long ping_delay; 242 243 /** 244 * @work: Periodic work to adjust GT timestamp, engine and 245 * context usage for overflows. 246 */ 247 struct delayed_work work; 248 249 /** 250 * @shift: Right shift value for the gpm timestamp 251 */ 252 u32 shift; 253 254 /** 255 * @last_stat_jiffies: jiffies at last actual stats collection time 256 * We use this timestamp to ensure we don't oversample the 257 * stats because runtime power management events can trigger 258 * stats collection at much higher rates than required. 259 */ 260 unsigned long last_stat_jiffies; 261 } timestamp; 262 263 #ifdef CONFIG_DRM_I915_SELFTEST 264 /** 265 * @number_guc_id_stolen: The number of guc_ids that have been stolen 266 */ 267 int number_guc_id_stolen; 268 #endif 269 }; 270 271 static inline struct intel_guc *log_to_guc(struct intel_guc_log *log) 272 { 273 return container_of(log, struct intel_guc, log); 274 } 275 276 static 277 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) 278 { 279 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 0); 280 } 281 282 static 283 inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len, 284 u32 g2h_len_dw) 285 { 286 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 287 MAKE_SEND_FLAGS(g2h_len_dw)); 288 } 289 290 static inline int 291 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, 292 u32 *response_buf, u32 response_buf_size) 293 { 294 return intel_guc_ct_send(&guc->ct, action, len, 295 response_buf, response_buf_size, 0); 296 } 297 298 static inline int intel_guc_send_busy_loop(struct intel_guc *guc, 299 const u32 *action, 300 u32 len, 301 u32 g2h_len_dw, 302 bool loop) 303 { 304 int err; 305 unsigned int sleep_period_ms = 1; 306 bool not_atomic = !in_atomic() && !irqs_disabled(); 307 308 /* 309 * FIXME: Have caller pass in if we are in an atomic context to avoid 310 * using in_atomic(). It is likely safe here as we check for irqs 311 * disabled which basically all the spin locks in the i915 do but 312 * regardless this should be cleaned up. 313 */ 314 315 /* No sleeping with spin locks, just busy loop */ 316 might_sleep_if(loop && not_atomic); 317 318 retry: 319 err = intel_guc_send_nb(guc, action, len, g2h_len_dw); 320 if (unlikely(err == -EBUSY && loop)) { 321 if (likely(not_atomic)) { 322 if (msleep_interruptible(sleep_period_ms)) 323 return -EINTR; 324 sleep_period_ms = sleep_period_ms << 1; 325 } else { 326 cpu_relax(); 327 } 328 goto retry; 329 } 330 331 return err; 332 } 333 334 /* Only call this from the interrupt handler code */ 335 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) 336 { 337 if (guc->interrupts.enabled) 338 intel_guc_ct_event_handler(&guc->ct); 339 } 340 341 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ 342 #define GUC_GGTT_TOP 0xFEE00000 343 344 /** 345 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma 346 * @guc: intel_guc structure. 347 * @vma: i915 graphics virtual memory area. 348 * 349 * GuC does not allow any gfx GGTT address that falls into range 350 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. 351 * Currently, in order to exclude [0, ggtt.pin_bias) address space from 352 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() 353 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. 354 * 355 * Return: GGTT offset of the @vma. 356 */ 357 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, 358 struct i915_vma *vma) 359 { 360 u32 offset = i915_ggtt_offset(vma); 361 362 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma)); 363 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); 364 365 return offset; 366 } 367 368 void intel_guc_init_early(struct intel_guc *guc); 369 void intel_guc_init_late(struct intel_guc *guc); 370 void intel_guc_init_send_regs(struct intel_guc *guc); 371 void intel_guc_write_params(struct intel_guc *guc); 372 int intel_guc_init(struct intel_guc *guc); 373 void intel_guc_fini(struct intel_guc *guc); 374 void intel_guc_notify(struct intel_guc *guc); 375 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 376 u32 *response_buf, u32 response_buf_size); 377 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 378 const u32 *payload, u32 len); 379 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); 380 int intel_guc_suspend(struct intel_guc *guc); 381 int intel_guc_resume(struct intel_guc *guc); 382 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); 383 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size, 384 struct i915_vma **out_vma, void **out_vaddr); 385 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value); 386 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value); 387 388 static inline bool intel_guc_is_supported(struct intel_guc *guc) 389 { 390 return intel_uc_fw_is_supported(&guc->fw); 391 } 392 393 static inline bool intel_guc_is_wanted(struct intel_guc *guc) 394 { 395 return intel_uc_fw_is_enabled(&guc->fw); 396 } 397 398 static inline bool intel_guc_is_used(struct intel_guc *guc) 399 { 400 GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED); 401 return intel_uc_fw_is_available(&guc->fw); 402 } 403 404 static inline bool intel_guc_is_fw_running(struct intel_guc *guc) 405 { 406 return intel_uc_fw_is_running(&guc->fw); 407 } 408 409 static inline bool intel_guc_is_ready(struct intel_guc *guc) 410 { 411 return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(&guc->ct); 412 } 413 414 static inline void intel_guc_reset_interrupts(struct intel_guc *guc) 415 { 416 guc->interrupts.reset(guc); 417 } 418 419 static inline void intel_guc_enable_interrupts(struct intel_guc *guc) 420 { 421 guc->interrupts.enable(guc); 422 } 423 424 static inline void intel_guc_disable_interrupts(struct intel_guc *guc) 425 { 426 guc->interrupts.disable(guc); 427 } 428 429 static inline int intel_guc_sanitize(struct intel_guc *guc) 430 { 431 intel_uc_fw_sanitize(&guc->fw); 432 intel_guc_disable_interrupts(guc); 433 intel_guc_ct_sanitize(&guc->ct); 434 guc->mmio_msg = 0; 435 436 return 0; 437 } 438 439 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) 440 { 441 spin_lock_irq(&guc->irq_lock); 442 guc->msg_enabled_mask |= mask; 443 spin_unlock_irq(&guc->irq_lock); 444 } 445 446 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) 447 { 448 spin_lock_irq(&guc->irq_lock); 449 guc->msg_enabled_mask &= ~mask; 450 spin_unlock_irq(&guc->irq_lock); 451 } 452 453 int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout); 454 455 int intel_guc_deregister_done_process_msg(struct intel_guc *guc, 456 const u32 *msg, u32 len); 457 int intel_guc_sched_done_process_msg(struct intel_guc *guc, 458 const u32 *msg, u32 len); 459 int intel_guc_context_reset_process_msg(struct intel_guc *guc, 460 const u32 *msg, u32 len); 461 int intel_guc_engine_failure_process_msg(struct intel_guc *guc, 462 const u32 *msg, u32 len); 463 int intel_guc_error_capture_process_msg(struct intel_guc *guc, 464 const u32 *msg, u32 len); 465 466 struct intel_engine_cs * 467 intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance); 468 469 void intel_guc_find_hung_context(struct intel_engine_cs *engine); 470 471 int intel_guc_global_policies_update(struct intel_guc *guc); 472 473 void intel_guc_context_ban(struct intel_context *ce, struct i915_request *rq); 474 475 void intel_guc_submission_reset_prepare(struct intel_guc *guc); 476 void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled); 477 void intel_guc_submission_reset_finish(struct intel_guc *guc); 478 void intel_guc_submission_cancel_requests(struct intel_guc *guc); 479 480 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p); 481 482 void intel_guc_write_barrier(struct intel_guc *guc); 483 484 void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p); 485 486 int intel_guc_sched_disable_gucid_threshold_max(struct intel_guc *guc); 487 488 #endif 489