1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gpu_commands.h" 12 #include "intel_gt.h" 13 #include "intel_gt_ccs_mode.h" 14 #include "intel_gt_mcr.h" 15 #include "intel_gt_print.h" 16 #include "intel_gt_regs.h" 17 #include "intel_ring.h" 18 #include "intel_workarounds.h" 19 20 /** 21 * DOC: Hardware workarounds 22 * 23 * Hardware workarounds are register programming documented to be executed in 24 * the driver that fall outside of the normal programming sequences for a 25 * platform. There are some basic categories of workarounds, depending on 26 * how/when they are applied: 27 * 28 * - Context workarounds: workarounds that touch registers that are 29 * saved/restored to/from the HW context image. The list is emitted (via Load 30 * Register Immediate commands) once when initializing the device and saved in 31 * the default context. That default context is then used on every context 32 * creation to have a "primed golden context", i.e. a context image that 33 * already contains the changes needed to all the registers. 34 * 35 * Context workarounds should be implemented in the \*_ctx_workarounds_init() 36 * variants respective to the targeted platforms. 37 * 38 * - Engine workarounds: the list of these WAs is applied whenever the specific 39 * engine is reset. It's also possible that a set of engine classes share a 40 * common power domain and they are reset together. This happens on some 41 * platforms with render and compute engines. In this case (at least) one of 42 * them need to keeep the workaround programming: the approach taken in the 43 * driver is to tie those workarounds to the first compute/render engine that 44 * is registered. When executing with GuC submission, engine resets are 45 * outside of kernel driver control, hence the list of registers involved in 46 * written once, on engine initialization, and then passed to GuC, that 47 * saves/restores their values before/after the reset takes place. See 48 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 49 * 50 * Workarounds for registers specific to RCS and CCS should be implemented in 51 * rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for 52 * registers belonging to BCS, VCS or VECS should be implemented in 53 * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific 54 * engine's MMIO range but that are part of of the common RCS/CCS reset domain 55 * should be implemented in general_render_compute_wa_init(). The settings 56 * about the CCS load balancing should be added in ccs_engine_wa_mode(). 57 * 58 * - GT workarounds: the list of these WAs is applied whenever these registers 59 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 60 * 61 * GT workarounds should be implemented in the \*_gt_workarounds_init() 62 * variants respective to the targeted platforms. 63 * 64 * - Register whitelist: some workarounds need to be implemented in userspace, 65 * but need to touch privileged registers. The whitelist in the kernel 66 * instructs the hardware to allow the access to happen. From the kernel side, 67 * this is just a special case of a MMIO workaround (as we write the list of 68 * these to/be-whitelisted registers to some special HW registers). 69 * 70 * Register whitelisting should be done in the \*_whitelist_build() variants 71 * respective to the targeted platforms. 72 * 73 * - Workaround batchbuffers: buffers that get executed automatically by the 74 * hardware on every HW context restore. These buffers are created and 75 * programmed in the default context so the hardware always go through those 76 * programming sequences when switching contexts. The support for workaround 77 * batchbuffers is enabled these hardware mechanisms: 78 * 79 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 80 * context, pointing the hardware to jump to that location when that offset 81 * is reached in the context restore. Workaround batchbuffer in the driver 82 * currently uses this mechanism for all platforms. 83 * 84 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 85 * pointing the hardware to a buffer to continue executing after the 86 * engine registers are restored in a context restore sequence. This is 87 * currently not used in the driver. 88 * 89 * - Other: There are WAs that, due to their nature, cannot be applied from a 90 * central place. Those are peppered around the rest of the code, as needed. 91 * Workarounds related to the display IP are the main example. 92 * 93 * .. [1] Technically, some registers are powercontext saved & restored, so they 94 * survive a suspend/resume. In practice, writing them again is not too 95 * costly and simplifies things, so it's the approach taken in the driver. 96 */ 97 98 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 99 const char *name, const char *engine_name) 100 { 101 wal->gt = gt; 102 wal->name = name; 103 wal->engine_name = engine_name; 104 } 105 106 #define WA_LIST_CHUNK (1 << 4) 107 108 static void wa_init_finish(struct i915_wa_list *wal) 109 { 110 /* Trim unused entries. */ 111 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 112 struct i915_wa *list = kmemdup(wal->list, 113 wal->count * sizeof(*list), 114 GFP_KERNEL); 115 116 if (list) { 117 kfree(wal->list); 118 wal->list = list; 119 } 120 } 121 122 if (!wal->count) 123 return; 124 125 gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n", 126 wal->wa_count, wal->name, wal->engine_name); 127 } 128 129 static enum forcewake_domains 130 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 131 { 132 enum forcewake_domains fw = 0; 133 struct i915_wa *wa; 134 unsigned int i; 135 136 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 137 fw |= intel_uncore_forcewake_for_reg(uncore, 138 wa->reg, 139 FW_REG_READ | 140 FW_REG_WRITE); 141 142 return fw; 143 } 144 145 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 146 { 147 unsigned int addr = i915_mmio_reg_offset(wa->reg); 148 struct drm_i915_private *i915 = wal->gt->i915; 149 unsigned int start = 0, end = wal->count; 150 const unsigned int grow = WA_LIST_CHUNK; 151 struct i915_wa *wa_; 152 153 GEM_BUG_ON(!is_power_of_2(grow)); 154 155 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 156 struct i915_wa *list; 157 158 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 159 GFP_KERNEL); 160 if (!list) { 161 drm_err(&i915->drm, "No space for workaround init!\n"); 162 return; 163 } 164 165 if (wal->list) { 166 memcpy(list, wal->list, sizeof(*wa) * wal->count); 167 kfree(wal->list); 168 } 169 170 wal->list = list; 171 } 172 173 while (start < end) { 174 unsigned int mid = start + (end - start) / 2; 175 176 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 177 start = mid + 1; 178 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 179 end = mid; 180 } else { 181 wa_ = &wal->list[mid]; 182 183 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 184 drm_err(&i915->drm, 185 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 186 i915_mmio_reg_offset(wa_->reg), 187 wa_->clr, wa_->set); 188 189 wa_->set &= ~wa->clr; 190 } 191 192 wal->wa_count++; 193 wa_->set |= wa->set; 194 wa_->clr |= wa->clr; 195 wa_->read |= wa->read; 196 return; 197 } 198 } 199 200 wal->wa_count++; 201 wa_ = &wal->list[wal->count++]; 202 *wa_ = *wa; 203 204 while (wa_-- > wal->list) { 205 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 206 i915_mmio_reg_offset(wa_[1].reg)); 207 if (i915_mmio_reg_offset(wa_[1].reg) > 208 i915_mmio_reg_offset(wa_[0].reg)) 209 break; 210 211 swap(wa_[1], wa_[0]); 212 } 213 } 214 215 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 216 u32 clear, u32 set, u32 read_mask, bool masked_reg) 217 { 218 struct i915_wa wa = { 219 .reg = reg, 220 .clr = clear, 221 .set = set, 222 .read = read_mask, 223 .masked_reg = masked_reg, 224 }; 225 226 _wa_add(wal, &wa); 227 } 228 229 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 230 u32 clear, u32 set, u32 read_mask, bool masked_reg) 231 { 232 struct i915_wa wa = { 233 .mcr_reg = reg, 234 .clr = clear, 235 .set = set, 236 .read = read_mask, 237 .masked_reg = masked_reg, 238 .is_mcr = 1, 239 }; 240 241 _wa_add(wal, &wa); 242 } 243 244 static void 245 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 246 { 247 wa_add(wal, reg, clear, set, clear | set, false); 248 } 249 250 static void 251 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 252 { 253 wa_mcr_add(wal, reg, clear, set, clear | set, false); 254 } 255 256 static void 257 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 258 { 259 wa_write_clr_set(wal, reg, ~0, set); 260 } 261 262 static void 263 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 264 { 265 wa_write_clr_set(wal, reg, set, set); 266 } 267 268 static void 269 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 270 { 271 wa_mcr_write_clr_set(wal, reg, set, set); 272 } 273 274 static void 275 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 276 { 277 wa_write_clr_set(wal, reg, clr, 0); 278 } 279 280 static void 281 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 282 { 283 wa_mcr_write_clr_set(wal, reg, clr, 0); 284 } 285 286 /* 287 * WA operations on "masked register". A masked register has the upper 16 bits 288 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 289 * portion of the register without a rmw: you simply write in the upper 16 bits 290 * the mask of bits you are going to modify. 291 * 292 * The wa_masked_* family of functions already does the necessary operations to 293 * calculate the mask based on the parameters passed, so user only has to 294 * provide the lower 16 bits of that register. 295 */ 296 297 static void 298 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 299 { 300 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 301 } 302 303 static void 304 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 305 { 306 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 307 } 308 309 static void 310 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 311 { 312 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 313 } 314 315 static void 316 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 317 { 318 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 319 } 320 321 static void 322 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 323 u32 mask, u32 val) 324 { 325 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 326 } 327 328 static void 329 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 330 u32 mask, u32 val) 331 { 332 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 333 } 334 335 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 336 struct i915_wa_list *wal) 337 { 338 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 339 } 340 341 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 342 struct i915_wa_list *wal) 343 { 344 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 345 } 346 347 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 348 struct i915_wa_list *wal) 349 { 350 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 351 352 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 353 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 354 355 /* WaDisablePartialInstShootdown:bdw,chv */ 356 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 357 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 358 359 /* Use Force Non-Coherent whenever executing a 3D context. This is a 360 * workaround for a possible hang in the unlikely event a TLB 361 * invalidation occurs during a PSD flush. 362 */ 363 /* WaForceEnableNonCoherent:bdw,chv */ 364 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 365 wa_masked_en(wal, HDC_CHICKEN0, 366 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 367 HDC_FORCE_NON_COHERENT); 368 369 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 370 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 371 * polygons in the same 8x4 pixel/sample area to be processed without 372 * stalling waiting for the earlier ones to write to Hierarchical Z 373 * buffer." 374 * 375 * This optimization is off by default for BDW and CHV; turn it on. 376 */ 377 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 378 379 /* Wa4x4STCOptimizationDisable:bdw,chv */ 380 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 381 382 /* 383 * BSpec recommends 8x4 when MSAA is used, 384 * however in practice 16x4 seems fastest. 385 * 386 * Note that PS/WM thread counts depend on the WIZ hashing 387 * disable bit, which we don't touch here, but it's good 388 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 389 */ 390 wa_masked_field_set(wal, GEN7_GT_MODE, 391 GEN6_WIZ_HASHING_MASK, 392 GEN6_WIZ_HASHING_16x4); 393 } 394 395 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 396 struct i915_wa_list *wal) 397 { 398 struct drm_i915_private *i915 = engine->i915; 399 400 gen8_ctx_workarounds_init(engine, wal); 401 402 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 403 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 404 405 /* WaDisableDopClockGating:bdw 406 * 407 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 408 * to disable EUTC clock gating. 409 */ 410 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 411 DOP_CLOCK_GATING_DISABLE); 412 413 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 414 GEN8_SAMPLER_POWER_BYPASS_DIS); 415 416 wa_masked_en(wal, HDC_CHICKEN0, 417 /* WaForceContextSaveRestoreNonCoherent:bdw */ 418 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 419 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 420 (IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 421 } 422 423 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 424 struct i915_wa_list *wal) 425 { 426 gen8_ctx_workarounds_init(engine, wal); 427 428 /* WaDisableThreadStallDopClockGating:chv */ 429 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 430 431 /* Improve HiZ throughput on CHV. */ 432 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 433 } 434 435 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 436 struct i915_wa_list *wal) 437 { 438 struct drm_i915_private *i915 = engine->i915; 439 440 if (HAS_LLC(i915)) { 441 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 442 * 443 * Must match Display Engine. See 444 * WaCompressedResourceDisplayNewHashMode. 445 */ 446 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 447 GEN9_PBE_COMPRESSED_HASH_SELECTION); 448 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 449 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 450 } 451 452 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 453 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 454 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 455 FLOW_CONTROL_ENABLE | 456 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 457 458 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 459 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 460 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 461 GEN9_ENABLE_YV12_BUGFIX | 462 GEN9_ENABLE_GPGPU_PREEMPTION); 463 464 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 465 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 466 wa_masked_en(wal, CACHE_MODE_1, 467 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 468 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 469 470 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 471 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 472 GEN9_CCS_TLB_PREFETCH_ENABLE); 473 474 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 475 wa_masked_en(wal, HDC_CHICKEN0, 476 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 477 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 478 479 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 480 * both tied to WaForceContextSaveRestoreNonCoherent 481 * in some hsds for skl. We keep the tie for all gen9. The 482 * documentation is a bit hazy and so we want to get common behaviour, 483 * even though there is no clear evidence we would need both on kbl/bxt. 484 * This area has been source of system hangs so we play it safe 485 * and mimic the skl regardless of what bspec says. 486 * 487 * Use Force Non-Coherent whenever executing a 3D context. This 488 * is a workaround for a possible hang in the unlikely event 489 * a TLB invalidation occurs during a PSD flush. 490 */ 491 492 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 493 wa_masked_en(wal, HDC_CHICKEN0, 494 HDC_FORCE_NON_COHERENT); 495 496 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 497 if (IS_SKYLAKE(i915) || 498 IS_KABYLAKE(i915) || 499 IS_COFFEELAKE(i915) || 500 IS_COMETLAKE(i915)) 501 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 502 GEN8_SAMPLER_POWER_BYPASS_DIS); 503 504 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 505 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 506 507 /* 508 * Supporting preemption with fine-granularity requires changes in the 509 * batch buffer programming. Since we can't break old userspace, we 510 * need to set our default preemption level to safe value. Userspace is 511 * still able to use more fine-grained preemption levels, since in 512 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 513 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 514 * not real HW workarounds, but merely a way to start using preemption 515 * while maintaining old contract with userspace. 516 */ 517 518 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 519 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 520 521 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 522 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 523 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 524 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 525 526 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 527 if (IS_GEN9_LP(i915)) 528 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 529 } 530 531 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 532 struct i915_wa_list *wal) 533 { 534 struct intel_gt *gt = engine->gt; 535 u8 vals[3] = { 0, 0, 0 }; 536 unsigned int i; 537 538 for (i = 0; i < 3; i++) { 539 u8 ss; 540 541 /* 542 * Only consider slices where one, and only one, subslice has 7 543 * EUs 544 */ 545 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 546 continue; 547 548 /* 549 * subslice_7eu[i] != 0 (because of the check above) and 550 * ss_max == 4 (maximum number of subslices possible per slice) 551 * 552 * -> 0 <= ss <= 3; 553 */ 554 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 555 vals[i] = 3 - ss; 556 } 557 558 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 559 return; 560 561 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 562 wa_masked_field_set(wal, GEN7_GT_MODE, 563 GEN9_IZ_HASHING_MASK(2) | 564 GEN9_IZ_HASHING_MASK(1) | 565 GEN9_IZ_HASHING_MASK(0), 566 GEN9_IZ_HASHING(2, vals[2]) | 567 GEN9_IZ_HASHING(1, vals[1]) | 568 GEN9_IZ_HASHING(0, vals[0])); 569 } 570 571 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 572 struct i915_wa_list *wal) 573 { 574 gen9_ctx_workarounds_init(engine, wal); 575 skl_tune_iz_hashing(engine, wal); 576 } 577 578 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 579 struct i915_wa_list *wal) 580 { 581 gen9_ctx_workarounds_init(engine, wal); 582 583 /* WaDisableThreadStallDopClockGating:bxt */ 584 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 585 STALL_DOP_GATING_DISABLE); 586 587 /* WaToEnableHwFixForPushConstHWBug:bxt */ 588 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 589 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 590 } 591 592 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 593 struct i915_wa_list *wal) 594 { 595 struct drm_i915_private *i915 = engine->i915; 596 597 gen9_ctx_workarounds_init(engine, wal); 598 599 /* WaToEnableHwFixForPushConstHWBug:kbl */ 600 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 601 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 602 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 603 604 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 605 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 606 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 607 } 608 609 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 610 struct i915_wa_list *wal) 611 { 612 gen9_ctx_workarounds_init(engine, wal); 613 614 /* WaToEnableHwFixForPushConstHWBug:glk */ 615 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 616 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 617 } 618 619 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 620 struct i915_wa_list *wal) 621 { 622 gen9_ctx_workarounds_init(engine, wal); 623 624 /* WaToEnableHwFixForPushConstHWBug:cfl */ 625 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 626 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 627 628 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 629 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 630 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 631 } 632 633 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 634 struct i915_wa_list *wal) 635 { 636 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 637 wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL); 638 639 /* WaForceEnableNonCoherent:icl 640 * This is not the same workaround as in early Gen9 platforms, where 641 * lacking this could cause system hangs, but coherency performance 642 * overhead is high and only a few compute workloads really need it 643 * (the register is whitelisted in hardware now, so UMDs can opt in 644 * for coherency if they have a good reason). 645 */ 646 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 647 648 /* WaEnableFloatBlendOptimization:icl */ 649 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 650 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 651 0 /* write-only, so skip validation */, 652 true); 653 654 /* WaDisableGPGPUMidThreadPreemption:icl */ 655 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 656 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 657 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 658 659 /* allow headerless messages for preemptible GPGPU context */ 660 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 661 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 662 663 /* Wa_1604278689:icl,ehl */ 664 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 665 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 666 0, 667 0xFFFFFFFF); 668 669 /* Wa_1406306137:icl,ehl */ 670 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 671 } 672 673 /* 674 * These settings aren't actually workarounds, but general tuning settings that 675 * need to be programmed on dg2 platform. 676 */ 677 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 678 struct i915_wa_list *wal) 679 { 680 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 681 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 682 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 683 wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK, 684 FF_MODE2_TDS_TIMER_128); 685 } 686 687 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 688 struct i915_wa_list *wal) 689 { 690 struct drm_i915_private *i915 = engine->i915; 691 692 /* 693 * Wa_1409142259:tgl,dg1,adl-p 694 * Wa_1409347922:tgl,dg1,adl-p 695 * Wa_1409252684:tgl,dg1,adl-p 696 * Wa_1409217633:tgl,dg1,adl-p 697 * Wa_1409207793:tgl,dg1,adl-p 698 * Wa_1409178076:tgl,dg1,adl-p 699 * Wa_1408979724:tgl,dg1,adl-p 700 * Wa_14010443199:tgl,rkl,dg1,adl-p 701 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 702 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 703 */ 704 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 705 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 706 707 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 708 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 709 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 710 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 711 712 /* 713 * Wa_16011163337 - GS_TIMER 714 * 715 * TDS_TIMER: Although some platforms refer to it as Wa_1604555607, we 716 * need to program it even on those that don't explicitly list that 717 * workaround. 718 * 719 * Note that the programming of GEN12_FF_MODE2 is further modified 720 * according to the FF_MODE2 guidance given by Wa_1608008084. 721 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 722 * value when read from the CPU. 723 * 724 * The default value for this register is zero for all fields. 725 * So instead of doing a RMW we should just write the desired values 726 * for TDS and GS timers. Note that since the readback can't be trusted, 727 * the clear mask is just set to ~0 to make sure other bits are not 728 * inadvertently set. For the same reason read verification is ignored. 729 */ 730 wa_add(wal, 731 GEN12_FF_MODE2, 732 ~0, 733 FF_MODE2_TDS_TIMER_128 | FF_MODE2_GS_TIMER_224, 734 0, false); 735 736 if (!IS_DG1(i915)) { 737 /* Wa_1806527549 */ 738 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 739 740 /* Wa_1606376872 */ 741 wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); 742 } 743 } 744 745 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 746 struct i915_wa_list *wal) 747 { 748 gen12_ctx_workarounds_init(engine, wal); 749 750 /* Wa_1409044764 */ 751 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 752 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 753 754 /* Wa_22010493298 */ 755 wa_masked_en(wal, HIZ_CHICKEN, 756 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 757 } 758 759 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 760 struct i915_wa_list *wal) 761 { 762 dg2_ctx_gt_tuning_init(engine, wal); 763 764 /* Wa_16013271637:dg2 */ 765 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 766 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 767 768 /* Wa_14014947963:dg2 */ 769 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 770 771 /* Wa_18018764978:dg2 */ 772 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 773 774 /* Wa_18019271663:dg2 */ 775 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 776 777 /* Wa_14019877138:dg2 */ 778 wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT); 779 } 780 781 static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine, 782 struct i915_wa_list *wal) 783 { 784 struct intel_gt *gt = engine->gt; 785 786 dg2_ctx_gt_tuning_init(engine, wal); 787 788 /* 789 * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in 790 * gen12_emit_indirect_ctx_rcs() rather than here on some early 791 * steppings. 792 */ 793 if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 794 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))) 795 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); 796 } 797 798 static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine, 799 struct i915_wa_list *wal) 800 { 801 struct intel_gt *gt = engine->gt; 802 803 xelpg_ctx_gt_tuning_init(engine, wal); 804 805 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 806 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { 807 /* Wa_14014947963 */ 808 wa_masked_field_set(wal, VF_PREEMPTION, 809 PREEMPTION_VERTEX_COUNT, 0x4000); 810 811 /* Wa_16013271637 */ 812 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 813 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 814 815 /* Wa_18019627453 */ 816 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS); 817 818 /* Wa_18018764978 */ 819 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 820 } 821 822 /* Wa_18019271663 */ 823 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 824 825 /* Wa_14019877138 */ 826 wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT); 827 } 828 829 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 830 struct i915_wa_list *wal) 831 { 832 /* 833 * This is a "fake" workaround defined by software to ensure we 834 * maintain reliable, backward-compatible behavior for userspace with 835 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 836 * 837 * The per-context setting of MI_MODE[12] determines whether the bits 838 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 839 * in the traditional manner or whether they should instead use a new 840 * tgl+ meaning that breaks backward compatibility, but allows nesting 841 * into 3rd-level batchbuffers. When this new capability was first 842 * added in TGL, it remained off by default unless a context 843 * intentionally opted in to the new behavior. However Xe_HPG now 844 * flips this on by default and requires that we explicitly opt out if 845 * we don't want the new behavior. 846 * 847 * From a SW perspective, we want to maintain the backward-compatible 848 * behavior for userspace, so we'll apply a fake workaround to set it 849 * back to the legacy behavior on platforms where the hardware default 850 * is to break compatibility. At the moment there is no Linux 851 * userspace that utilizes third-level batchbuffers, so this will avoid 852 * userspace from needing to make any changes. using the legacy 853 * meaning is the correct thing to do. If/when we have userspace 854 * consumers that want to utilize third-level batch nesting, we can 855 * provide a context parameter to allow them to opt-in. 856 */ 857 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 858 } 859 860 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 861 struct i915_wa_list *wal) 862 { 863 u8 mocs; 864 865 /* 866 * Some blitter commands do not have a field for MOCS, those 867 * commands will use MOCS index pointed by BLIT_CCTL. 868 * BLIT_CCTL registers are needed to be programmed to un-cached. 869 */ 870 if (engine->class == COPY_ENGINE_CLASS) { 871 mocs = engine->gt->mocs.uc_index; 872 wa_write_clr_set(wal, 873 BLIT_CCTL(engine->mmio_base), 874 BLIT_CCTL_MASK, 875 BLIT_CCTL_MOCS(mocs, mocs)); 876 } 877 } 878 879 /* 880 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 881 * defined by the hardware team, but it programming general context registers. 882 * Adding those context register programming in context workaround 883 * allow us to use the wa framework for proper application and validation. 884 */ 885 static void 886 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 887 struct i915_wa_list *wal) 888 { 889 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 890 fakewa_disable_nestedbb_mode(engine, wal); 891 892 gen12_ctx_gt_mocs_init(engine, wal); 893 } 894 895 static void 896 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 897 struct i915_wa_list *wal, 898 const char *name) 899 { 900 struct drm_i915_private *i915 = engine->i915; 901 902 wa_init_start(wal, engine->gt, name, engine->name); 903 904 /* Applies to all engines */ 905 /* 906 * Fake workarounds are not the actual workaround but 907 * programming of context registers using workaround framework. 908 */ 909 if (GRAPHICS_VER(i915) >= 12) 910 gen12_ctx_gt_fake_wa_init(engine, wal); 911 912 if (engine->class != RENDER_CLASS) 913 goto done; 914 915 if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) 916 xelpg_ctx_workarounds_init(engine, wal); 917 else if (IS_DG2(i915)) 918 dg2_ctx_workarounds_init(engine, wal); 919 else if (IS_DG1(i915)) 920 dg1_ctx_workarounds_init(engine, wal); 921 else if (GRAPHICS_VER(i915) == 12) 922 gen12_ctx_workarounds_init(engine, wal); 923 else if (GRAPHICS_VER(i915) == 11) 924 icl_ctx_workarounds_init(engine, wal); 925 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 926 cfl_ctx_workarounds_init(engine, wal); 927 else if (IS_GEMINILAKE(i915)) 928 glk_ctx_workarounds_init(engine, wal); 929 else if (IS_KABYLAKE(i915)) 930 kbl_ctx_workarounds_init(engine, wal); 931 else if (IS_BROXTON(i915)) 932 bxt_ctx_workarounds_init(engine, wal); 933 else if (IS_SKYLAKE(i915)) 934 skl_ctx_workarounds_init(engine, wal); 935 else if (IS_CHERRYVIEW(i915)) 936 chv_ctx_workarounds_init(engine, wal); 937 else if (IS_BROADWELL(i915)) 938 bdw_ctx_workarounds_init(engine, wal); 939 else if (GRAPHICS_VER(i915) == 7) 940 gen7_ctx_workarounds_init(engine, wal); 941 else if (GRAPHICS_VER(i915) == 6) 942 gen6_ctx_workarounds_init(engine, wal); 943 else if (GRAPHICS_VER(i915) < 8) 944 ; 945 else 946 MISSING_CASE(GRAPHICS_VER(i915)); 947 948 done: 949 wa_init_finish(wal); 950 } 951 952 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 953 { 954 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 955 } 956 957 int intel_engine_emit_ctx_wa(struct i915_request *rq) 958 { 959 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 960 struct intel_uncore *uncore = rq->engine->uncore; 961 enum forcewake_domains fw; 962 unsigned long flags; 963 struct i915_wa *wa; 964 unsigned int i; 965 u32 *cs; 966 int ret; 967 968 if (wal->count == 0) 969 return 0; 970 971 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 972 if (ret) 973 return ret; 974 975 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 976 if (IS_ERR(cs)) 977 return PTR_ERR(cs); 978 979 fw = wal_get_fw_for_rmw(uncore, wal); 980 981 intel_gt_mcr_lock(wal->gt, &flags); 982 spin_lock(&uncore->lock); 983 intel_uncore_forcewake_get__locked(uncore, fw); 984 985 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 986 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 987 u32 val; 988 989 /* Skip reading the register if it's not really needed */ 990 if (wa->masked_reg || (wa->clr | wa->set) == U32_MAX) { 991 val = wa->set; 992 } else { 993 val = wa->is_mcr ? 994 intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) : 995 intel_uncore_read_fw(uncore, wa->reg); 996 val &= ~wa->clr; 997 val |= wa->set; 998 } 999 1000 *cs++ = i915_mmio_reg_offset(wa->reg); 1001 *cs++ = val; 1002 } 1003 *cs++ = MI_NOOP; 1004 1005 intel_uncore_forcewake_put__locked(uncore, fw); 1006 spin_unlock(&uncore->lock); 1007 intel_gt_mcr_unlock(wal->gt, flags); 1008 1009 intel_ring_advance(rq, cs); 1010 1011 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 1012 if (ret) 1013 return ret; 1014 1015 return 0; 1016 } 1017 1018 static void 1019 gen4_gt_workarounds_init(struct intel_gt *gt, 1020 struct i915_wa_list *wal) 1021 { 1022 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 1023 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 1024 } 1025 1026 static void 1027 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1028 { 1029 gen4_gt_workarounds_init(gt, wal); 1030 1031 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 1032 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 1033 } 1034 1035 static void 1036 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1037 { 1038 g4x_gt_workarounds_init(gt, wal); 1039 1040 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 1041 } 1042 1043 static void 1044 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1045 { 1046 } 1047 1048 static void 1049 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1050 { 1051 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 1052 wa_masked_dis(wal, 1053 GEN7_COMMON_SLICE_CHICKEN1, 1054 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 1055 1056 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 1057 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 1058 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 1059 1060 /* WaForceL3Serialization:ivb */ 1061 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1062 } 1063 1064 static void 1065 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1066 { 1067 /* WaForceL3Serialization:vlv */ 1068 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1069 1070 /* 1071 * WaIncreaseL3CreditsForVLVB0:vlv 1072 * This is the hardware default actually. 1073 */ 1074 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1075 } 1076 1077 static void 1078 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1079 { 1080 /* L3 caching of data atomics doesn't work -- disable it. */ 1081 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1082 1083 wa_add(wal, 1084 HSW_ROW_CHICKEN3, 0, 1085 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1086 0 /* XXX does this reg exist? */, true); 1087 1088 /* WaVSRefCountFullforceMissDisable:hsw */ 1089 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1090 } 1091 1092 static void 1093 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1094 { 1095 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1096 unsigned int slice, subslice; 1097 u32 mcr, mcr_mask; 1098 1099 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1100 1101 /* 1102 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1103 * Before any MMIO read into slice/subslice specific registers, MCR 1104 * packet control register needs to be programmed to point to any 1105 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1106 * This means each subsequent MMIO read will be forwarded to an 1107 * specific s/ss combination, but this is OK since these registers 1108 * are consistent across s/ss in almost all cases. In the rare 1109 * occasions, such as INSTDONE, where this value is dependent 1110 * on s/ss combo, the read should be done with read_subslice_reg. 1111 */ 1112 slice = ffs(sseu->slice_mask) - 1; 1113 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1114 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1115 GEM_BUG_ON(!subslice); 1116 subslice--; 1117 1118 /* 1119 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1120 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1121 */ 1122 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1123 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1124 1125 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1126 1127 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1128 } 1129 1130 static void 1131 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1132 { 1133 struct drm_i915_private *i915 = gt->i915; 1134 1135 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1136 gen9_wa_init_mcr(i915, wal); 1137 1138 /* WaDisableKillLogic:bxt,skl,kbl */ 1139 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1140 wa_write_or(wal, 1141 GAM_ECOCHK, 1142 ECOCHK_DIS_TLB); 1143 1144 if (HAS_LLC(i915)) { 1145 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1146 * 1147 * Must match Display Engine. See 1148 * WaCompressedResourceDisplayNewHashMode. 1149 */ 1150 wa_write_or(wal, 1151 MMCD_MISC_CTRL, 1152 MMCD_PCLA | MMCD_HOTSPOT_EN); 1153 } 1154 1155 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1156 wa_write_or(wal, 1157 GAM_ECOCHK, 1158 BDW_DISABLE_HDC_INVALIDATION); 1159 } 1160 1161 static void 1162 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1163 { 1164 gen9_gt_workarounds_init(gt, wal); 1165 1166 /* WaDisableGafsUnitClkGating:skl */ 1167 wa_write_or(wal, 1168 GEN7_UCGCTL4, 1169 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1170 1171 /* WaInPlaceDecompressionHang:skl */ 1172 if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1173 wa_write_or(wal, 1174 GEN9_GAMT_ECO_REG_RW_IA, 1175 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1176 } 1177 1178 static void 1179 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1180 { 1181 gen9_gt_workarounds_init(gt, wal); 1182 1183 /* WaDisableDynamicCreditSharing:kbl */ 1184 if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1185 wa_write_or(wal, 1186 GAMT_CHKN_BIT_REG, 1187 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1188 1189 /* WaDisableGafsUnitClkGating:kbl */ 1190 wa_write_or(wal, 1191 GEN7_UCGCTL4, 1192 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1193 1194 /* WaInPlaceDecompressionHang:kbl */ 1195 wa_write_or(wal, 1196 GEN9_GAMT_ECO_REG_RW_IA, 1197 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1198 } 1199 1200 static void 1201 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1202 { 1203 gen9_gt_workarounds_init(gt, wal); 1204 } 1205 1206 static void 1207 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1208 { 1209 gen9_gt_workarounds_init(gt, wal); 1210 1211 /* WaDisableGafsUnitClkGating:cfl */ 1212 wa_write_or(wal, 1213 GEN7_UCGCTL4, 1214 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1215 1216 /* WaInPlaceDecompressionHang:cfl */ 1217 wa_write_or(wal, 1218 GEN9_GAMT_ECO_REG_RW_IA, 1219 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1220 } 1221 1222 static void __set_mcr_steering(struct i915_wa_list *wal, 1223 i915_reg_t steering_reg, 1224 unsigned int slice, unsigned int subslice) 1225 { 1226 u32 mcr, mcr_mask; 1227 1228 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1229 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1230 1231 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1232 } 1233 1234 static void debug_dump_steering(struct intel_gt *gt) 1235 { 1236 struct drm_printer p = drm_dbg_printer(>->i915->drm, DRM_UT_DRIVER, 1237 "MCR Steering:"); 1238 1239 if (drm_debug_enabled(DRM_UT_DRIVER)) 1240 intel_gt_mcr_report_steering(&p, gt, false); 1241 } 1242 1243 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1244 unsigned int slice, unsigned int subslice) 1245 { 1246 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1247 1248 gt->default_steering.groupid = slice; 1249 gt->default_steering.instanceid = subslice; 1250 1251 debug_dump_steering(gt); 1252 } 1253 1254 static void 1255 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1256 { 1257 const struct sseu_dev_info *sseu = >->info.sseu; 1258 unsigned int subslice; 1259 1260 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1261 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1262 1263 /* 1264 * Although a platform may have subslices, we need to always steer 1265 * reads to the lowest instance that isn't fused off. When Render 1266 * Power Gating is enabled, grabbing forcewake will only power up a 1267 * single subslice (the "minconfig") if there isn't a real workload 1268 * that needs to be run; this means that if we steer register reads to 1269 * one of the higher subslices, we run the risk of reading back 0's or 1270 * random garbage. 1271 */ 1272 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1273 1274 /* 1275 * If the subslice we picked above also steers us to a valid L3 bank, 1276 * then we can just rely on the default steering and won't need to 1277 * worry about explicitly re-steering L3BANK reads later. 1278 */ 1279 if (gt->info.l3bank_mask & BIT(subslice)) 1280 gt->steering_table[L3BANK] = NULL; 1281 1282 __add_mcr_wa(gt, wal, 0, subslice); 1283 } 1284 1285 static void 1286 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1287 { 1288 const struct sseu_dev_info *sseu = >->info.sseu; 1289 unsigned long slice, subslice = 0, slice_mask = 0; 1290 u32 lncf_mask = 0; 1291 int i; 1292 1293 /* 1294 * On Xe_HP the steering increases in complexity. There are now several 1295 * more units that require steering and we're not guaranteed to be able 1296 * to find a common setting for all of them. These are: 1297 * - GSLICE (fusable) 1298 * - DSS (sub-unit within gslice; fusable) 1299 * - L3 Bank (fusable) 1300 * - MSLICE (fusable) 1301 * - LNCF (sub-unit within mslice; always present if mslice is present) 1302 * 1303 * We'll do our default/implicit steering based on GSLICE (in the 1304 * sliceid field) and DSS (in the subsliceid field). If we can 1305 * find overlap between the valid MSLICE and/or LNCF values with 1306 * a suitable GSLICE, then we can just re-use the default value and 1307 * skip and explicit steering at runtime. 1308 * 1309 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1310 * a valid sliceid value. DSS steering is the only type of steering 1311 * that utilizes the 'subsliceid' bits. 1312 * 1313 * Also note that, even though the steering domain is called "GSlice" 1314 * and it is encoded in the register using the gslice format, the spec 1315 * says that the combined (geometry | compute) fuse should be used to 1316 * select the steering. 1317 */ 1318 1319 /* Find the potential gslice candidates */ 1320 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1321 GEN_DSS_PER_GSLICE); 1322 1323 /* 1324 * Find the potential LNCF candidates. Either LNCF within a valid 1325 * mslice is fine. 1326 */ 1327 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1328 lncf_mask |= (0x3 << (i * 2)); 1329 1330 /* 1331 * Are there any sliceid values that work for both GSLICE and LNCF 1332 * steering? 1333 */ 1334 if (slice_mask & lncf_mask) { 1335 slice_mask &= lncf_mask; 1336 gt->steering_table[LNCF] = NULL; 1337 } 1338 1339 /* How about sliceid values that also work for MSLICE steering? */ 1340 if (slice_mask & gt->info.mslice_mask) { 1341 slice_mask &= gt->info.mslice_mask; 1342 gt->steering_table[MSLICE] = NULL; 1343 } 1344 1345 slice = __ffs(slice_mask); 1346 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1347 GEN_DSS_PER_GSLICE; 1348 1349 __add_mcr_wa(gt, wal, slice, subslice); 1350 1351 /* 1352 * SQIDI ranges are special because they use different steering 1353 * registers than everything else we work with. On XeHP SDV and 1354 * DG2-G10, any value in the steering registers will work fine since 1355 * all instances are present, but DG2-G11 only has SQIDI instances at 1356 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1357 * we'll just steer to a hardcoded "2" since that value will work 1358 * everywhere. 1359 */ 1360 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1361 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1362 1363 /* 1364 * On DG2, GAM registers have a dedicated steering control register 1365 * and must always be programmed to a hardcoded groupid of "1." 1366 */ 1367 if (IS_DG2(gt->i915)) 1368 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1369 } 1370 1371 static void 1372 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1373 { 1374 struct drm_i915_private *i915 = gt->i915; 1375 1376 icl_wa_init_mcr(gt, wal); 1377 1378 /* WaModifyGamTlbPartitioning:icl */ 1379 wa_write_clr_set(wal, 1380 GEN11_GACB_PERF_CTRL, 1381 GEN11_HASH_CTRL_MASK, 1382 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1383 1384 /* Wa_1405766107:icl 1385 * Formerly known as WaCL2SFHalfMaxAlloc 1386 */ 1387 wa_write_or(wal, 1388 GEN11_LSN_UNSLCVC, 1389 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1390 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1391 1392 /* Wa_220166154:icl 1393 * Formerly known as WaDisCtxReload 1394 */ 1395 wa_write_or(wal, 1396 GEN8_GAMW_ECO_DEV_RW_IA, 1397 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1398 1399 /* Wa_1406463099:icl 1400 * Formerly known as WaGamTlbPendError 1401 */ 1402 wa_write_or(wal, 1403 GAMT_CHKN_BIT_REG, 1404 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1405 1406 /* 1407 * Wa_1408615072:icl,ehl (vsunit) 1408 * Wa_1407596294:icl,ehl (hsunit) 1409 */ 1410 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1411 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1412 1413 /* Wa_1407352427:icl,ehl */ 1414 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1415 PSDUNIT_CLKGATE_DIS); 1416 1417 /* Wa_1406680159:icl,ehl */ 1418 wa_mcr_write_or(wal, 1419 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1420 GWUNIT_CLKGATE_DIS); 1421 1422 /* Wa_1607087056:icl,ehl,jsl */ 1423 if (IS_ICELAKE(i915) || 1424 ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && 1425 IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))) 1426 wa_write_or(wal, 1427 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1428 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1429 1430 /* 1431 * This is not a documented workaround, but rather an optimization 1432 * to reduce sampler power. 1433 */ 1434 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1435 } 1436 1437 /* 1438 * Though there are per-engine instances of these registers, 1439 * they retain their value through engine resets and should 1440 * only be provided on the GT workaround list rather than 1441 * the engine-specific workaround list. 1442 */ 1443 static void 1444 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1445 { 1446 struct intel_engine_cs *engine; 1447 int id; 1448 1449 for_each_engine(engine, gt, id) { 1450 if (engine->class != VIDEO_DECODE_CLASS || 1451 (engine->instance % 2)) 1452 continue; 1453 1454 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1455 IECPUNIT_CLKGATE_DIS); 1456 } 1457 } 1458 1459 static void 1460 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1461 { 1462 icl_wa_init_mcr(gt, wal); 1463 1464 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1465 wa_14011060649(gt, wal); 1466 1467 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1468 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1469 1470 /* 1471 * Wa_14015795083 1472 * 1473 * Firmware on some gen12 platforms locks the MISCCPCTL register, 1474 * preventing i915 from modifying it for this workaround. Skip the 1475 * readback verification for this workaround on debug builds; if the 1476 * workaround doesn't stick due to firmware behavior, it's not an error 1477 * that we want CI to flag. 1478 */ 1479 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, 1480 0, 0, false); 1481 } 1482 1483 static void 1484 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1485 { 1486 gen12_gt_workarounds_init(gt, wal); 1487 1488 /* Wa_1409420604:dg1 */ 1489 wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, 1490 CPSSUNIT_CLKGATE_DIS); 1491 1492 /* Wa_1408615072:dg1 */ 1493 /* Empirical testing shows this register is unaffected by engine reset. */ 1494 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); 1495 } 1496 1497 static void 1498 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1499 { 1500 xehp_init_mcr(gt, wal); 1501 1502 /* Wa_14011060649:dg2 */ 1503 wa_14011060649(gt, wal); 1504 1505 if (IS_DG2_G10(gt->i915)) { 1506 /* Wa_22010523718:dg2 */ 1507 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1508 CG3DDISCFEG_CLKGATE_DIS); 1509 1510 /* Wa_14011006942:dg2 */ 1511 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1512 DSS_ROUTER_CLKGATE_DIS); 1513 } 1514 1515 /* Wa_14014830051:dg2 */ 1516 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1517 1518 /* 1519 * Wa_14015795083 1520 * Skip verification for possibly locked register. 1521 */ 1522 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, 1523 0, 0, false); 1524 1525 /* Wa_18018781329 */ 1526 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1527 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1528 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1529 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1530 1531 /* Wa_1509235366:dg2 */ 1532 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, 1533 INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); 1534 1535 /* Wa_14010648519:dg2 */ 1536 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 1537 } 1538 1539 static void 1540 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1541 { 1542 /* Wa_14018575942 / Wa_18018781329 */ 1543 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1544 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1545 1546 /* Wa_22016670082 */ 1547 wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); 1548 1549 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 1550 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { 1551 /* Wa_14014830051 */ 1552 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1553 1554 /* Wa_14015795083 */ 1555 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1556 } 1557 1558 /* 1559 * Unlike older platforms, we no longer setup implicit steering here; 1560 * all MCR accesses are explicitly steered. 1561 */ 1562 debug_dump_steering(gt); 1563 } 1564 1565 static void 1566 wa_16021867713(struct intel_gt *gt, struct i915_wa_list *wal) 1567 { 1568 struct intel_engine_cs *engine; 1569 int id; 1570 1571 for_each_engine(engine, gt, id) 1572 if (engine->class == VIDEO_DECODE_CLASS) 1573 wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base), 1574 MFXPIPE_CLKGATE_DIS); 1575 } 1576 1577 static void 1578 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1579 { 1580 wa_16021867713(gt, wal); 1581 1582 /* 1583 * Wa_14018778641 1584 * Wa_18018781329 1585 * 1586 * Note that although these registers are MCR on the primary 1587 * GT, the media GT's versions are regular singleton registers. 1588 */ 1589 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); 1590 1591 /* Wa_22016670082 */ 1592 wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); 1593 1594 debug_dump_steering(gt); 1595 } 1596 1597 /* 1598 * The bspec performance guide has recommended MMIO tuning settings. These 1599 * aren't truly "workarounds" but we want to program them through the 1600 * workaround infrastructure to make sure they're (re)applied at the proper 1601 * times. 1602 * 1603 * The programming in this function is for settings that persist through 1604 * engine resets and also are not part of any engine's register state context. 1605 * I.e., settings that only need to be re-applied in the event of a full GT 1606 * reset. 1607 */ 1608 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) 1609 { 1610 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { 1611 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1612 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1613 } 1614 1615 if (IS_DG2(gt->i915)) { 1616 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1617 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1618 } 1619 } 1620 1621 static void 1622 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1623 { 1624 struct drm_i915_private *i915 = gt->i915; 1625 1626 gt_tuning_settings(gt, wal); 1627 1628 if (gt->type == GT_MEDIA) { 1629 if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) 1630 xelpmp_gt_workarounds_init(gt, wal); 1631 else 1632 MISSING_CASE(MEDIA_VER_FULL(i915)); 1633 1634 return; 1635 } 1636 1637 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) 1638 xelpg_gt_workarounds_init(gt, wal); 1639 else if (IS_DG2(i915)) 1640 dg2_gt_workarounds_init(gt, wal); 1641 else if (IS_DG1(i915)) 1642 dg1_gt_workarounds_init(gt, wal); 1643 else if (GRAPHICS_VER(i915) == 12) 1644 gen12_gt_workarounds_init(gt, wal); 1645 else if (GRAPHICS_VER(i915) == 11) 1646 icl_gt_workarounds_init(gt, wal); 1647 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1648 cfl_gt_workarounds_init(gt, wal); 1649 else if (IS_GEMINILAKE(i915)) 1650 glk_gt_workarounds_init(gt, wal); 1651 else if (IS_KABYLAKE(i915)) 1652 kbl_gt_workarounds_init(gt, wal); 1653 else if (IS_BROXTON(i915)) 1654 gen9_gt_workarounds_init(gt, wal); 1655 else if (IS_SKYLAKE(i915)) 1656 skl_gt_workarounds_init(gt, wal); 1657 else if (IS_HASWELL(i915)) 1658 hsw_gt_workarounds_init(gt, wal); 1659 else if (IS_VALLEYVIEW(i915)) 1660 vlv_gt_workarounds_init(gt, wal); 1661 else if (IS_IVYBRIDGE(i915)) 1662 ivb_gt_workarounds_init(gt, wal); 1663 else if (GRAPHICS_VER(i915) == 6) 1664 snb_gt_workarounds_init(gt, wal); 1665 else if (GRAPHICS_VER(i915) == 5) 1666 ilk_gt_workarounds_init(gt, wal); 1667 else if (IS_G4X(i915)) 1668 g4x_gt_workarounds_init(gt, wal); 1669 else if (GRAPHICS_VER(i915) == 4) 1670 gen4_gt_workarounds_init(gt, wal); 1671 else if (GRAPHICS_VER(i915) <= 8) 1672 ; 1673 else 1674 MISSING_CASE(GRAPHICS_VER(i915)); 1675 } 1676 1677 void intel_gt_init_workarounds(struct intel_gt *gt) 1678 { 1679 struct i915_wa_list *wal = >->wa_list; 1680 1681 wa_init_start(wal, gt, "GT", "global"); 1682 gt_init_workarounds(gt, wal); 1683 wa_init_finish(wal); 1684 } 1685 1686 static bool 1687 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1688 const char *name, const char *from) 1689 { 1690 if ((cur ^ wa->set) & wa->read) { 1691 gt_err(gt, 1692 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1693 name, from, i915_mmio_reg_offset(wa->reg), 1694 cur, cur & wa->read, wa->set & wa->read); 1695 1696 return false; 1697 } 1698 1699 return true; 1700 } 1701 1702 static void wa_list_apply(const struct i915_wa_list *wal) 1703 { 1704 struct intel_gt *gt = wal->gt; 1705 struct intel_uncore *uncore = gt->uncore; 1706 enum forcewake_domains fw; 1707 unsigned long flags; 1708 struct i915_wa *wa; 1709 unsigned int i; 1710 1711 if (!wal->count) 1712 return; 1713 1714 fw = wal_get_fw_for_rmw(uncore, wal); 1715 1716 intel_gt_mcr_lock(gt, &flags); 1717 spin_lock(&uncore->lock); 1718 intel_uncore_forcewake_get__locked(uncore, fw); 1719 1720 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1721 u32 val, old = 0; 1722 1723 /* open-coded rmw due to steering */ 1724 if (wa->clr) 1725 old = wa->is_mcr ? 1726 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1727 intel_uncore_read_fw(uncore, wa->reg); 1728 val = (old & ~wa->clr) | wa->set; 1729 if (val != old || !wa->clr) { 1730 if (wa->is_mcr) 1731 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1732 else 1733 intel_uncore_write_fw(uncore, wa->reg, val); 1734 } 1735 1736 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1737 u32 val = wa->is_mcr ? 1738 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1739 intel_uncore_read_fw(uncore, wa->reg); 1740 1741 wa_verify(gt, wa, val, wal->name, "application"); 1742 } 1743 } 1744 1745 intel_uncore_forcewake_put__locked(uncore, fw); 1746 spin_unlock(&uncore->lock); 1747 intel_gt_mcr_unlock(gt, flags); 1748 } 1749 1750 void intel_gt_apply_workarounds(struct intel_gt *gt) 1751 { 1752 wa_list_apply(>->wa_list); 1753 } 1754 1755 static bool wa_list_verify(struct intel_gt *gt, 1756 const struct i915_wa_list *wal, 1757 const char *from) 1758 { 1759 struct intel_uncore *uncore = gt->uncore; 1760 struct i915_wa *wa; 1761 enum forcewake_domains fw; 1762 unsigned long flags; 1763 unsigned int i; 1764 bool ok = true; 1765 1766 fw = wal_get_fw_for_rmw(uncore, wal); 1767 1768 intel_gt_mcr_lock(gt, &flags); 1769 spin_lock(&uncore->lock); 1770 intel_uncore_forcewake_get__locked(uncore, fw); 1771 1772 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1773 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1774 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1775 intel_uncore_read_fw(uncore, wa->reg), 1776 wal->name, from); 1777 1778 intel_uncore_forcewake_put__locked(uncore, fw); 1779 spin_unlock(&uncore->lock); 1780 intel_gt_mcr_unlock(gt, flags); 1781 1782 return ok; 1783 } 1784 1785 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1786 { 1787 return wa_list_verify(gt, >->wa_list, from); 1788 } 1789 1790 __maybe_unused 1791 static bool is_nonpriv_flags_valid(u32 flags) 1792 { 1793 /* Check only valid flag bits are set */ 1794 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1795 return false; 1796 1797 /* NB: Only 3 out of 4 enum values are valid for access field */ 1798 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1799 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1800 return false; 1801 1802 return true; 1803 } 1804 1805 static void 1806 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1807 { 1808 struct i915_wa wa = { 1809 .reg = reg 1810 }; 1811 1812 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1813 return; 1814 1815 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1816 return; 1817 1818 wa.reg.reg |= flags; 1819 _wa_add(wal, &wa); 1820 } 1821 1822 static void 1823 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 1824 { 1825 struct i915_wa wa = { 1826 .mcr_reg = reg, 1827 .is_mcr = 1, 1828 }; 1829 1830 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1831 return; 1832 1833 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1834 return; 1835 1836 wa.mcr_reg.reg |= flags; 1837 _wa_add(wal, &wa); 1838 } 1839 1840 static void 1841 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1842 { 1843 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1844 } 1845 1846 static void 1847 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 1848 { 1849 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1850 } 1851 1852 static void gen9_whitelist_build(struct i915_wa_list *w) 1853 { 1854 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1855 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1856 1857 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1858 whitelist_reg(w, GEN8_CS_CHICKEN1); 1859 1860 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1861 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1862 1863 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1864 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1865 } 1866 1867 static void skl_whitelist_build(struct intel_engine_cs *engine) 1868 { 1869 struct i915_wa_list *w = &engine->whitelist; 1870 1871 if (engine->class != RENDER_CLASS) 1872 return; 1873 1874 gen9_whitelist_build(w); 1875 1876 /* WaDisableLSQCROPERFforOCL:skl */ 1877 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1878 } 1879 1880 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1881 { 1882 if (engine->class != RENDER_CLASS) 1883 return; 1884 1885 gen9_whitelist_build(&engine->whitelist); 1886 } 1887 1888 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1889 { 1890 struct i915_wa_list *w = &engine->whitelist; 1891 1892 if (engine->class != RENDER_CLASS) 1893 return; 1894 1895 gen9_whitelist_build(w); 1896 1897 /* WaDisableLSQCROPERFforOCL:kbl */ 1898 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1899 } 1900 1901 static void glk_whitelist_build(struct intel_engine_cs *engine) 1902 { 1903 struct i915_wa_list *w = &engine->whitelist; 1904 1905 if (engine->class != RENDER_CLASS) 1906 return; 1907 1908 gen9_whitelist_build(w); 1909 1910 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1911 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1912 } 1913 1914 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1915 { 1916 struct i915_wa_list *w = &engine->whitelist; 1917 1918 if (engine->class != RENDER_CLASS) 1919 return; 1920 1921 gen9_whitelist_build(w); 1922 1923 /* 1924 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1925 * 1926 * This covers 4 register which are next to one another : 1927 * - PS_INVOCATION_COUNT 1928 * - PS_INVOCATION_COUNT_UDW 1929 * - PS_DEPTH_COUNT 1930 * - PS_DEPTH_COUNT_UDW 1931 */ 1932 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1933 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1934 RING_FORCE_TO_NONPRIV_RANGE_4); 1935 } 1936 1937 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1938 { 1939 struct i915_wa_list *w = &engine->whitelist; 1940 1941 if (engine->class != RENDER_CLASS) 1942 whitelist_reg_ext(w, 1943 RING_CTX_TIMESTAMP(engine->mmio_base), 1944 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1945 } 1946 1947 static void cml_whitelist_build(struct intel_engine_cs *engine) 1948 { 1949 allow_read_ctx_timestamp(engine); 1950 1951 cfl_whitelist_build(engine); 1952 } 1953 1954 static void icl_whitelist_build(struct intel_engine_cs *engine) 1955 { 1956 struct i915_wa_list *w = &engine->whitelist; 1957 1958 allow_read_ctx_timestamp(engine); 1959 1960 switch (engine->class) { 1961 case RENDER_CLASS: 1962 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1963 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1964 1965 /* WaAllowUMDToModifySamplerMode:icl */ 1966 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 1967 1968 /* WaEnableStateCacheRedirectToCS:icl */ 1969 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1970 1971 /* 1972 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1973 * 1974 * This covers 4 register which are next to one another : 1975 * - PS_INVOCATION_COUNT 1976 * - PS_INVOCATION_COUNT_UDW 1977 * - PS_DEPTH_COUNT 1978 * - PS_DEPTH_COUNT_UDW 1979 */ 1980 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1981 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1982 RING_FORCE_TO_NONPRIV_RANGE_4); 1983 break; 1984 1985 case VIDEO_DECODE_CLASS: 1986 /* hucStatusRegOffset */ 1987 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1988 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1989 /* hucUKernelHdrInfoRegOffset */ 1990 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1991 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1992 /* hucStatus2RegOffset */ 1993 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1994 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1995 break; 1996 1997 default: 1998 break; 1999 } 2000 } 2001 2002 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2003 { 2004 struct i915_wa_list *w = &engine->whitelist; 2005 2006 allow_read_ctx_timestamp(engine); 2007 2008 switch (engine->class) { 2009 case RENDER_CLASS: 2010 /* 2011 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2012 * Wa_1408556865:tgl 2013 * 2014 * This covers 4 registers which are next to one another : 2015 * - PS_INVOCATION_COUNT 2016 * - PS_INVOCATION_COUNT_UDW 2017 * - PS_DEPTH_COUNT 2018 * - PS_DEPTH_COUNT_UDW 2019 */ 2020 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2021 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2022 RING_FORCE_TO_NONPRIV_RANGE_4); 2023 2024 /* 2025 * Wa_1808121037:tgl 2026 * Wa_14012131227:dg1 2027 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2028 */ 2029 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2030 2031 /* Wa_1806527549:tgl */ 2032 whitelist_reg(w, HIZ_CHICKEN); 2033 2034 /* Required by recommended tuning setting (not a workaround) */ 2035 whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3); 2036 2037 break; 2038 default: 2039 break; 2040 } 2041 } 2042 2043 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2044 { 2045 struct i915_wa_list *w = &engine->whitelist; 2046 2047 switch (engine->class) { 2048 case RENDER_CLASS: 2049 /* Required by recommended tuning setting (not a workaround) */ 2050 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); 2051 2052 break; 2053 default: 2054 break; 2055 } 2056 } 2057 2058 static void xelpg_whitelist_build(struct intel_engine_cs *engine) 2059 { 2060 struct i915_wa_list *w = &engine->whitelist; 2061 2062 switch (engine->class) { 2063 case RENDER_CLASS: 2064 /* Required by recommended tuning setting (not a workaround) */ 2065 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); 2066 2067 break; 2068 default: 2069 break; 2070 } 2071 } 2072 2073 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2074 { 2075 struct drm_i915_private *i915 = engine->i915; 2076 struct i915_wa_list *w = &engine->whitelist; 2077 2078 wa_init_start(w, engine->gt, "whitelist", engine->name); 2079 2080 if (engine->gt->type == GT_MEDIA) 2081 ; /* none yet */ 2082 else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) 2083 xelpg_whitelist_build(engine); 2084 else if (IS_DG2(i915)) 2085 dg2_whitelist_build(engine); 2086 else if (GRAPHICS_VER(i915) == 12) 2087 tgl_whitelist_build(engine); 2088 else if (GRAPHICS_VER(i915) == 11) 2089 icl_whitelist_build(engine); 2090 else if (IS_COMETLAKE(i915)) 2091 cml_whitelist_build(engine); 2092 else if (IS_COFFEELAKE(i915)) 2093 cfl_whitelist_build(engine); 2094 else if (IS_GEMINILAKE(i915)) 2095 glk_whitelist_build(engine); 2096 else if (IS_KABYLAKE(i915)) 2097 kbl_whitelist_build(engine); 2098 else if (IS_BROXTON(i915)) 2099 bxt_whitelist_build(engine); 2100 else if (IS_SKYLAKE(i915)) 2101 skl_whitelist_build(engine); 2102 else if (GRAPHICS_VER(i915) <= 8) 2103 ; 2104 else 2105 MISSING_CASE(GRAPHICS_VER(i915)); 2106 2107 wa_init_finish(w); 2108 } 2109 2110 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2111 { 2112 const struct i915_wa_list *wal = &engine->whitelist; 2113 struct intel_uncore *uncore = engine->uncore; 2114 const u32 base = engine->mmio_base; 2115 struct i915_wa *wa; 2116 unsigned int i; 2117 2118 if (!wal->count) 2119 return; 2120 2121 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2122 intel_uncore_write(uncore, 2123 RING_FORCE_TO_NONPRIV(base, i), 2124 i915_mmio_reg_offset(wa->reg)); 2125 2126 /* And clear the rest just in case of garbage */ 2127 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2128 intel_uncore_write(uncore, 2129 RING_FORCE_TO_NONPRIV(base, i), 2130 i915_mmio_reg_offset(RING_NOPID(base))); 2131 } 2132 2133 /* 2134 * engine_fake_wa_init(), a place holder to program the registers 2135 * which are not part of an official workaround defined by the 2136 * hardware team. 2137 * Adding programming of those register inside workaround will 2138 * allow utilizing wa framework to proper application and verification. 2139 */ 2140 static void 2141 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2142 { 2143 u8 mocs_w, mocs_r; 2144 2145 /* 2146 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2147 * by the command streamer when executing commands that don't have 2148 * a way to explicitly specify a MOCS setting. The default should 2149 * usually reference whichever MOCS entry corresponds to uncached 2150 * behavior, although use of a WB cached entry is recommended by the 2151 * spec in certain circumstances on specific platforms. 2152 */ 2153 if (GRAPHICS_VER(engine->i915) >= 12) { 2154 mocs_r = engine->gt->mocs.uc_index; 2155 mocs_w = engine->gt->mocs.uc_index; 2156 2157 if (HAS_L3_CCS_READ(engine->i915) && 2158 engine->class == COMPUTE_CLASS) { 2159 mocs_r = engine->gt->mocs.wb_index; 2160 2161 /* 2162 * Even on the few platforms where MOCS 0 is a 2163 * legitimate table entry, it's never the correct 2164 * setting to use here; we can assume the MOCS init 2165 * just forgot to initialize wb_index. 2166 */ 2167 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2168 } 2169 2170 wa_masked_field_set(wal, 2171 RING_CMD_CCTL(engine->mmio_base), 2172 CMD_CCTL_MOCS_MASK, 2173 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2174 } 2175 } 2176 2177 static void 2178 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2179 { 2180 struct drm_i915_private *i915 = engine->i915; 2181 struct intel_gt *gt = engine->gt; 2182 2183 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2184 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { 2185 /* Wa_22014600077 */ 2186 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2187 ENABLE_EU_COUNT_FOR_TDL_FLUSH); 2188 } 2189 2190 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2191 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2192 IS_DG2(i915)) { 2193 /* Wa_1509727124 */ 2194 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2195 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2196 } 2197 2198 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2199 IS_DG2(i915)) { 2200 /* Wa_22012856258 */ 2201 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2202 GEN12_DISABLE_READ_SUPPRESSION); 2203 } 2204 2205 if (IS_DG2(i915)) { 2206 /* 2207 * Wa_22010960976:dg2 2208 * Wa_14013347512:dg2 2209 */ 2210 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2211 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2212 } 2213 2214 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || 2215 IS_DG2(i915)) { 2216 /* Wa_14015150844 */ 2217 wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0, 2218 _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), 2219 0, true); 2220 } 2221 2222 if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2223 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2224 /* 2225 * Wa_1606700617:tgl,dg1,adl-p 2226 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2227 * Wa_14010826681:tgl,dg1,rkl,adl-p 2228 * Wa_18019627453:dg2 2229 */ 2230 wa_masked_en(wal, 2231 GEN9_CS_DEBUG_MODE1, 2232 FF_DOP_CLOCK_GATE_DISABLE); 2233 } 2234 2235 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2236 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2237 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2238 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2239 2240 /* 2241 * Wa_1407928979:tgl A* 2242 * Wa_18011464164:tgl[B0+],dg1[B0+] 2243 * Wa_22010931296:tgl[B0+],dg1[B0+] 2244 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2245 */ 2246 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2247 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2248 2249 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2250 wa_mcr_masked_en(wal, 2251 GEN10_SAMPLER_MODE, 2252 ENABLE_SMALLPL); 2253 } 2254 2255 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2256 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2257 /* Wa_1409804808 */ 2258 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2259 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2260 2261 /* Wa_14010229206 */ 2262 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2263 } 2264 2265 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2266 /* 2267 * Wa_1607297627 2268 * 2269 * On TGL and RKL there are multiple entries for this WA in the 2270 * BSpec; some indicate this is an A0-only WA, others indicate 2271 * it applies to all steppings so we trust the "all steppings." 2272 */ 2273 wa_masked_en(wal, 2274 RING_PSMI_CTL(RENDER_RING_BASE), 2275 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2276 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2277 } 2278 2279 if (GRAPHICS_VER(i915) == 11) { 2280 /* This is not an Wa. Enable for better image quality */ 2281 wa_masked_en(wal, 2282 _3D_CHICKEN3, 2283 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2284 2285 /* 2286 * Wa_1405543622:icl 2287 * Formerly known as WaGAPZPriorityScheme 2288 */ 2289 wa_write_or(wal, 2290 GEN8_GARBCNTL, 2291 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2292 2293 /* 2294 * Wa_1604223664:icl 2295 * Formerly known as WaL3BankAddressHashing 2296 */ 2297 wa_write_clr_set(wal, 2298 GEN8_GARBCNTL, 2299 GEN11_HASH_CTRL_EXCL_MASK, 2300 GEN11_HASH_CTRL_EXCL_BIT0); 2301 wa_write_clr_set(wal, 2302 GEN11_GLBLINVL, 2303 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2304 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2305 2306 /* 2307 * Wa_1405733216:icl 2308 * Formerly known as WaDisableCleanEvicts 2309 */ 2310 wa_mcr_write_or(wal, 2311 GEN8_L3SQCREG4, 2312 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2313 2314 /* Wa_1606682166:icl */ 2315 wa_write_or(wal, 2316 GEN7_SARCHKMD, 2317 GEN7_DISABLE_SAMPLER_PREFETCH); 2318 2319 /* Wa_1409178092:icl */ 2320 wa_mcr_write_clr_set(wal, 2321 GEN11_SCRATCH2, 2322 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2323 0); 2324 2325 /* WaEnable32PlaneMode:icl */ 2326 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2327 GEN11_ENABLE_32_PLANE_MODE); 2328 2329 /* 2330 * Wa_1408767742:icl[a2..forever],ehl[all] 2331 * Wa_1605460711:icl[a0..c0] 2332 */ 2333 wa_write_or(wal, 2334 GEN7_FF_THREAD_MODE, 2335 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2336 2337 /* Wa_22010271021 */ 2338 wa_masked_en(wal, 2339 GEN9_CS_DEBUG_MODE1, 2340 FF_DOP_CLOCK_GATE_DISABLE); 2341 } 2342 2343 /* 2344 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2345 * beyond) allow the kernel-mode driver to choose between two different 2346 * options for controlling preemption granularity and behavior. 2347 * 2348 * Option 1 (hardware default): 2349 * Preemption settings are controlled in a global manner via 2350 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2351 * and settings chosen by the kernel-mode driver will apply to all 2352 * userspace clients. 2353 * 2354 * Option 2: 2355 * Preemption settings are controlled on a per-context basis via 2356 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2357 * context switch and is writable by userspace (e.g., via 2358 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2359 * which allows different userspace drivers/clients to select 2360 * different settings, or to change those settings on the fly in 2361 * response to runtime needs. This option was known by name 2362 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2363 * that name is somewhat misleading as other non-granularity 2364 * preemption settings are also impacted by this decision. 2365 * 2366 * On Linux, our policy has always been to let userspace drivers 2367 * control preemption granularity/settings (Option 2). This was 2368 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2369 * userspace developed before object-level preemption was enabled would 2370 * not behave well if i915 were to go with Option 1 and enable that 2371 * preemption in a global manner). On gen9 each context would have 2372 * object-level preemption disabled by default (see 2373 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2374 * userspace drivers could opt-in to object-level preemption as they 2375 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2376 * even though it is no longer necessary for ABI compatibility when 2377 * enabling a new platform, it does ensure that userspace will be able 2378 * to implement any workarounds that show up requiring temporary 2379 * adjustments to preemption behavior at runtime. 2380 * 2381 * Notes/Workarounds: 2382 * - Wa_14015141709: On DG2 and early steppings of MTL, 2383 * CS_CHICKEN1[0] does not disable object-level preemption as 2384 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2385 * using Option 1). Effectively this means userspace is unable 2386 * to disable object-level preemption on these platforms/steppings 2387 * despite the setting here. 2388 * 2389 * - Wa_16013994831: May require that userspace program 2390 * CS_CHICKEN1[10] when certain runtime conditions are true. 2391 * Userspace requires Option 2 to be in effect for their update of 2392 * CS_CHICKEN1[10] to be effective. 2393 * 2394 * Other workarounds may appear in the future that will also require 2395 * Option 2 behavior to allow proper userspace implementation. 2396 */ 2397 if (GRAPHICS_VER(i915) >= 9) 2398 wa_masked_en(wal, 2399 GEN7_FF_SLICE_CS_CHICKEN1, 2400 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2401 2402 if (IS_SKYLAKE(i915) || 2403 IS_KABYLAKE(i915) || 2404 IS_COFFEELAKE(i915) || 2405 IS_COMETLAKE(i915)) { 2406 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2407 wa_write_or(wal, 2408 GEN8_GARBCNTL, 2409 GEN9_GAPS_TSV_CREDIT_DISABLE); 2410 } 2411 2412 if (IS_BROXTON(i915)) { 2413 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2414 wa_masked_en(wal, 2415 FF_SLICE_CS_CHICKEN2, 2416 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2417 } 2418 2419 if (GRAPHICS_VER(i915) == 9) { 2420 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2421 wa_masked_en(wal, 2422 GEN9_CSFE_CHICKEN1_RCS, 2423 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2424 2425 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2426 wa_mcr_write_or(wal, 2427 BDW_SCRATCH1, 2428 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2429 2430 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2431 if (IS_GEN9_LP(i915)) 2432 wa_mcr_write_clr_set(wal, 2433 GEN8_L3SQCREG1, 2434 L3_PRIO_CREDITS_MASK, 2435 L3_GENERAL_PRIO_CREDITS(62) | 2436 L3_HIGH_PRIO_CREDITS(2)); 2437 2438 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2439 wa_mcr_write_or(wal, 2440 GEN8_L3SQCREG4, 2441 GEN8_LQSC_FLUSH_COHERENT_LINES); 2442 2443 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2444 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2445 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2446 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2447 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2448 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2449 EVICTION_PERF_FIX_ENABLE, 0); 2450 } 2451 2452 if (IS_HASWELL(i915)) { 2453 /* WaSampleCChickenBitEnable:hsw */ 2454 wa_masked_en(wal, 2455 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2456 2457 wa_masked_dis(wal, 2458 CACHE_MODE_0_GEN7, 2459 /* enable HiZ Raw Stall Optimization */ 2460 HIZ_RAW_STALL_OPT_DISABLE); 2461 } 2462 2463 if (IS_VALLEYVIEW(i915)) { 2464 /* WaDisableEarlyCull:vlv */ 2465 wa_masked_en(wal, 2466 _3D_CHICKEN3, 2467 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2468 2469 /* 2470 * WaVSThreadDispatchOverride:ivb,vlv 2471 * 2472 * This actually overrides the dispatch 2473 * mode for all thread types. 2474 */ 2475 wa_write_clr_set(wal, 2476 GEN7_FF_THREAD_MODE, 2477 GEN7_FF_SCHED_MASK, 2478 GEN7_FF_TS_SCHED_HW | 2479 GEN7_FF_VS_SCHED_HW | 2480 GEN7_FF_DS_SCHED_HW); 2481 2482 /* WaPsdDispatchEnable:vlv */ 2483 /* WaDisablePSDDualDispatchEnable:vlv */ 2484 wa_masked_en(wal, 2485 GEN7_HALF_SLICE_CHICKEN1, 2486 GEN7_MAX_PS_THREAD_DEP | 2487 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2488 } 2489 2490 if (IS_IVYBRIDGE(i915)) { 2491 /* WaDisableEarlyCull:ivb */ 2492 wa_masked_en(wal, 2493 _3D_CHICKEN3, 2494 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2495 2496 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2497 /* enable HiZ Raw Stall Optimization */ 2498 wa_masked_dis(wal, 2499 CACHE_MODE_0_GEN7, 2500 HIZ_RAW_STALL_OPT_DISABLE); 2501 } 2502 2503 /* 2504 * WaVSThreadDispatchOverride:ivb,vlv 2505 * 2506 * This actually overrides the dispatch 2507 * mode for all thread types. 2508 */ 2509 wa_write_clr_set(wal, 2510 GEN7_FF_THREAD_MODE, 2511 GEN7_FF_SCHED_MASK, 2512 GEN7_FF_TS_SCHED_HW | 2513 GEN7_FF_VS_SCHED_HW | 2514 GEN7_FF_DS_SCHED_HW); 2515 2516 /* WaDisablePSDDualDispatchEnable:ivb */ 2517 if (IS_IVB_GT1(i915)) 2518 wa_masked_en(wal, 2519 GEN7_HALF_SLICE_CHICKEN1, 2520 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2521 } 2522 2523 if (GRAPHICS_VER(i915) == 7) { 2524 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2525 wa_masked_en(wal, 2526 RING_MODE_GEN7(RENDER_RING_BASE), 2527 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2528 2529 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2530 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2531 2532 /* 2533 * BSpec says this must be set, even though 2534 * WaDisable4x2SubspanOptimization:ivb,hsw 2535 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2536 */ 2537 wa_masked_en(wal, 2538 CACHE_MODE_1, 2539 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2540 2541 /* 2542 * BSpec recommends 8x4 when MSAA is used, 2543 * however in practice 16x4 seems fastest. 2544 * 2545 * Note that PS/WM thread counts depend on the WIZ hashing 2546 * disable bit, which we don't touch here, but it's good 2547 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2548 */ 2549 wa_masked_field_set(wal, 2550 GEN7_GT_MODE, 2551 GEN6_WIZ_HASHING_MASK, 2552 GEN6_WIZ_HASHING_16x4); 2553 } 2554 2555 if (IS_GRAPHICS_VER(i915, 6, 7)) 2556 /* 2557 * We need to disable the AsyncFlip performance optimisations in 2558 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2559 * already be programmed to '1' on all products. 2560 * 2561 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2562 */ 2563 wa_masked_en(wal, 2564 RING_MI_MODE(RENDER_RING_BASE), 2565 ASYNC_FLIP_PERF_DISABLE); 2566 2567 if (GRAPHICS_VER(i915) == 6) { 2568 /* 2569 * Required for the hardware to program scanline values for 2570 * waiting 2571 * WaEnableFlushTlbInvalidationMode:snb 2572 */ 2573 wa_masked_en(wal, 2574 GFX_MODE, 2575 GFX_TLB_INVALIDATE_EXPLICIT); 2576 2577 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2578 wa_masked_en(wal, 2579 _3D_CHICKEN, 2580 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2581 2582 wa_masked_en(wal, 2583 _3D_CHICKEN3, 2584 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2585 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2586 /* 2587 * Bspec says: 2588 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2589 * to normal and 3DSTATE_SF number of SF output attributes 2590 * is more than 16." 2591 */ 2592 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2593 2594 /* 2595 * BSpec recommends 8x4 when MSAA is used, 2596 * however in practice 16x4 seems fastest. 2597 * 2598 * Note that PS/WM thread counts depend on the WIZ hashing 2599 * disable bit, which we don't touch here, but it's good 2600 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2601 */ 2602 wa_masked_field_set(wal, 2603 GEN6_GT_MODE, 2604 GEN6_WIZ_HASHING_MASK, 2605 GEN6_WIZ_HASHING_16x4); 2606 2607 /* WaDisable_RenderCache_OperationalFlush:snb */ 2608 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2609 2610 /* 2611 * From the Sandybridge PRM, volume 1 part 3, page 24: 2612 * "If this bit is set, STCunit will have LRA as replacement 2613 * policy. [...] This bit must be reset. LRA replacement 2614 * policy is not supported." 2615 */ 2616 wa_masked_dis(wal, 2617 CACHE_MODE_0, 2618 CM0_STC_EVICT_DISABLE_LRA_SNB); 2619 } 2620 2621 if (IS_GRAPHICS_VER(i915, 4, 6)) 2622 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2623 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2624 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2625 /* XXX bit doesn't stick on Broadwater */ 2626 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2627 2628 if (GRAPHICS_VER(i915) == 4) 2629 /* 2630 * Disable CONSTANT_BUFFER before it is loaded from the context 2631 * image. For as it is loaded, it is executed and the stored 2632 * address may no longer be valid, leading to a GPU hang. 2633 * 2634 * This imposes the requirement that userspace reload their 2635 * CONSTANT_BUFFER on every batch, fortunately a requirement 2636 * they are already accustomed to from before contexts were 2637 * enabled. 2638 */ 2639 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2640 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2641 0 /* XXX bit doesn't stick on Broadwater */, 2642 true); 2643 } 2644 2645 static void 2646 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2647 { 2648 struct drm_i915_private *i915 = engine->i915; 2649 2650 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2651 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2652 wa_write(wal, 2653 RING_SEMA_WAIT_POLL(engine->mmio_base), 2654 1); 2655 } 2656 /* Wa_16018031267, Wa_16018063123 */ 2657 if (NEEDS_FASTCOLOR_BLT_WABB(engine)) 2658 wa_masked_field_set(wal, ECOSKPD(engine->mmio_base), 2659 XEHP_BLITTER_SCHEDULING_MODE_MASK, 2660 XEHP_BLITTER_ROUND_ROBIN_MODE); 2661 } 2662 2663 static void 2664 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2665 { 2666 /* boilerplate for any CCS engine workaround */ 2667 } 2668 2669 /* 2670 * The bspec performance guide has recommended MMIO tuning settings. These 2671 * aren't truly "workarounds" but we want to program them with the same 2672 * workaround infrastructure to ensure that they're automatically added to 2673 * the GuC save/restore lists, re-applied at the right times, and checked for 2674 * any conflicting programming requested by real workarounds. 2675 * 2676 * Programming settings should be added here only if their registers are not 2677 * part of an engine's register state context. If a register is part of a 2678 * context, then any tuning settings should be programmed in an appropriate 2679 * function invoked by __intel_engine_init_ctx_wa(). 2680 */ 2681 static void 2682 add_render_compute_tuning_settings(struct intel_gt *gt, 2683 struct i915_wa_list *wal) 2684 { 2685 struct drm_i915_private *i915 = gt->i915; 2686 2687 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915)) 2688 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2689 2690 /* 2691 * This tuning setting proves beneficial only on ATS-M designs; the 2692 * default "age based" setting is optimal on regular DG2 and other 2693 * platforms. 2694 */ 2695 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2696 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2697 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2698 2699 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55)) 2700 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); 2701 } 2702 2703 static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2704 { 2705 struct intel_gt *gt = engine->gt; 2706 2707 if (!IS_DG2(gt->i915)) 2708 return; 2709 2710 /* 2711 * Wa_14019159160: This workaround, along with others, leads to 2712 * significant challenges in utilizing load balancing among the 2713 * CCS slices. Consequently, an architectural decision has been 2714 * made to completely disable automatic CCS load balancing. 2715 */ 2716 wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); 2717 2718 /* 2719 * After having disabled automatic load balancing we need to 2720 * assign all slices to a single CCS. We will call it CCS mode 1 2721 */ 2722 intel_gt_apply_ccs_mode(gt); 2723 } 2724 2725 /* 2726 * The workarounds in this function apply to shared registers in 2727 * the general render reset domain that aren't tied to a 2728 * specific engine. Since all render+compute engines get reset 2729 * together, and the contents of these registers are lost during 2730 * the shared render domain reset, we'll define such workarounds 2731 * here and then add them to just a single RCS or CCS engine's 2732 * workaround list (whichever engine has the XXXX flag). 2733 */ 2734 static void 2735 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2736 { 2737 struct drm_i915_private *i915 = engine->i915; 2738 struct intel_gt *gt = engine->gt; 2739 2740 add_render_compute_tuning_settings(gt, wal); 2741 2742 if (GRAPHICS_VER(i915) >= 11) { 2743 /* This is not a Wa (although referred to as 2744 * WaSetInidrectStateOverride in places), this allows 2745 * applications that reference sampler states through 2746 * the BindlessSamplerStateBaseAddress to have their 2747 * border color relative to DynamicStateBaseAddress 2748 * rather than BindlessSamplerStateBaseAddress. 2749 * 2750 * Otherwise SAMPLER_STATE border colors have to be 2751 * copied in multiple heaps (DynamicStateBaseAddress & 2752 * BindlessSamplerStateBaseAddress) 2753 * 2754 * BSpec: 46052 2755 */ 2756 wa_mcr_masked_en(wal, 2757 GEN10_SAMPLER_MODE, 2758 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); 2759 } 2760 2761 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) || 2762 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) || 2763 IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74))) 2764 /* Wa_14017856879 */ 2765 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); 2766 2767 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2768 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) 2769 /* 2770 * Wa_14017066071 2771 * Wa_14017654203 2772 */ 2773 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2774 MTL_DISABLE_SAMPLER_SC_OOO); 2775 2776 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) 2777 /* Wa_22015279794 */ 2778 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2779 DISABLE_PREFETCH_INTO_IC); 2780 2781 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2782 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2783 IS_DG2(i915)) { 2784 /* Wa_22013037850 */ 2785 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2786 DISABLE_128B_EVICTION_COMMAND_UDW); 2787 2788 /* Wa_18017747507 */ 2789 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 2790 } 2791 2792 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2793 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2794 IS_DG2(i915)) { 2795 /* Wa_22014226127 */ 2796 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2797 } 2798 2799 if (IS_DG2(i915)) { 2800 /* Wa_14015227452:dg2,pvc */ 2801 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2802 2803 /* Wa_16015675438:dg2,pvc */ 2804 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2805 2806 /* 2807 * Wa_16011620976:dg2_g11 2808 * Wa_22015475538:dg2 2809 */ 2810 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2811 2812 /* Wa_18028616096 */ 2813 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); 2814 } 2815 2816 if (IS_DG2_G11(i915)) { 2817 /* 2818 * Wa_22012826095:dg2 2819 * Wa_22013059131:dg2 2820 */ 2821 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2822 MAXREQS_PER_BANK, 2823 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2824 2825 /* Wa_22013059131:dg2 */ 2826 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2827 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2828 2829 /* 2830 * Wa_22012654132 2831 * 2832 * Note that register 0xE420 is write-only and cannot be read 2833 * back for verification on DG2 (due to Wa_14012342262), so 2834 * we need to explicitly skip the readback. 2835 */ 2836 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2837 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2838 0 /* write-only, so skip validation */, 2839 true); 2840 } 2841 } 2842 2843 static void 2844 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2845 { 2846 if (GRAPHICS_VER(engine->i915) < 4) 2847 return; 2848 2849 engine_fake_wa_init(engine, wal); 2850 2851 /* 2852 * These are common workarounds that just need to applied 2853 * to a single RCS/CCS engine's workaround list since 2854 * they're reset as part of the general render domain reset. 2855 */ 2856 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) { 2857 general_render_compute_wa_init(engine, wal); 2858 ccs_engine_wa_mode(engine, wal); 2859 } 2860 2861 if (engine->class == COMPUTE_CLASS) 2862 ccs_engine_wa_init(engine, wal); 2863 else if (engine->class == RENDER_CLASS) 2864 rcs_engine_wa_init(engine, wal); 2865 else 2866 xcs_engine_wa_init(engine, wal); 2867 } 2868 2869 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2870 { 2871 struct i915_wa_list *wal = &engine->wa_list; 2872 2873 wa_init_start(wal, engine->gt, "engine", engine->name); 2874 engine_init_workarounds(engine, wal); 2875 wa_init_finish(wal); 2876 } 2877 2878 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2879 { 2880 wa_list_apply(&engine->wa_list); 2881 } 2882 2883 static const struct i915_range mcr_ranges_gen8[] = { 2884 { .start = 0x5500, .end = 0x55ff }, 2885 { .start = 0x7000, .end = 0x7fff }, 2886 { .start = 0x9400, .end = 0x97ff }, 2887 { .start = 0xb000, .end = 0xb3ff }, 2888 { .start = 0xe000, .end = 0xe7ff }, 2889 {}, 2890 }; 2891 2892 static const struct i915_range mcr_ranges_gen12[] = { 2893 { .start = 0x8150, .end = 0x815f }, 2894 { .start = 0x9520, .end = 0x955f }, 2895 { .start = 0xb100, .end = 0xb3ff }, 2896 { .start = 0xde80, .end = 0xe8ff }, 2897 { .start = 0x24a00, .end = 0x24a7f }, 2898 {}, 2899 }; 2900 2901 static const struct i915_range mcr_ranges_xehp[] = { 2902 { .start = 0x4000, .end = 0x4aff }, 2903 { .start = 0x5200, .end = 0x52ff }, 2904 { .start = 0x5400, .end = 0x7fff }, 2905 { .start = 0x8140, .end = 0x815f }, 2906 { .start = 0x8c80, .end = 0x8dff }, 2907 { .start = 0x94d0, .end = 0x955f }, 2908 { .start = 0x9680, .end = 0x96ff }, 2909 { .start = 0xb000, .end = 0xb3ff }, 2910 { .start = 0xc800, .end = 0xcfff }, 2911 { .start = 0xd800, .end = 0xd8ff }, 2912 { .start = 0xdc00, .end = 0xffff }, 2913 { .start = 0x17000, .end = 0x17fff }, 2914 { .start = 0x24a00, .end = 0x24a7f }, 2915 {}, 2916 }; 2917 2918 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2919 { 2920 const struct i915_range *mcr_ranges; 2921 int i; 2922 2923 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) 2924 mcr_ranges = mcr_ranges_xehp; 2925 else if (GRAPHICS_VER(i915) >= 12) 2926 mcr_ranges = mcr_ranges_gen12; 2927 else if (GRAPHICS_VER(i915) >= 8) 2928 mcr_ranges = mcr_ranges_gen8; 2929 else 2930 return false; 2931 2932 /* 2933 * Registers in these ranges are affected by the MCR selector 2934 * which only controls CPU initiated MMIO. Routing does not 2935 * work for CS access so we cannot verify them on this path. 2936 */ 2937 for (i = 0; mcr_ranges[i].start; i++) 2938 if (offset >= mcr_ranges[i].start && 2939 offset <= mcr_ranges[i].end) 2940 return true; 2941 2942 return false; 2943 } 2944 2945 static int 2946 wa_list_srm(struct i915_request *rq, 2947 const struct i915_wa_list *wal, 2948 struct i915_vma *vma) 2949 { 2950 struct drm_i915_private *i915 = rq->i915; 2951 unsigned int i, count = 0; 2952 const struct i915_wa *wa; 2953 u32 srm, *cs; 2954 2955 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2956 if (GRAPHICS_VER(i915) >= 8) 2957 srm++; 2958 2959 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2960 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2961 count++; 2962 } 2963 2964 cs = intel_ring_begin(rq, 4 * count); 2965 if (IS_ERR(cs)) 2966 return PTR_ERR(cs); 2967 2968 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2969 u32 offset = i915_mmio_reg_offset(wa->reg); 2970 2971 if (mcr_range(i915, offset)) 2972 continue; 2973 2974 *cs++ = srm; 2975 *cs++ = offset; 2976 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2977 *cs++ = 0; 2978 } 2979 intel_ring_advance(rq, cs); 2980 2981 return 0; 2982 } 2983 2984 static int engine_wa_list_verify(struct intel_context *ce, 2985 const struct i915_wa_list * const wal, 2986 const char *from) 2987 { 2988 const struct i915_wa *wa; 2989 struct i915_request *rq; 2990 struct i915_vma *vma; 2991 struct i915_gem_ww_ctx ww; 2992 unsigned int i; 2993 u32 *results; 2994 int err; 2995 2996 if (!wal->count) 2997 return 0; 2998 2999 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3000 wal->count * sizeof(u32)); 3001 if (IS_ERR(vma)) 3002 return PTR_ERR(vma); 3003 3004 intel_engine_pm_get(ce->engine); 3005 i915_gem_ww_ctx_init(&ww, false); 3006 retry: 3007 err = i915_gem_object_lock(vma->obj, &ww); 3008 if (err == 0) 3009 err = intel_context_pin_ww(ce, &ww); 3010 if (err) 3011 goto err_pm; 3012 3013 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3014 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3015 if (err) 3016 goto err_unpin; 3017 3018 rq = i915_request_create(ce); 3019 if (IS_ERR(rq)) { 3020 err = PTR_ERR(rq); 3021 goto err_vma; 3022 } 3023 3024 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3025 if (err == 0) 3026 err = wa_list_srm(rq, wal, vma); 3027 3028 i915_request_get(rq); 3029 if (err) 3030 i915_request_set_error_once(rq, err); 3031 i915_request_add(rq); 3032 3033 if (err) 3034 goto err_rq; 3035 3036 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3037 err = -ETIME; 3038 goto err_rq; 3039 } 3040 3041 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3042 if (IS_ERR(results)) { 3043 err = PTR_ERR(results); 3044 goto err_rq; 3045 } 3046 3047 err = 0; 3048 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3049 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) 3050 continue; 3051 3052 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3053 err = -ENXIO; 3054 } 3055 3056 i915_gem_object_unpin_map(vma->obj); 3057 3058 err_rq: 3059 i915_request_put(rq); 3060 err_vma: 3061 i915_vma_unpin(vma); 3062 err_unpin: 3063 intel_context_unpin(ce); 3064 err_pm: 3065 if (err == -EDEADLK) { 3066 err = i915_gem_ww_ctx_backoff(&ww); 3067 if (!err) 3068 goto retry; 3069 } 3070 i915_gem_ww_ctx_fini(&ww); 3071 intel_engine_pm_put(ce->engine); 3072 i915_vma_put(vma); 3073 return err; 3074 } 3075 3076 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3077 const char *from) 3078 { 3079 return engine_wa_list_verify(engine->kernel_context, 3080 &engine->wa_list, 3081 from); 3082 } 3083 3084 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3085 #include "selftest_workarounds.c" 3086 #endif 3087