1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gpu_commands.h" 11 #include "intel_gt.h" 12 #include "intel_ring.h" 13 #include "intel_workarounds.h" 14 15 /** 16 * DOC: Hardware workarounds 17 * 18 * This file is intended as a central place to implement most [1]_ of the 19 * required workarounds for hardware to work as originally intended. They fall 20 * in five basic categories depending on how/when they are applied: 21 * 22 * - Workarounds that touch registers that are saved/restored to/from the HW 23 * context image. The list is emitted (via Load Register Immediate commands) 24 * everytime a new context is created. 25 * - GT workarounds. The list of these WAs is applied whenever these registers 26 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 27 * - Display workarounds. The list is applied during display clock-gating 28 * initialization. 29 * - Workarounds that whitelist a privileged register, so that UMDs can manage 30 * them directly. This is just a special case of a MMMIO workaround (as we 31 * write the list of these to/be-whitelisted registers to some special HW 32 * registers). 33 * - Workaround batchbuffers, that get executed automatically by the hardware 34 * on every HW context restore. 35 * 36 * .. [1] Please notice that there are other WAs that, due to their nature, 37 * cannot be applied from a central place. Those are peppered around the rest 38 * of the code, as needed. 39 * 40 * .. [2] Technically, some registers are powercontext saved & restored, so they 41 * survive a suspend/resume. In practice, writing them again is not too 42 * costly and simplifies things. We can revisit this in the future. 43 * 44 * Layout 45 * ~~~~~~ 46 * 47 * Keep things in this file ordered by WA type, as per the above (context, GT, 48 * display, register whitelist, batchbuffer). Then, inside each type, keep the 49 * following order: 50 * 51 * - Infrastructure functions and macros 52 * - WAs per platform in standard gen/chrono order 53 * - Public functions to init or apply the given workaround type. 54 */ 55 56 /* 57 * KBL revision ID ordering is bizarre; higher revision ID's map to lower 58 * steppings in some cases. So rather than test against the revision ID 59 * directly, let's map that into our own range of increasing ID's that we 60 * can test against in a regular manner. 61 */ 62 63 const struct i915_rev_steppings kbl_revids[] = { 64 [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 }, 65 [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 }, 66 [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 }, 67 [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 }, 68 [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 }, 69 [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 }, 70 [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 }, 71 [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 }, 72 }; 73 74 const struct i915_rev_steppings tgl_uy_revids[] = { 75 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 }, 76 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 }, 77 [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 }, 78 [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 }, 79 }; 80 81 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ 82 const struct i915_rev_steppings tgl_revids[] = { 83 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 }, 84 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 }, 85 }; 86 87 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 88 { 89 wal->name = name; 90 wal->engine_name = engine_name; 91 } 92 93 #define WA_LIST_CHUNK (1 << 4) 94 95 static void wa_init_finish(struct i915_wa_list *wal) 96 { 97 /* Trim unused entries. */ 98 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 99 struct i915_wa *list = kmemdup(wal->list, 100 wal->count * sizeof(*list), 101 GFP_KERNEL); 102 103 if (list) { 104 kfree(wal->list); 105 wal->list = list; 106 } 107 } 108 109 if (!wal->count) 110 return; 111 112 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 113 wal->wa_count, wal->name, wal->engine_name); 114 } 115 116 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 117 { 118 unsigned int addr = i915_mmio_reg_offset(wa->reg); 119 unsigned int start = 0, end = wal->count; 120 const unsigned int grow = WA_LIST_CHUNK; 121 struct i915_wa *wa_; 122 123 GEM_BUG_ON(!is_power_of_2(grow)); 124 125 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 126 struct i915_wa *list; 127 128 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 129 GFP_KERNEL); 130 if (!list) { 131 DRM_ERROR("No space for workaround init!\n"); 132 return; 133 } 134 135 if (wal->list) { 136 memcpy(list, wal->list, sizeof(*wa) * wal->count); 137 kfree(wal->list); 138 } 139 140 wal->list = list; 141 } 142 143 while (start < end) { 144 unsigned int mid = start + (end - start) / 2; 145 146 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 147 start = mid + 1; 148 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 149 end = mid; 150 } else { 151 wa_ = &wal->list[mid]; 152 153 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 154 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 155 i915_mmio_reg_offset(wa_->reg), 156 wa_->clr, wa_->set); 157 158 wa_->set &= ~wa->clr; 159 } 160 161 wal->wa_count++; 162 wa_->set |= wa->set; 163 wa_->clr |= wa->clr; 164 wa_->read |= wa->read; 165 return; 166 } 167 } 168 169 wal->wa_count++; 170 wa_ = &wal->list[wal->count++]; 171 *wa_ = *wa; 172 173 while (wa_-- > wal->list) { 174 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 175 i915_mmio_reg_offset(wa_[1].reg)); 176 if (i915_mmio_reg_offset(wa_[1].reg) > 177 i915_mmio_reg_offset(wa_[0].reg)) 178 break; 179 180 swap(wa_[1], wa_[0]); 181 } 182 } 183 184 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 185 u32 clear, u32 set, u32 read_mask) 186 { 187 struct i915_wa wa = { 188 .reg = reg, 189 .clr = clear, 190 .set = set, 191 .read = read_mask, 192 }; 193 194 _wa_add(wal, &wa); 195 } 196 197 static void 198 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 199 { 200 wa_add(wal, reg, clear, set, clear); 201 } 202 203 static void 204 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 205 { 206 wa_write_clr_set(wal, reg, ~0, set); 207 } 208 209 static void 210 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 211 { 212 wa_write_clr_set(wal, reg, set, set); 213 } 214 215 static void 216 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 217 { 218 wa_write_clr_set(wal, reg, clr, 0); 219 } 220 221 /* 222 * WA operations on "masked register". A masked register has the upper 16 bits 223 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 224 * portion of the register without a rmw: you simply write in the upper 16 bits 225 * the mask of bits you are going to modify. 226 * 227 * The wa_masked_* family of functions already does the necessary operations to 228 * calculate the mask based on the parameters passed, so user only has to 229 * provide the lower 16 bits of that register. 230 */ 231 232 static void 233 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 234 { 235 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 236 } 237 238 static void 239 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 240 { 241 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 242 } 243 244 static void 245 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 246 u32 mask, u32 val) 247 { 248 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask); 249 } 250 251 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 252 struct i915_wa_list *wal) 253 { 254 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 255 } 256 257 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 258 struct i915_wa_list *wal) 259 { 260 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 261 } 262 263 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 264 struct i915_wa_list *wal) 265 { 266 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 267 268 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 269 wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE); 270 271 /* WaDisablePartialInstShootdown:bdw,chv */ 272 wa_masked_en(wal, GEN8_ROW_CHICKEN, 273 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 274 275 /* Use Force Non-Coherent whenever executing a 3D context. This is a 276 * workaround for for a possible hang in the unlikely event a TLB 277 * invalidation occurs during a PSD flush. 278 */ 279 /* WaForceEnableNonCoherent:bdw,chv */ 280 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 281 wa_masked_en(wal, HDC_CHICKEN0, 282 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 283 HDC_FORCE_NON_COHERENT); 284 285 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 286 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 287 * polygons in the same 8x4 pixel/sample area to be processed without 288 * stalling waiting for the earlier ones to write to Hierarchical Z 289 * buffer." 290 * 291 * This optimization is off by default for BDW and CHV; turn it on. 292 */ 293 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 294 295 /* Wa4x4STCOptimizationDisable:bdw,chv */ 296 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 297 298 /* 299 * BSpec recommends 8x4 when MSAA is used, 300 * however in practice 16x4 seems fastest. 301 * 302 * Note that PS/WM thread counts depend on the WIZ hashing 303 * disable bit, which we don't touch here, but it's good 304 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 305 */ 306 wa_masked_field_set(wal, GEN7_GT_MODE, 307 GEN6_WIZ_HASHING_MASK, 308 GEN6_WIZ_HASHING_16x4); 309 } 310 311 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 312 struct i915_wa_list *wal) 313 { 314 struct drm_i915_private *i915 = engine->i915; 315 316 gen8_ctx_workarounds_init(engine, wal); 317 318 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 319 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 320 321 /* WaDisableDopClockGating:bdw 322 * 323 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 324 * to disable EUTC clock gating. 325 */ 326 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 327 DOP_CLOCK_GATING_DISABLE); 328 329 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 330 GEN8_SAMPLER_POWER_BYPASS_DIS); 331 332 wa_masked_en(wal, HDC_CHICKEN0, 333 /* WaForceContextSaveRestoreNonCoherent:bdw */ 334 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 335 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 336 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 337 } 338 339 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 340 struct i915_wa_list *wal) 341 { 342 gen8_ctx_workarounds_init(engine, wal); 343 344 /* WaDisableThreadStallDopClockGating:chv */ 345 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 346 347 /* Improve HiZ throughput on CHV. */ 348 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 349 } 350 351 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 352 struct i915_wa_list *wal) 353 { 354 struct drm_i915_private *i915 = engine->i915; 355 356 if (HAS_LLC(i915)) { 357 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 358 * 359 * Must match Display Engine. See 360 * WaCompressedResourceDisplayNewHashMode. 361 */ 362 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 363 GEN9_PBE_COMPRESSED_HASH_SELECTION); 364 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 365 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 366 } 367 368 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 369 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 370 wa_masked_en(wal, GEN8_ROW_CHICKEN, 371 FLOW_CONTROL_ENABLE | 372 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 373 374 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 375 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 376 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 377 GEN9_ENABLE_YV12_BUGFIX | 378 GEN9_ENABLE_GPGPU_PREEMPTION); 379 380 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 381 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 382 wa_masked_en(wal, CACHE_MODE_1, 383 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 384 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 385 386 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 387 wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 388 GEN9_CCS_TLB_PREFETCH_ENABLE); 389 390 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 391 wa_masked_en(wal, HDC_CHICKEN0, 392 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 393 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 394 395 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 396 * both tied to WaForceContextSaveRestoreNonCoherent 397 * in some hsds for skl. We keep the tie for all gen9. The 398 * documentation is a bit hazy and so we want to get common behaviour, 399 * even though there is no clear evidence we would need both on kbl/bxt. 400 * This area has been source of system hangs so we play it safe 401 * and mimic the skl regardless of what bspec says. 402 * 403 * Use Force Non-Coherent whenever executing a 3D context. This 404 * is a workaround for a possible hang in the unlikely event 405 * a TLB invalidation occurs during a PSD flush. 406 */ 407 408 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 409 wa_masked_en(wal, HDC_CHICKEN0, 410 HDC_FORCE_NON_COHERENT); 411 412 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 413 if (IS_SKYLAKE(i915) || 414 IS_KABYLAKE(i915) || 415 IS_COFFEELAKE(i915) || 416 IS_COMETLAKE(i915)) 417 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 418 GEN8_SAMPLER_POWER_BYPASS_DIS); 419 420 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 421 wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 422 423 /* 424 * Supporting preemption with fine-granularity requires changes in the 425 * batch buffer programming. Since we can't break old userspace, we 426 * need to set our default preemption level to safe value. Userspace is 427 * still able to use more fine-grained preemption levels, since in 428 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 429 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 430 * not real HW workarounds, but merely a way to start using preemption 431 * while maintaining old contract with userspace. 432 */ 433 434 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 435 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 436 437 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 438 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 439 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 440 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 441 442 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 443 if (IS_GEN9_LP(i915)) 444 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 445 } 446 447 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 448 struct i915_wa_list *wal) 449 { 450 struct intel_gt *gt = engine->gt; 451 u8 vals[3] = { 0, 0, 0 }; 452 unsigned int i; 453 454 for (i = 0; i < 3; i++) { 455 u8 ss; 456 457 /* 458 * Only consider slices where one, and only one, subslice has 7 459 * EUs 460 */ 461 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 462 continue; 463 464 /* 465 * subslice_7eu[i] != 0 (because of the check above) and 466 * ss_max == 4 (maximum number of subslices possible per slice) 467 * 468 * -> 0 <= ss <= 3; 469 */ 470 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 471 vals[i] = 3 - ss; 472 } 473 474 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 475 return; 476 477 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 478 wa_masked_field_set(wal, GEN7_GT_MODE, 479 GEN9_IZ_HASHING_MASK(2) | 480 GEN9_IZ_HASHING_MASK(1) | 481 GEN9_IZ_HASHING_MASK(0), 482 GEN9_IZ_HASHING(2, vals[2]) | 483 GEN9_IZ_HASHING(1, vals[1]) | 484 GEN9_IZ_HASHING(0, vals[0])); 485 } 486 487 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 488 struct i915_wa_list *wal) 489 { 490 gen9_ctx_workarounds_init(engine, wal); 491 skl_tune_iz_hashing(engine, wal); 492 } 493 494 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 495 struct i915_wa_list *wal) 496 { 497 gen9_ctx_workarounds_init(engine, wal); 498 499 /* WaDisableThreadStallDopClockGating:bxt */ 500 wa_masked_en(wal, GEN8_ROW_CHICKEN, 501 STALL_DOP_GATING_DISABLE); 502 503 /* WaToEnableHwFixForPushConstHWBug:bxt */ 504 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 505 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 506 } 507 508 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 509 struct i915_wa_list *wal) 510 { 511 struct drm_i915_private *i915 = engine->i915; 512 513 gen9_ctx_workarounds_init(engine, wal); 514 515 /* WaToEnableHwFixForPushConstHWBug:kbl */ 516 if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 517 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 518 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 519 520 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 521 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 522 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 523 } 524 525 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 526 struct i915_wa_list *wal) 527 { 528 gen9_ctx_workarounds_init(engine, wal); 529 530 /* WaToEnableHwFixForPushConstHWBug:glk */ 531 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 532 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 533 } 534 535 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 536 struct i915_wa_list *wal) 537 { 538 gen9_ctx_workarounds_init(engine, wal); 539 540 /* WaToEnableHwFixForPushConstHWBug:cfl */ 541 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 542 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 543 544 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 545 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 546 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 547 } 548 549 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 550 struct i915_wa_list *wal) 551 { 552 /* WaForceContextSaveRestoreNonCoherent:cnl */ 553 wa_masked_en(wal, CNL_HDC_CHICKEN0, 554 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 555 556 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 557 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 558 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 559 560 /* WaPushConstantDereferenceHoldDisable:cnl */ 561 wa_masked_en(wal, GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 562 563 /* FtrEnableFastAnisoL1BankingFix:cnl */ 564 wa_masked_en(wal, HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 565 566 /* WaDisable3DMidCmdPreemption:cnl */ 567 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 568 569 /* WaDisableGPGPUMidCmdPreemption:cnl */ 570 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 571 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 572 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 573 574 /* WaDisableEarlyEOT:cnl */ 575 wa_masked_en(wal, GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 576 } 577 578 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 579 struct i915_wa_list *wal) 580 { 581 struct drm_i915_private *i915 = engine->i915; 582 583 /* WaDisableBankHangMode:icl */ 584 wa_write(wal, 585 GEN8_L3CNTLREG, 586 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 587 GEN8_ERRDETBCTRL); 588 589 /* Wa_1604370585:icl (pre-prod) 590 * Formerly known as WaPushConstantDereferenceHoldDisable 591 */ 592 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 593 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 594 PUSH_CONSTANT_DEREF_DISABLE); 595 596 /* WaForceEnableNonCoherent:icl 597 * This is not the same workaround as in early Gen9 platforms, where 598 * lacking this could cause system hangs, but coherency performance 599 * overhead is high and only a few compute workloads really need it 600 * (the register is whitelisted in hardware now, so UMDs can opt in 601 * for coherency if they have a good reason). 602 */ 603 wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 604 605 /* Wa_2006611047:icl (pre-prod) 606 * Formerly known as WaDisableImprovedTdlClkGating 607 */ 608 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 609 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 610 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 611 612 /* Wa_2006665173:icl (pre-prod) */ 613 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 614 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 615 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 616 617 /* WaEnableFloatBlendOptimization:icl */ 618 wa_write_clr_set(wal, 619 GEN10_CACHE_MODE_SS, 620 0, /* write-only, so skip validation */ 621 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 622 623 /* WaDisableGPGPUMidThreadPreemption:icl */ 624 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 625 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 626 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 627 628 /* allow headerless messages for preemptible GPGPU context */ 629 wa_masked_en(wal, GEN10_SAMPLER_MODE, 630 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 631 632 /* Wa_1604278689:icl,ehl */ 633 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 634 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 635 0, /* write-only register; skip validation */ 636 0xFFFFFFFF); 637 638 /* Wa_1406306137:icl,ehl */ 639 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 640 } 641 642 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 643 struct i915_wa_list *wal) 644 { 645 /* 646 * Wa_1409142259:tgl 647 * Wa_1409347922:tgl 648 * Wa_1409252684:tgl 649 * Wa_1409217633:tgl 650 * Wa_1409207793:tgl 651 * Wa_1409178076:tgl 652 * Wa_1408979724:tgl 653 * Wa_14010443199:rkl 654 * Wa_14010698770:rkl 655 */ 656 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 657 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 658 659 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 660 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 661 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 662 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 663 } 664 665 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 666 struct i915_wa_list *wal) 667 { 668 gen12_ctx_workarounds_init(engine, wal); 669 670 /* 671 * Wa_1604555607:tgl,rkl 672 * 673 * Note that the implementation of this workaround is further modified 674 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 675 * FF_MODE2 register will return the wrong value when read. The default 676 * value for this register is zero for all fields and there are no bit 677 * masks. So instead of doing a RMW we should just write the GS Timer 678 * and TDS timer values for Wa_1604555607 and Wa_16011163337. 679 */ 680 wa_add(wal, 681 FF_MODE2, 682 FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, 683 FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 684 0); 685 } 686 687 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 688 struct i915_wa_list *wal) 689 { 690 gen12_ctx_workarounds_init(engine, wal); 691 692 /* Wa_1409044764 */ 693 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 694 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 695 696 /* Wa_22010493298 */ 697 wa_masked_en(wal, HIZ_CHICKEN, 698 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 699 700 /* 701 * Wa_16011163337 702 * 703 * Like in tgl_ctx_workarounds_init(), read verification is ignored due 704 * to Wa_1608008084. 705 */ 706 wa_add(wal, 707 FF_MODE2, 708 FF_MODE2_GS_TIMER_MASK, FF_MODE2_GS_TIMER_224, 0); 709 } 710 711 static void 712 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 713 struct i915_wa_list *wal, 714 const char *name) 715 { 716 struct drm_i915_private *i915 = engine->i915; 717 718 if (engine->class != RENDER_CLASS) 719 return; 720 721 wa_init_start(wal, name, engine->name); 722 723 if (IS_DG1(i915)) 724 dg1_ctx_workarounds_init(engine, wal); 725 else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) 726 tgl_ctx_workarounds_init(engine, wal); 727 else if (IS_GEN(i915, 12)) 728 gen12_ctx_workarounds_init(engine, wal); 729 else if (IS_GEN(i915, 11)) 730 icl_ctx_workarounds_init(engine, wal); 731 else if (IS_CANNONLAKE(i915)) 732 cnl_ctx_workarounds_init(engine, wal); 733 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 734 cfl_ctx_workarounds_init(engine, wal); 735 else if (IS_GEMINILAKE(i915)) 736 glk_ctx_workarounds_init(engine, wal); 737 else if (IS_KABYLAKE(i915)) 738 kbl_ctx_workarounds_init(engine, wal); 739 else if (IS_BROXTON(i915)) 740 bxt_ctx_workarounds_init(engine, wal); 741 else if (IS_SKYLAKE(i915)) 742 skl_ctx_workarounds_init(engine, wal); 743 else if (IS_CHERRYVIEW(i915)) 744 chv_ctx_workarounds_init(engine, wal); 745 else if (IS_BROADWELL(i915)) 746 bdw_ctx_workarounds_init(engine, wal); 747 else if (IS_GEN(i915, 7)) 748 gen7_ctx_workarounds_init(engine, wal); 749 else if (IS_GEN(i915, 6)) 750 gen6_ctx_workarounds_init(engine, wal); 751 else if (INTEL_GEN(i915) < 8) 752 return; 753 else 754 MISSING_CASE(INTEL_GEN(i915)); 755 756 wa_init_finish(wal); 757 } 758 759 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 760 { 761 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 762 } 763 764 int intel_engine_emit_ctx_wa(struct i915_request *rq) 765 { 766 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 767 struct i915_wa *wa; 768 unsigned int i; 769 u32 *cs; 770 int ret; 771 772 if (wal->count == 0) 773 return 0; 774 775 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 776 if (ret) 777 return ret; 778 779 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 780 if (IS_ERR(cs)) 781 return PTR_ERR(cs); 782 783 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 784 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 785 *cs++ = i915_mmio_reg_offset(wa->reg); 786 *cs++ = wa->set; 787 } 788 *cs++ = MI_NOOP; 789 790 intel_ring_advance(rq, cs); 791 792 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 793 if (ret) 794 return ret; 795 796 return 0; 797 } 798 799 static void 800 gen4_gt_workarounds_init(struct drm_i915_private *i915, 801 struct i915_wa_list *wal) 802 { 803 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 804 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 805 } 806 807 static void 808 g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 809 { 810 gen4_gt_workarounds_init(i915, wal); 811 812 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 813 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 814 } 815 816 static void 817 ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 818 { 819 g4x_gt_workarounds_init(i915, wal); 820 821 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 822 } 823 824 static void 825 snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 826 { 827 } 828 829 static void 830 ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 831 { 832 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 833 wa_masked_dis(wal, 834 GEN7_COMMON_SLICE_CHICKEN1, 835 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 836 837 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 838 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 839 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 840 841 /* WaForceL3Serialization:ivb */ 842 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 843 } 844 845 static void 846 vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 847 { 848 /* WaForceL3Serialization:vlv */ 849 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 850 851 /* 852 * WaIncreaseL3CreditsForVLVB0:vlv 853 * This is the hardware default actually. 854 */ 855 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 856 } 857 858 static void 859 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 860 { 861 /* L3 caching of data atomics doesn't work -- disable it. */ 862 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 863 864 wa_add(wal, 865 HSW_ROW_CHICKEN3, 0, 866 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 867 0 /* XXX does this reg exist? */); 868 869 /* WaVSRefCountFullforceMissDisable:hsw */ 870 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 871 } 872 873 static void 874 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 875 { 876 /* WaDisableKillLogic:bxt,skl,kbl */ 877 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 878 wa_write_or(wal, 879 GAM_ECOCHK, 880 ECOCHK_DIS_TLB); 881 882 if (HAS_LLC(i915)) { 883 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 884 * 885 * Must match Display Engine. See 886 * WaCompressedResourceDisplayNewHashMode. 887 */ 888 wa_write_or(wal, 889 MMCD_MISC_CTRL, 890 MMCD_PCLA | MMCD_HOTSPOT_EN); 891 } 892 893 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 894 wa_write_or(wal, 895 GAM_ECOCHK, 896 BDW_DISABLE_HDC_INVALIDATION); 897 } 898 899 static void 900 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 901 { 902 gen9_gt_workarounds_init(i915, wal); 903 904 /* WaDisableGafsUnitClkGating:skl */ 905 wa_write_or(wal, 906 GEN7_UCGCTL4, 907 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 908 909 /* WaInPlaceDecompressionHang:skl */ 910 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 911 wa_write_or(wal, 912 GEN9_GAMT_ECO_REG_RW_IA, 913 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 914 } 915 916 static void 917 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 918 { 919 gen9_gt_workarounds_init(i915, wal); 920 921 /* WaInPlaceDecompressionHang:bxt */ 922 wa_write_or(wal, 923 GEN9_GAMT_ECO_REG_RW_IA, 924 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 925 } 926 927 static void 928 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 929 { 930 gen9_gt_workarounds_init(i915, wal); 931 932 /* WaDisableDynamicCreditSharing:kbl */ 933 if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0)) 934 wa_write_or(wal, 935 GAMT_CHKN_BIT_REG, 936 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 937 938 /* WaDisableGafsUnitClkGating:kbl */ 939 wa_write_or(wal, 940 GEN7_UCGCTL4, 941 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 942 943 /* WaInPlaceDecompressionHang:kbl */ 944 wa_write_or(wal, 945 GEN9_GAMT_ECO_REG_RW_IA, 946 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 947 } 948 949 static void 950 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 951 { 952 gen9_gt_workarounds_init(i915, wal); 953 } 954 955 static void 956 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 957 { 958 gen9_gt_workarounds_init(i915, wal); 959 960 /* WaDisableGafsUnitClkGating:cfl */ 961 wa_write_or(wal, 962 GEN7_UCGCTL4, 963 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 964 965 /* WaInPlaceDecompressionHang:cfl */ 966 wa_write_or(wal, 967 GEN9_GAMT_ECO_REG_RW_IA, 968 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 969 } 970 971 static void 972 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 973 { 974 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; 975 unsigned int slice, subslice; 976 u32 l3_en, mcr, mcr_mask; 977 978 GEM_BUG_ON(INTEL_GEN(i915) < 10); 979 980 /* 981 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 982 * L3Banks could be fused off in single slice scenario. If that is 983 * the case, we might need to program MCR select to a valid L3Bank 984 * by default, to make sure we correctly read certain registers 985 * later on (in the range 0xB100 - 0xB3FF). 986 * 987 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 988 * Before any MMIO read into slice/subslice specific registers, MCR 989 * packet control register needs to be programmed to point to any 990 * enabled s/ss pair. Otherwise, incorrect values will be returned. 991 * This means each subsequent MMIO read will be forwarded to an 992 * specific s/ss combination, but this is OK since these registers 993 * are consistent across s/ss in almost all cases. In the rare 994 * occasions, such as INSTDONE, where this value is dependent 995 * on s/ss combo, the read should be done with read_subslice_reg. 996 * 997 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 998 * to which subslice, or to which L3 bank, the respective mmio reads 999 * will go, we have to find a common index which works for both 1000 * accesses. 1001 * 1002 * Case where we cannot find a common index fortunately should not 1003 * happen in production hardware, so we only emit a warning instead of 1004 * implementing something more complex that requires checking the range 1005 * of every MMIO read. 1006 */ 1007 1008 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 1009 u32 l3_fuse = 1010 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 1011 GEN10_L3BANK_MASK; 1012 1013 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse); 1014 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 1015 } else { 1016 l3_en = ~0; 1017 } 1018 1019 slice = fls(sseu->slice_mask) - 1; 1020 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 1021 if (!subslice) { 1022 drm_warn(&i915->drm, 1023 "No common index found between subslice mask %x and L3 bank mask %x!\n", 1024 intel_sseu_get_subslices(sseu, slice), l3_en); 1025 subslice = fls(l3_en); 1026 drm_WARN_ON(&i915->drm, !subslice); 1027 } 1028 subslice--; 1029 1030 if (INTEL_GEN(i915) >= 11) { 1031 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1032 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1033 } else { 1034 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1035 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1036 } 1037 1038 drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr); 1039 1040 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1041 } 1042 1043 static void 1044 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1045 { 1046 wa_init_mcr(i915, wal); 1047 1048 /* WaInPlaceDecompressionHang:cnl */ 1049 wa_write_or(wal, 1050 GEN9_GAMT_ECO_REG_RW_IA, 1051 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1052 } 1053 1054 static void 1055 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1056 { 1057 wa_init_mcr(i915, wal); 1058 1059 /* WaInPlaceDecompressionHang:icl */ 1060 wa_write_or(wal, 1061 GEN9_GAMT_ECO_REG_RW_IA, 1062 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1063 1064 /* WaModifyGamTlbPartitioning:icl */ 1065 wa_write_clr_set(wal, 1066 GEN11_GACB_PERF_CTRL, 1067 GEN11_HASH_CTRL_MASK, 1068 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1069 1070 /* Wa_1405766107:icl 1071 * Formerly known as WaCL2SFHalfMaxAlloc 1072 */ 1073 wa_write_or(wal, 1074 GEN11_LSN_UNSLCVC, 1075 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1076 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1077 1078 /* Wa_220166154:icl 1079 * Formerly known as WaDisCtxReload 1080 */ 1081 wa_write_or(wal, 1082 GEN8_GAMW_ECO_DEV_RW_IA, 1083 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1084 1085 /* Wa_1405779004:icl (pre-prod) */ 1086 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 1087 wa_write_or(wal, 1088 SLICE_UNIT_LEVEL_CLKGATE, 1089 MSCUNIT_CLKGATE_DIS); 1090 1091 /* Wa_1406838659:icl (pre-prod) */ 1092 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1093 wa_write_or(wal, 1094 INF_UNIT_LEVEL_CLKGATE, 1095 CGPSF_CLKGATE_DIS); 1096 1097 /* Wa_1406463099:icl 1098 * Formerly known as WaGamTlbPendError 1099 */ 1100 wa_write_or(wal, 1101 GAMT_CHKN_BIT_REG, 1102 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1103 1104 /* Wa_1607087056:icl,ehl,jsl */ 1105 if (IS_ICELAKE(i915) || 1106 IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) { 1107 wa_write_or(wal, 1108 SLICE_UNIT_LEVEL_CLKGATE, 1109 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1110 } 1111 } 1112 1113 static void 1114 gen12_gt_workarounds_init(struct drm_i915_private *i915, 1115 struct i915_wa_list *wal) 1116 { 1117 wa_init_mcr(i915, wal); 1118 } 1119 1120 static void 1121 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1122 { 1123 gen12_gt_workarounds_init(i915, wal); 1124 1125 /* Wa_1409420604:tgl */ 1126 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1127 wa_write_or(wal, 1128 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1129 CPSSUNIT_CLKGATE_DIS); 1130 1131 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1132 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1133 wa_write_or(wal, 1134 SLICE_UNIT_LEVEL_CLKGATE, 1135 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1136 1137 /* Wa_1408615072:tgl[a0] */ 1138 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1139 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1140 VSUNIT_CLKGATE_DIS_TGL); 1141 } 1142 1143 static void 1144 dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1145 { 1146 gen12_gt_workarounds_init(i915, wal); 1147 1148 /* Wa_1607087056:dg1 */ 1149 if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0)) 1150 wa_write_or(wal, 1151 SLICE_UNIT_LEVEL_CLKGATE, 1152 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1153 1154 /* Wa_1409420604:dg1 */ 1155 if (IS_DG1(i915)) 1156 wa_write_or(wal, 1157 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1158 CPSSUNIT_CLKGATE_DIS); 1159 1160 /* Wa_1408615072:dg1 */ 1161 /* Empirical testing shows this register is unaffected by engine reset. */ 1162 if (IS_DG1(i915)) 1163 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1164 VSUNIT_CLKGATE_DIS_TGL); 1165 } 1166 1167 static void 1168 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 1169 { 1170 if (IS_DG1(i915)) 1171 dg1_gt_workarounds_init(i915, wal); 1172 else if (IS_TIGERLAKE(i915)) 1173 tgl_gt_workarounds_init(i915, wal); 1174 else if (IS_GEN(i915, 12)) 1175 gen12_gt_workarounds_init(i915, wal); 1176 else if (IS_GEN(i915, 11)) 1177 icl_gt_workarounds_init(i915, wal); 1178 else if (IS_CANNONLAKE(i915)) 1179 cnl_gt_workarounds_init(i915, wal); 1180 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1181 cfl_gt_workarounds_init(i915, wal); 1182 else if (IS_GEMINILAKE(i915)) 1183 glk_gt_workarounds_init(i915, wal); 1184 else if (IS_KABYLAKE(i915)) 1185 kbl_gt_workarounds_init(i915, wal); 1186 else if (IS_BROXTON(i915)) 1187 bxt_gt_workarounds_init(i915, wal); 1188 else if (IS_SKYLAKE(i915)) 1189 skl_gt_workarounds_init(i915, wal); 1190 else if (IS_HASWELL(i915)) 1191 hsw_gt_workarounds_init(i915, wal); 1192 else if (IS_VALLEYVIEW(i915)) 1193 vlv_gt_workarounds_init(i915, wal); 1194 else if (IS_IVYBRIDGE(i915)) 1195 ivb_gt_workarounds_init(i915, wal); 1196 else if (IS_GEN(i915, 6)) 1197 snb_gt_workarounds_init(i915, wal); 1198 else if (IS_GEN(i915, 5)) 1199 ilk_gt_workarounds_init(i915, wal); 1200 else if (IS_G4X(i915)) 1201 g4x_gt_workarounds_init(i915, wal); 1202 else if (IS_GEN(i915, 4)) 1203 gen4_gt_workarounds_init(i915, wal); 1204 else if (INTEL_GEN(i915) <= 8) 1205 return; 1206 else 1207 MISSING_CASE(INTEL_GEN(i915)); 1208 } 1209 1210 void intel_gt_init_workarounds(struct drm_i915_private *i915) 1211 { 1212 struct i915_wa_list *wal = &i915->gt_wa_list; 1213 1214 wa_init_start(wal, "GT", "global"); 1215 gt_init_workarounds(i915, wal); 1216 wa_init_finish(wal); 1217 } 1218 1219 static enum forcewake_domains 1220 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1221 { 1222 enum forcewake_domains fw = 0; 1223 struct i915_wa *wa; 1224 unsigned int i; 1225 1226 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1227 fw |= intel_uncore_forcewake_for_reg(uncore, 1228 wa->reg, 1229 FW_REG_READ | 1230 FW_REG_WRITE); 1231 1232 return fw; 1233 } 1234 1235 static bool 1236 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1237 { 1238 if ((cur ^ wa->set) & wa->read) { 1239 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1240 name, from, i915_mmio_reg_offset(wa->reg), 1241 cur, cur & wa->read, wa->set & wa->read); 1242 1243 return false; 1244 } 1245 1246 return true; 1247 } 1248 1249 static void 1250 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1251 { 1252 enum forcewake_domains fw; 1253 unsigned long flags; 1254 struct i915_wa *wa; 1255 unsigned int i; 1256 1257 if (!wal->count) 1258 return; 1259 1260 fw = wal_get_fw_for_rmw(uncore, wal); 1261 1262 spin_lock_irqsave(&uncore->lock, flags); 1263 intel_uncore_forcewake_get__locked(uncore, fw); 1264 1265 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1266 if (wa->clr) 1267 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1268 else 1269 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1270 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1271 wa_verify(wa, 1272 intel_uncore_read_fw(uncore, wa->reg), 1273 wal->name, "application"); 1274 } 1275 1276 intel_uncore_forcewake_put__locked(uncore, fw); 1277 spin_unlock_irqrestore(&uncore->lock, flags); 1278 } 1279 1280 void intel_gt_apply_workarounds(struct intel_gt *gt) 1281 { 1282 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1283 } 1284 1285 static bool wa_list_verify(struct intel_uncore *uncore, 1286 const struct i915_wa_list *wal, 1287 const char *from) 1288 { 1289 struct i915_wa *wa; 1290 unsigned int i; 1291 bool ok = true; 1292 1293 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1294 ok &= wa_verify(wa, 1295 intel_uncore_read(uncore, wa->reg), 1296 wal->name, from); 1297 1298 return ok; 1299 } 1300 1301 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1302 { 1303 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1304 } 1305 1306 __maybe_unused 1307 static bool is_nonpriv_flags_valid(u32 flags) 1308 { 1309 /* Check only valid flag bits are set */ 1310 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1311 return false; 1312 1313 /* NB: Only 3 out of 4 enum values are valid for access field */ 1314 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1315 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1316 return false; 1317 1318 return true; 1319 } 1320 1321 static void 1322 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1323 { 1324 struct i915_wa wa = { 1325 .reg = reg 1326 }; 1327 1328 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1329 return; 1330 1331 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1332 return; 1333 1334 wa.reg.reg |= flags; 1335 _wa_add(wal, &wa); 1336 } 1337 1338 static void 1339 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1340 { 1341 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1342 } 1343 1344 static void gen9_whitelist_build(struct i915_wa_list *w) 1345 { 1346 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1347 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1348 1349 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1350 whitelist_reg(w, GEN8_CS_CHICKEN1); 1351 1352 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1353 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1354 1355 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1356 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1357 } 1358 1359 static void skl_whitelist_build(struct intel_engine_cs *engine) 1360 { 1361 struct i915_wa_list *w = &engine->whitelist; 1362 1363 if (engine->class != RENDER_CLASS) 1364 return; 1365 1366 gen9_whitelist_build(w); 1367 1368 /* WaDisableLSQCROPERFforOCL:skl */ 1369 whitelist_reg(w, GEN8_L3SQCREG4); 1370 } 1371 1372 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1373 { 1374 if (engine->class != RENDER_CLASS) 1375 return; 1376 1377 gen9_whitelist_build(&engine->whitelist); 1378 } 1379 1380 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1381 { 1382 struct i915_wa_list *w = &engine->whitelist; 1383 1384 if (engine->class != RENDER_CLASS) 1385 return; 1386 1387 gen9_whitelist_build(w); 1388 1389 /* WaDisableLSQCROPERFforOCL:kbl */ 1390 whitelist_reg(w, GEN8_L3SQCREG4); 1391 } 1392 1393 static void glk_whitelist_build(struct intel_engine_cs *engine) 1394 { 1395 struct i915_wa_list *w = &engine->whitelist; 1396 1397 if (engine->class != RENDER_CLASS) 1398 return; 1399 1400 gen9_whitelist_build(w); 1401 1402 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1403 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1404 } 1405 1406 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1407 { 1408 struct i915_wa_list *w = &engine->whitelist; 1409 1410 if (engine->class != RENDER_CLASS) 1411 return; 1412 1413 gen9_whitelist_build(w); 1414 1415 /* 1416 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1417 * 1418 * This covers 4 register which are next to one another : 1419 * - PS_INVOCATION_COUNT 1420 * - PS_INVOCATION_COUNT_UDW 1421 * - PS_DEPTH_COUNT 1422 * - PS_DEPTH_COUNT_UDW 1423 */ 1424 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1425 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1426 RING_FORCE_TO_NONPRIV_RANGE_4); 1427 } 1428 1429 static void cml_whitelist_build(struct intel_engine_cs *engine) 1430 { 1431 struct i915_wa_list *w = &engine->whitelist; 1432 1433 if (engine->class != RENDER_CLASS) 1434 whitelist_reg_ext(w, 1435 RING_CTX_TIMESTAMP(engine->mmio_base), 1436 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1437 1438 cfl_whitelist_build(engine); 1439 } 1440 1441 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1442 { 1443 struct i915_wa_list *w = &engine->whitelist; 1444 1445 if (engine->class != RENDER_CLASS) 1446 return; 1447 1448 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1449 whitelist_reg(w, GEN8_CS_CHICKEN1); 1450 } 1451 1452 static void icl_whitelist_build(struct intel_engine_cs *engine) 1453 { 1454 struct i915_wa_list *w = &engine->whitelist; 1455 1456 switch (engine->class) { 1457 case RENDER_CLASS: 1458 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1459 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1460 1461 /* WaAllowUMDToModifySamplerMode:icl */ 1462 whitelist_reg(w, GEN10_SAMPLER_MODE); 1463 1464 /* WaEnableStateCacheRedirectToCS:icl */ 1465 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1466 1467 /* 1468 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1469 * 1470 * This covers 4 register which are next to one another : 1471 * - PS_INVOCATION_COUNT 1472 * - PS_INVOCATION_COUNT_UDW 1473 * - PS_DEPTH_COUNT 1474 * - PS_DEPTH_COUNT_UDW 1475 */ 1476 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1477 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1478 RING_FORCE_TO_NONPRIV_RANGE_4); 1479 break; 1480 1481 case VIDEO_DECODE_CLASS: 1482 /* hucStatusRegOffset */ 1483 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1484 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1485 /* hucUKernelHdrInfoRegOffset */ 1486 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1487 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1488 /* hucStatus2RegOffset */ 1489 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1490 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1491 whitelist_reg_ext(w, 1492 RING_CTX_TIMESTAMP(engine->mmio_base), 1493 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1494 break; 1495 1496 default: 1497 whitelist_reg_ext(w, 1498 RING_CTX_TIMESTAMP(engine->mmio_base), 1499 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1500 break; 1501 } 1502 } 1503 1504 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1505 { 1506 struct i915_wa_list *w = &engine->whitelist; 1507 1508 switch (engine->class) { 1509 case RENDER_CLASS: 1510 /* 1511 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1512 * Wa_1408556865:tgl 1513 * 1514 * This covers 4 registers which are next to one another : 1515 * - PS_INVOCATION_COUNT 1516 * - PS_INVOCATION_COUNT_UDW 1517 * - PS_DEPTH_COUNT 1518 * - PS_DEPTH_COUNT_UDW 1519 */ 1520 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1521 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1522 RING_FORCE_TO_NONPRIV_RANGE_4); 1523 1524 /* Wa_1808121037:tgl */ 1525 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1526 1527 /* Wa_1806527549:tgl */ 1528 whitelist_reg(w, HIZ_CHICKEN); 1529 break; 1530 default: 1531 whitelist_reg_ext(w, 1532 RING_CTX_TIMESTAMP(engine->mmio_base), 1533 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1534 break; 1535 } 1536 } 1537 1538 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1539 { 1540 struct i915_wa_list *w = &engine->whitelist; 1541 1542 tgl_whitelist_build(engine); 1543 1544 /* GEN:BUG:1409280441:dg1 */ 1545 if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) && 1546 (engine->class == RENDER_CLASS || 1547 engine->class == COPY_ENGINE_CLASS)) 1548 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1549 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1550 } 1551 1552 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1553 { 1554 struct drm_i915_private *i915 = engine->i915; 1555 struct i915_wa_list *w = &engine->whitelist; 1556 1557 wa_init_start(w, "whitelist", engine->name); 1558 1559 if (IS_DG1(i915)) 1560 dg1_whitelist_build(engine); 1561 else if (IS_GEN(i915, 12)) 1562 tgl_whitelist_build(engine); 1563 else if (IS_GEN(i915, 11)) 1564 icl_whitelist_build(engine); 1565 else if (IS_CANNONLAKE(i915)) 1566 cnl_whitelist_build(engine); 1567 else if (IS_COMETLAKE(i915)) 1568 cml_whitelist_build(engine); 1569 else if (IS_COFFEELAKE(i915)) 1570 cfl_whitelist_build(engine); 1571 else if (IS_GEMINILAKE(i915)) 1572 glk_whitelist_build(engine); 1573 else if (IS_KABYLAKE(i915)) 1574 kbl_whitelist_build(engine); 1575 else if (IS_BROXTON(i915)) 1576 bxt_whitelist_build(engine); 1577 else if (IS_SKYLAKE(i915)) 1578 skl_whitelist_build(engine); 1579 else if (INTEL_GEN(i915) <= 8) 1580 return; 1581 else 1582 MISSING_CASE(INTEL_GEN(i915)); 1583 1584 wa_init_finish(w); 1585 } 1586 1587 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1588 { 1589 const struct i915_wa_list *wal = &engine->whitelist; 1590 struct intel_uncore *uncore = engine->uncore; 1591 const u32 base = engine->mmio_base; 1592 struct i915_wa *wa; 1593 unsigned int i; 1594 1595 if (!wal->count) 1596 return; 1597 1598 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1599 intel_uncore_write(uncore, 1600 RING_FORCE_TO_NONPRIV(base, i), 1601 i915_mmio_reg_offset(wa->reg)); 1602 1603 /* And clear the rest just in case of garbage */ 1604 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1605 intel_uncore_write(uncore, 1606 RING_FORCE_TO_NONPRIV(base, i), 1607 i915_mmio_reg_offset(RING_NOPID(base))); 1608 } 1609 1610 static void 1611 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1612 { 1613 struct drm_i915_private *i915 = engine->i915; 1614 1615 if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || 1616 IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1617 /* 1618 * Wa_1607138336:tgl[a0],dg1[a0] 1619 * Wa_1607063988:tgl[a0],dg1[a0] 1620 */ 1621 wa_write_or(wal, 1622 GEN9_CTX_PREEMPT_REG, 1623 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1624 } 1625 1626 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1627 /* 1628 * Wa_1606679103:tgl 1629 * (see also Wa_1606682166:icl) 1630 */ 1631 wa_write_or(wal, 1632 GEN7_SARCHKMD, 1633 GEN7_DISABLE_SAMPLER_PREFETCH); 1634 } 1635 1636 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1637 /* Wa_1606931601:tgl,rkl,dg1 */ 1638 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1639 1640 /* 1641 * Wa_1407928979:tgl A* 1642 * Wa_18011464164:tgl[B0+],dg1[B0+] 1643 * Wa_22010931296:tgl[B0+],dg1[B0+] 1644 * Wa_14010919138:rkl, dg1 1645 */ 1646 wa_write_or(wal, GEN7_FF_THREAD_MODE, 1647 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1648 1649 /* 1650 * Wa_1606700617:tgl,dg1 1651 * Wa_22010271021:tgl,rkl,dg1 1652 */ 1653 wa_masked_en(wal, 1654 GEN9_CS_DEBUG_MODE1, 1655 FF_DOP_CLOCK_GATE_DISABLE); 1656 1657 /* Wa_1406941453:tgl,rkl,dg1 */ 1658 wa_masked_en(wal, 1659 GEN10_SAMPLER_MODE, 1660 ENABLE_SMALLPL); 1661 } 1662 1663 if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || 1664 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1665 /* Wa_1409804808:tgl,rkl,dg1[a0] */ 1666 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1667 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1668 1669 /* 1670 * Wa_1409085225:tgl 1671 * Wa_14010229206:tgl,rkl,dg1[a0] 1672 */ 1673 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1674 1675 /* 1676 * Wa_1607030317:tgl 1677 * Wa_1607186500:tgl 1678 * Wa_1607297627:tgl,rkl,dg1[a0] 1679 * 1680 * On TGL and RKL there are multiple entries for this WA in the 1681 * BSpec; some indicate this is an A0-only WA, others indicate 1682 * it applies to all steppings so we trust the "all steppings." 1683 * For DG1 this only applies to A0. 1684 */ 1685 wa_masked_en(wal, 1686 GEN6_RC_SLEEP_PSMI_CONTROL, 1687 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1688 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1689 } 1690 1691 if (IS_GEN(i915, 11)) { 1692 /* This is not an Wa. Enable for better image quality */ 1693 wa_masked_en(wal, 1694 _3D_CHICKEN3, 1695 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1696 1697 /* WaPipelineFlushCoherentLines:icl */ 1698 wa_write_or(wal, 1699 GEN8_L3SQCREG4, 1700 GEN8_LQSC_FLUSH_COHERENT_LINES); 1701 1702 /* 1703 * Wa_1405543622:icl 1704 * Formerly known as WaGAPZPriorityScheme 1705 */ 1706 wa_write_or(wal, 1707 GEN8_GARBCNTL, 1708 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1709 1710 /* 1711 * Wa_1604223664:icl 1712 * Formerly known as WaL3BankAddressHashing 1713 */ 1714 wa_write_clr_set(wal, 1715 GEN8_GARBCNTL, 1716 GEN11_HASH_CTRL_EXCL_MASK, 1717 GEN11_HASH_CTRL_EXCL_BIT0); 1718 wa_write_clr_set(wal, 1719 GEN11_GLBLINVL, 1720 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1721 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1722 1723 /* 1724 * Wa_1405733216:icl 1725 * Formerly known as WaDisableCleanEvicts 1726 */ 1727 wa_write_or(wal, 1728 GEN8_L3SQCREG4, 1729 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1730 1731 /* WaForwardProgressSoftReset:icl */ 1732 wa_write_or(wal, 1733 GEN10_SCRATCH_LNCF2, 1734 PMFLUSHDONE_LNICRSDROP | 1735 PMFLUSH_GAPL3UNBLOCK | 1736 PMFLUSHDONE_LNEBLK); 1737 1738 /* Wa_1406609255:icl (pre-prod) */ 1739 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1740 wa_write_or(wal, 1741 GEN7_SARCHKMD, 1742 GEN7_DISABLE_DEMAND_PREFETCH); 1743 1744 /* Wa_1606682166:icl */ 1745 wa_write_or(wal, 1746 GEN7_SARCHKMD, 1747 GEN7_DISABLE_SAMPLER_PREFETCH); 1748 1749 /* Wa_1409178092:icl */ 1750 wa_write_clr_set(wal, 1751 GEN11_SCRATCH2, 1752 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1753 0); 1754 1755 /* WaEnable32PlaneMode:icl */ 1756 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1757 GEN11_ENABLE_32_PLANE_MODE); 1758 1759 /* 1760 * Wa_1408615072:icl,ehl (vsunit) 1761 * Wa_1407596294:icl,ehl (hsunit) 1762 */ 1763 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1764 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1765 1766 /* Wa_1407352427:icl,ehl */ 1767 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1768 PSDUNIT_CLKGATE_DIS); 1769 1770 /* Wa_1406680159:icl,ehl */ 1771 wa_write_or(wal, 1772 SUBSLICE_UNIT_LEVEL_CLKGATE, 1773 GWUNIT_CLKGATE_DIS); 1774 1775 /* 1776 * Wa_1408767742:icl[a2..forever],ehl[all] 1777 * Wa_1605460711:icl[a0..c0] 1778 */ 1779 wa_write_or(wal, 1780 GEN7_FF_THREAD_MODE, 1781 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1782 1783 /* Wa_22010271021:ehl */ 1784 if (IS_JSL_EHL(i915)) 1785 wa_masked_en(wal, 1786 GEN9_CS_DEBUG_MODE1, 1787 FF_DOP_CLOCK_GATE_DISABLE); 1788 } 1789 1790 if (IS_GEN_RANGE(i915, 9, 12)) { 1791 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1792 wa_masked_en(wal, 1793 GEN7_FF_SLICE_CS_CHICKEN1, 1794 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1795 } 1796 1797 if (IS_SKYLAKE(i915) || 1798 IS_KABYLAKE(i915) || 1799 IS_COFFEELAKE(i915) || 1800 IS_COMETLAKE(i915)) { 1801 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1802 wa_write_or(wal, 1803 GEN8_GARBCNTL, 1804 GEN9_GAPS_TSV_CREDIT_DISABLE); 1805 } 1806 1807 if (IS_BROXTON(i915)) { 1808 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1809 wa_masked_en(wal, 1810 FF_SLICE_CS_CHICKEN2, 1811 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1812 } 1813 1814 if (IS_GEN(i915, 9)) { 1815 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1816 wa_masked_en(wal, 1817 GEN9_CSFE_CHICKEN1_RCS, 1818 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1819 1820 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1821 wa_write_or(wal, 1822 BDW_SCRATCH1, 1823 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1824 1825 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1826 if (IS_GEN9_LP(i915)) 1827 wa_write_clr_set(wal, 1828 GEN8_L3SQCREG1, 1829 L3_PRIO_CREDITS_MASK, 1830 L3_GENERAL_PRIO_CREDITS(62) | 1831 L3_HIGH_PRIO_CREDITS(2)); 1832 1833 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1834 wa_write_or(wal, 1835 GEN8_L3SQCREG4, 1836 GEN8_LQSC_FLUSH_COHERENT_LINES); 1837 } 1838 1839 if (IS_HASWELL(i915)) { 1840 /* WaSampleCChickenBitEnable:hsw */ 1841 wa_masked_en(wal, 1842 HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 1843 1844 wa_masked_dis(wal, 1845 CACHE_MODE_0_GEN7, 1846 /* enable HiZ Raw Stall Optimization */ 1847 HIZ_RAW_STALL_OPT_DISABLE); 1848 1849 /* WaDisable4x2SubspanOptimization:hsw */ 1850 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 1851 } 1852 1853 if (IS_VALLEYVIEW(i915)) { 1854 /* WaDisableEarlyCull:vlv */ 1855 wa_masked_en(wal, 1856 _3D_CHICKEN3, 1857 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 1858 1859 /* 1860 * WaVSThreadDispatchOverride:ivb,vlv 1861 * 1862 * This actually overrides the dispatch 1863 * mode for all thread types. 1864 */ 1865 wa_write_clr_set(wal, 1866 GEN7_FF_THREAD_MODE, 1867 GEN7_FF_SCHED_MASK, 1868 GEN7_FF_TS_SCHED_HW | 1869 GEN7_FF_VS_SCHED_HW | 1870 GEN7_FF_DS_SCHED_HW); 1871 1872 /* WaPsdDispatchEnable:vlv */ 1873 /* WaDisablePSDDualDispatchEnable:vlv */ 1874 wa_masked_en(wal, 1875 GEN7_HALF_SLICE_CHICKEN1, 1876 GEN7_MAX_PS_THREAD_DEP | 1877 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 1878 } 1879 1880 if (IS_IVYBRIDGE(i915)) { 1881 /* WaDisableEarlyCull:ivb */ 1882 wa_masked_en(wal, 1883 _3D_CHICKEN3, 1884 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 1885 1886 if (0) { /* causes HiZ corruption on ivb:gt1 */ 1887 /* enable HiZ Raw Stall Optimization */ 1888 wa_masked_dis(wal, 1889 CACHE_MODE_0_GEN7, 1890 HIZ_RAW_STALL_OPT_DISABLE); 1891 } 1892 1893 /* 1894 * WaVSThreadDispatchOverride:ivb,vlv 1895 * 1896 * This actually overrides the dispatch 1897 * mode for all thread types. 1898 */ 1899 wa_write_clr_set(wal, 1900 GEN7_FF_THREAD_MODE, 1901 GEN7_FF_SCHED_MASK, 1902 GEN7_FF_TS_SCHED_HW | 1903 GEN7_FF_VS_SCHED_HW | 1904 GEN7_FF_DS_SCHED_HW); 1905 1906 /* WaDisablePSDDualDispatchEnable:ivb */ 1907 if (IS_IVB_GT1(i915)) 1908 wa_masked_en(wal, 1909 GEN7_HALF_SLICE_CHICKEN1, 1910 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 1911 } 1912 1913 if (IS_GEN(i915, 7)) { 1914 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1915 wa_masked_en(wal, 1916 GFX_MODE_GEN7, 1917 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1918 1919 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 1920 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 1921 1922 /* 1923 * BSpec says this must be set, even though 1924 * WaDisable4x2SubspanOptimization:ivb,hsw 1925 * WaDisable4x2SubspanOptimization isn't listed for VLV. 1926 */ 1927 wa_masked_en(wal, 1928 CACHE_MODE_1, 1929 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 1930 1931 /* 1932 * BSpec recommends 8x4 when MSAA is used, 1933 * however in practice 16x4 seems fastest. 1934 * 1935 * Note that PS/WM thread counts depend on the WIZ hashing 1936 * disable bit, which we don't touch here, but it's good 1937 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 1938 */ 1939 wa_add(wal, GEN7_GT_MODE, 0, 1940 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, 1941 GEN6_WIZ_HASHING_16x4), 1942 GEN6_WIZ_HASHING_16x4); 1943 } 1944 1945 if (IS_GEN_RANGE(i915, 6, 7)) 1946 /* 1947 * We need to disable the AsyncFlip performance optimisations in 1948 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1949 * already be programmed to '1' on all products. 1950 * 1951 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1952 */ 1953 wa_masked_en(wal, 1954 MI_MODE, 1955 ASYNC_FLIP_PERF_DISABLE); 1956 1957 if (IS_GEN(i915, 6)) { 1958 /* 1959 * Required for the hardware to program scanline values for 1960 * waiting 1961 * WaEnableFlushTlbInvalidationMode:snb 1962 */ 1963 wa_masked_en(wal, 1964 GFX_MODE, 1965 GFX_TLB_INVALIDATE_EXPLICIT); 1966 1967 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 1968 wa_masked_en(wal, 1969 _3D_CHICKEN, 1970 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 1971 1972 wa_masked_en(wal, 1973 _3D_CHICKEN3, 1974 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 1975 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 1976 /* 1977 * Bspec says: 1978 * "This bit must be set if 3DSTATE_CLIP clip mode is set 1979 * to normal and 3DSTATE_SF number of SF output attributes 1980 * is more than 16." 1981 */ 1982 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 1983 1984 /* 1985 * BSpec recommends 8x4 when MSAA is used, 1986 * however in practice 16x4 seems fastest. 1987 * 1988 * Note that PS/WM thread counts depend on the WIZ hashing 1989 * disable bit, which we don't touch here, but it's good 1990 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 1991 */ 1992 wa_add(wal, 1993 GEN6_GT_MODE, 0, 1994 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 1995 GEN6_WIZ_HASHING_16x4); 1996 1997 /* WaDisable_RenderCache_OperationalFlush:snb */ 1998 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 1999 2000 /* 2001 * From the Sandybridge PRM, volume 1 part 3, page 24: 2002 * "If this bit is set, STCunit will have LRA as replacement 2003 * policy. [...] This bit must be reset. LRA replacement 2004 * policy is not supported." 2005 */ 2006 wa_masked_dis(wal, 2007 CACHE_MODE_0, 2008 CM0_STC_EVICT_DISABLE_LRA_SNB); 2009 } 2010 2011 if (IS_GEN_RANGE(i915, 4, 6)) 2012 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2013 wa_add(wal, MI_MODE, 2014 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2015 /* XXX bit doesn't stick on Broadwater */ 2016 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 2017 2018 if (IS_GEN(i915, 4)) 2019 /* 2020 * Disable CONSTANT_BUFFER before it is loaded from the context 2021 * image. For as it is loaded, it is executed and the stored 2022 * address may no longer be valid, leading to a GPU hang. 2023 * 2024 * This imposes the requirement that userspace reload their 2025 * CONSTANT_BUFFER on every batch, fortunately a requirement 2026 * they are already accustomed to from before contexts were 2027 * enabled. 2028 */ 2029 wa_add(wal, ECOSKPD, 2030 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2031 0 /* XXX bit doesn't stick on Broadwater */); 2032 } 2033 2034 static void 2035 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2036 { 2037 struct drm_i915_private *i915 = engine->i915; 2038 2039 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2040 if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 2041 wa_write(wal, 2042 RING_SEMA_WAIT_POLL(engine->mmio_base), 2043 1); 2044 } 2045 } 2046 2047 static void 2048 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2049 { 2050 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 2051 return; 2052 2053 if (engine->class == RENDER_CLASS) 2054 rcs_engine_wa_init(engine, wal); 2055 else 2056 xcs_engine_wa_init(engine, wal); 2057 } 2058 2059 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2060 { 2061 struct i915_wa_list *wal = &engine->wa_list; 2062 2063 if (INTEL_GEN(engine->i915) < 4) 2064 return; 2065 2066 wa_init_start(wal, "engine", engine->name); 2067 engine_init_workarounds(engine, wal); 2068 wa_init_finish(wal); 2069 } 2070 2071 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2072 { 2073 wa_list_apply(engine->uncore, &engine->wa_list); 2074 } 2075 2076 struct mcr_range { 2077 u32 start; 2078 u32 end; 2079 }; 2080 2081 static const struct mcr_range mcr_ranges_gen8[] = { 2082 { .start = 0x5500, .end = 0x55ff }, 2083 { .start = 0x7000, .end = 0x7fff }, 2084 { .start = 0x9400, .end = 0x97ff }, 2085 { .start = 0xb000, .end = 0xb3ff }, 2086 { .start = 0xe000, .end = 0xe7ff }, 2087 {}, 2088 }; 2089 2090 static const struct mcr_range mcr_ranges_gen12[] = { 2091 { .start = 0x8150, .end = 0x815f }, 2092 { .start = 0x9520, .end = 0x955f }, 2093 { .start = 0xb100, .end = 0xb3ff }, 2094 { .start = 0xde80, .end = 0xe8ff }, 2095 { .start = 0x24a00, .end = 0x24a7f }, 2096 {}, 2097 }; 2098 2099 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2100 { 2101 const struct mcr_range *mcr_ranges; 2102 int i; 2103 2104 if (INTEL_GEN(i915) >= 12) 2105 mcr_ranges = mcr_ranges_gen12; 2106 else if (INTEL_GEN(i915) >= 8) 2107 mcr_ranges = mcr_ranges_gen8; 2108 else 2109 return false; 2110 2111 /* 2112 * Registers in these ranges are affected by the MCR selector 2113 * which only controls CPU initiated MMIO. Routing does not 2114 * work for CS access so we cannot verify them on this path. 2115 */ 2116 for (i = 0; mcr_ranges[i].start; i++) 2117 if (offset >= mcr_ranges[i].start && 2118 offset <= mcr_ranges[i].end) 2119 return true; 2120 2121 return false; 2122 } 2123 2124 static int 2125 wa_list_srm(struct i915_request *rq, 2126 const struct i915_wa_list *wal, 2127 struct i915_vma *vma) 2128 { 2129 struct drm_i915_private *i915 = rq->engine->i915; 2130 unsigned int i, count = 0; 2131 const struct i915_wa *wa; 2132 u32 srm, *cs; 2133 2134 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2135 if (INTEL_GEN(i915) >= 8) 2136 srm++; 2137 2138 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2139 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2140 count++; 2141 } 2142 2143 cs = intel_ring_begin(rq, 4 * count); 2144 if (IS_ERR(cs)) 2145 return PTR_ERR(cs); 2146 2147 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2148 u32 offset = i915_mmio_reg_offset(wa->reg); 2149 2150 if (mcr_range(i915, offset)) 2151 continue; 2152 2153 *cs++ = srm; 2154 *cs++ = offset; 2155 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2156 *cs++ = 0; 2157 } 2158 intel_ring_advance(rq, cs); 2159 2160 return 0; 2161 } 2162 2163 static int engine_wa_list_verify(struct intel_context *ce, 2164 const struct i915_wa_list * const wal, 2165 const char *from) 2166 { 2167 const struct i915_wa *wa; 2168 struct i915_request *rq; 2169 struct i915_vma *vma; 2170 struct i915_gem_ww_ctx ww; 2171 unsigned int i; 2172 u32 *results; 2173 int err; 2174 2175 if (!wal->count) 2176 return 0; 2177 2178 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 2179 wal->count * sizeof(u32)); 2180 if (IS_ERR(vma)) 2181 return PTR_ERR(vma); 2182 2183 intel_engine_pm_get(ce->engine); 2184 i915_gem_ww_ctx_init(&ww, false); 2185 retry: 2186 err = i915_gem_object_lock(vma->obj, &ww); 2187 if (err == 0) 2188 err = intel_context_pin_ww(ce, &ww); 2189 if (err) 2190 goto err_pm; 2191 2192 rq = i915_request_create(ce); 2193 if (IS_ERR(rq)) { 2194 err = PTR_ERR(rq); 2195 goto err_unpin; 2196 } 2197 2198 err = i915_request_await_object(rq, vma->obj, true); 2199 if (err == 0) 2200 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2201 if (err == 0) 2202 err = wa_list_srm(rq, wal, vma); 2203 2204 i915_request_get(rq); 2205 if (err) 2206 i915_request_set_error_once(rq, err); 2207 i915_request_add(rq); 2208 2209 if (err) 2210 goto err_rq; 2211 2212 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2213 err = -ETIME; 2214 goto err_rq; 2215 } 2216 2217 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2218 if (IS_ERR(results)) { 2219 err = PTR_ERR(results); 2220 goto err_rq; 2221 } 2222 2223 err = 0; 2224 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2225 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2226 continue; 2227 2228 if (!wa_verify(wa, results[i], wal->name, from)) 2229 err = -ENXIO; 2230 } 2231 2232 i915_gem_object_unpin_map(vma->obj); 2233 2234 err_rq: 2235 i915_request_put(rq); 2236 err_unpin: 2237 intel_context_unpin(ce); 2238 err_pm: 2239 if (err == -EDEADLK) { 2240 err = i915_gem_ww_ctx_backoff(&ww); 2241 if (!err) 2242 goto retry; 2243 } 2244 i915_gem_ww_ctx_fini(&ww); 2245 intel_engine_pm_put(ce->engine); 2246 i915_vma_unpin(vma); 2247 i915_vma_put(vma); 2248 return err; 2249 } 2250 2251 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2252 const char *from) 2253 { 2254 return engine_wa_list_verify(engine->kernel_context, 2255 &engine->wa_list, 2256 from); 2257 } 2258 2259 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2260 #include "selftest_workarounds.c" 2261 #endif 2262