1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 56 { 57 wal->name = name; 58 wal->engine_name = engine_name; 59 } 60 61 #define WA_LIST_CHUNK (1 << 4) 62 63 static void wa_init_finish(struct i915_wa_list *wal) 64 { 65 /* Trim unused entries. */ 66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 67 struct i915_wa *list = kmemdup(wal->list, 68 wal->count * sizeof(*list), 69 GFP_KERNEL); 70 71 if (list) { 72 kfree(wal->list); 73 wal->list = list; 74 } 75 } 76 77 if (!wal->count) 78 return; 79 80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 81 wal->wa_count, wal->name, wal->engine_name); 82 } 83 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 85 { 86 unsigned int addr = i915_mmio_reg_offset(wa->reg); 87 unsigned int start = 0, end = wal->count; 88 const unsigned int grow = WA_LIST_CHUNK; 89 struct i915_wa *wa_; 90 91 GEM_BUG_ON(!is_power_of_2(grow)); 92 93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 94 struct i915_wa *list; 95 96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 97 GFP_KERNEL); 98 if (!list) { 99 DRM_ERROR("No space for workaround init!\n"); 100 return; 101 } 102 103 if (wal->list) 104 memcpy(list, wal->list, sizeof(*wa) * wal->count); 105 106 wal->list = list; 107 } 108 109 while (start < end) { 110 unsigned int mid = start + (end - start) / 2; 111 112 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 113 start = mid + 1; 114 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 115 end = mid; 116 } else { 117 wa_ = &wal->list[mid]; 118 119 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 120 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 121 i915_mmio_reg_offset(wa_->reg), 122 wa_->clr, wa_->set); 123 124 wa_->set &= ~wa->clr; 125 } 126 127 wal->wa_count++; 128 wa_->set |= wa->set; 129 wa_->clr |= wa->clr; 130 wa_->read |= wa->read; 131 return; 132 } 133 } 134 135 wal->wa_count++; 136 wa_ = &wal->list[wal->count++]; 137 *wa_ = *wa; 138 139 while (wa_-- > wal->list) { 140 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 141 i915_mmio_reg_offset(wa_[1].reg)); 142 if (i915_mmio_reg_offset(wa_[1].reg) > 143 i915_mmio_reg_offset(wa_[0].reg)) 144 break; 145 146 swap(wa_[1], wa_[0]); 147 } 148 } 149 150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 151 u32 clear, u32 set, u32 read_mask) 152 { 153 struct i915_wa wa = { 154 .reg = reg, 155 .clr = clear, 156 .set = set, 157 .read = read_mask, 158 }; 159 160 _wa_add(wal, &wa); 161 } 162 163 static void 164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 165 { 166 wa_add(wal, reg, clear, set, clear); 167 } 168 169 static void 170 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 171 { 172 wa_write_masked_or(wal, reg, ~0, set); 173 } 174 175 static void 176 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 177 { 178 wa_write_masked_or(wal, reg, set, set); 179 } 180 181 static void 182 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 183 { 184 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 185 } 186 187 static void 188 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 189 { 190 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 191 } 192 193 #define WA_SET_BIT_MASKED(addr, mask) \ 194 wa_masked_en(wal, (addr), (mask)) 195 196 #define WA_CLR_BIT_MASKED(addr, mask) \ 197 wa_masked_dis(wal, (addr), (mask)) 198 199 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 200 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) 201 202 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 203 struct i915_wa_list *wal) 204 { 205 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 206 207 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 208 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 209 210 /* WaDisablePartialInstShootdown:bdw,chv */ 211 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 212 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 213 214 /* Use Force Non-Coherent whenever executing a 3D context. This is a 215 * workaround for for a possible hang in the unlikely event a TLB 216 * invalidation occurs during a PSD flush. 217 */ 218 /* WaForceEnableNonCoherent:bdw,chv */ 219 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 220 WA_SET_BIT_MASKED(HDC_CHICKEN0, 221 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 222 HDC_FORCE_NON_COHERENT); 223 224 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 225 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 226 * polygons in the same 8x4 pixel/sample area to be processed without 227 * stalling waiting for the earlier ones to write to Hierarchical Z 228 * buffer." 229 * 230 * This optimization is off by default for BDW and CHV; turn it on. 231 */ 232 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 233 234 /* Wa4x4STCOptimizationDisable:bdw,chv */ 235 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 236 237 /* 238 * BSpec recommends 8x4 when MSAA is used, 239 * however in practice 16x4 seems fastest. 240 * 241 * Note that PS/WM thread counts depend on the WIZ hashing 242 * disable bit, which we don't touch here, but it's good 243 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 244 */ 245 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 246 GEN6_WIZ_HASHING_MASK, 247 GEN6_WIZ_HASHING_16x4); 248 } 249 250 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 251 struct i915_wa_list *wal) 252 { 253 struct drm_i915_private *i915 = engine->i915; 254 255 gen8_ctx_workarounds_init(engine, wal); 256 257 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 258 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 259 260 /* WaDisableDopClockGating:bdw 261 * 262 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 263 * to disable EUTC clock gating. 264 */ 265 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 266 DOP_CLOCK_GATING_DISABLE); 267 268 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 269 GEN8_SAMPLER_POWER_BYPASS_DIS); 270 271 WA_SET_BIT_MASKED(HDC_CHICKEN0, 272 /* WaForceContextSaveRestoreNonCoherent:bdw */ 273 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 274 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 275 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 276 } 277 278 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 279 struct i915_wa_list *wal) 280 { 281 gen8_ctx_workarounds_init(engine, wal); 282 283 /* WaDisableThreadStallDopClockGating:chv */ 284 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 285 286 /* Improve HiZ throughput on CHV. */ 287 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 288 } 289 290 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 291 struct i915_wa_list *wal) 292 { 293 struct drm_i915_private *i915 = engine->i915; 294 295 if (HAS_LLC(i915)) { 296 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 297 * 298 * Must match Display Engine. See 299 * WaCompressedResourceDisplayNewHashMode. 300 */ 301 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 302 GEN9_PBE_COMPRESSED_HASH_SELECTION); 303 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 304 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 305 } 306 307 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 308 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 309 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 310 FLOW_CONTROL_ENABLE | 311 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 312 313 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 314 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 315 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 316 GEN9_ENABLE_YV12_BUGFIX | 317 GEN9_ENABLE_GPGPU_PREEMPTION); 318 319 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 320 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 321 WA_SET_BIT_MASKED(CACHE_MODE_1, 322 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 323 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 324 325 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 326 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 327 GEN9_CCS_TLB_PREFETCH_ENABLE); 328 329 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 330 WA_SET_BIT_MASKED(HDC_CHICKEN0, 331 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 332 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 333 334 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 335 * both tied to WaForceContextSaveRestoreNonCoherent 336 * in some hsds for skl. We keep the tie for all gen9. The 337 * documentation is a bit hazy and so we want to get common behaviour, 338 * even though there is no clear evidence we would need both on kbl/bxt. 339 * This area has been source of system hangs so we play it safe 340 * and mimic the skl regardless of what bspec says. 341 * 342 * Use Force Non-Coherent whenever executing a 3D context. This 343 * is a workaround for a possible hang in the unlikely event 344 * a TLB invalidation occurs during a PSD flush. 345 */ 346 347 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 348 WA_SET_BIT_MASKED(HDC_CHICKEN0, 349 HDC_FORCE_NON_COHERENT); 350 351 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 352 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) 353 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 354 GEN8_SAMPLER_POWER_BYPASS_DIS); 355 356 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 357 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 358 359 /* 360 * Supporting preemption with fine-granularity requires changes in the 361 * batch buffer programming. Since we can't break old userspace, we 362 * need to set our default preemption level to safe value. Userspace is 363 * still able to use more fine-grained preemption levels, since in 364 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 365 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 366 * not real HW workarounds, but merely a way to start using preemption 367 * while maintaining old contract with userspace. 368 */ 369 370 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 371 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 372 373 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 374 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 375 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 376 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 377 378 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 379 if (IS_GEN9_LP(i915)) 380 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 381 } 382 383 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 384 struct i915_wa_list *wal) 385 { 386 struct drm_i915_private *i915 = engine->i915; 387 u8 vals[3] = { 0, 0, 0 }; 388 unsigned int i; 389 390 for (i = 0; i < 3; i++) { 391 u8 ss; 392 393 /* 394 * Only consider slices where one, and only one, subslice has 7 395 * EUs 396 */ 397 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) 398 continue; 399 400 /* 401 * subslice_7eu[i] != 0 (because of the check above) and 402 * ss_max == 4 (maximum number of subslices possible per slice) 403 * 404 * -> 0 <= ss <= 3; 405 */ 406 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; 407 vals[i] = 3 - ss; 408 } 409 410 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 411 return; 412 413 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 414 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 415 GEN9_IZ_HASHING_MASK(2) | 416 GEN9_IZ_HASHING_MASK(1) | 417 GEN9_IZ_HASHING_MASK(0), 418 GEN9_IZ_HASHING(2, vals[2]) | 419 GEN9_IZ_HASHING(1, vals[1]) | 420 GEN9_IZ_HASHING(0, vals[0])); 421 } 422 423 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 424 struct i915_wa_list *wal) 425 { 426 gen9_ctx_workarounds_init(engine, wal); 427 skl_tune_iz_hashing(engine, wal); 428 } 429 430 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 431 struct i915_wa_list *wal) 432 { 433 gen9_ctx_workarounds_init(engine, wal); 434 435 /* WaDisableThreadStallDopClockGating:bxt */ 436 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 437 STALL_DOP_GATING_DISABLE); 438 439 /* WaToEnableHwFixForPushConstHWBug:bxt */ 440 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 441 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 442 } 443 444 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 445 struct i915_wa_list *wal) 446 { 447 struct drm_i915_private *i915 = engine->i915; 448 449 gen9_ctx_workarounds_init(engine, wal); 450 451 /* WaToEnableHwFixForPushConstHWBug:kbl */ 452 if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 453 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 454 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 455 456 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 457 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 458 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 459 } 460 461 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 462 struct i915_wa_list *wal) 463 { 464 gen9_ctx_workarounds_init(engine, wal); 465 466 /* WaToEnableHwFixForPushConstHWBug:glk */ 467 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 468 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 469 } 470 471 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 472 struct i915_wa_list *wal) 473 { 474 gen9_ctx_workarounds_init(engine, wal); 475 476 /* WaToEnableHwFixForPushConstHWBug:cfl */ 477 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 478 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 479 480 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 481 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 482 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 483 } 484 485 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 486 struct i915_wa_list *wal) 487 { 488 struct drm_i915_private *i915 = engine->i915; 489 490 /* WaForceContextSaveRestoreNonCoherent:cnl */ 491 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, 492 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 493 494 /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */ 495 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0)) 496 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5); 497 498 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 499 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 500 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 501 502 /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */ 503 if (IS_CNL_REVID(i915, 0, CNL_REVID_B0)) 504 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 505 GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE); 506 507 /* WaPushConstantDereferenceHoldDisable:cnl */ 508 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 509 510 /* FtrEnableFastAnisoL1BankingFix:cnl */ 511 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 512 513 /* WaDisable3DMidCmdPreemption:cnl */ 514 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 515 516 /* WaDisableGPGPUMidCmdPreemption:cnl */ 517 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 518 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 519 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 520 521 /* WaDisableEarlyEOT:cnl */ 522 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 523 } 524 525 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 526 struct i915_wa_list *wal) 527 { 528 struct drm_i915_private *i915 = engine->i915; 529 530 /* WaDisableBankHangMode:icl */ 531 wa_write(wal, 532 GEN8_L3CNTLREG, 533 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 534 GEN8_ERRDETBCTRL); 535 536 /* Wa_1604370585:icl (pre-prod) 537 * Formerly known as WaPushConstantDereferenceHoldDisable 538 */ 539 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 540 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 541 PUSH_CONSTANT_DEREF_DISABLE); 542 543 /* WaForceEnableNonCoherent:icl 544 * This is not the same workaround as in early Gen9 platforms, where 545 * lacking this could cause system hangs, but coherency performance 546 * overhead is high and only a few compute workloads really need it 547 * (the register is whitelisted in hardware now, so UMDs can opt in 548 * for coherency if they have a good reason). 549 */ 550 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 551 552 /* Wa_2006611047:icl (pre-prod) 553 * Formerly known as WaDisableImprovedTdlClkGating 554 */ 555 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 556 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 557 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 558 559 /* Wa_2006665173:icl (pre-prod) */ 560 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 561 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 562 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 563 564 /* WaEnableFloatBlendOptimization:icl */ 565 wa_write_masked_or(wal, 566 GEN10_CACHE_MODE_SS, 567 0, /* write-only, so skip validation */ 568 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 569 570 /* WaDisableGPGPUMidThreadPreemption:icl */ 571 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 572 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 573 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 574 575 /* allow headerless messages for preemptible GPGPU context */ 576 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, 577 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 578 } 579 580 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 581 struct i915_wa_list *wal) 582 { 583 u32 val; 584 585 /* Wa_1409142259:tgl */ 586 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 587 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 588 589 /* Wa_1604555607:tgl */ 590 val = intel_uncore_read(engine->uncore, FF_MODE2); 591 val &= ~FF_MODE2_TDS_TIMER_MASK; 592 val |= FF_MODE2_TDS_TIMER_128; 593 /* 594 * FIXME: FF_MODE2 register is not readable till TGL B0. We can 595 * enable verification of WA from the later steppings, which enables 596 * the read of FF_MODE2. 597 */ 598 wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 599 IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 : 600 FF_MODE2_TDS_TIMER_MASK); 601 } 602 603 static void 604 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 605 struct i915_wa_list *wal, 606 const char *name) 607 { 608 struct drm_i915_private *i915 = engine->i915; 609 610 if (engine->class != RENDER_CLASS) 611 return; 612 613 wa_init_start(wal, name, engine->name); 614 615 if (IS_GEN(i915, 12)) 616 tgl_ctx_workarounds_init(engine, wal); 617 else if (IS_GEN(i915, 11)) 618 icl_ctx_workarounds_init(engine, wal); 619 else if (IS_CANNONLAKE(i915)) 620 cnl_ctx_workarounds_init(engine, wal); 621 else if (IS_COFFEELAKE(i915)) 622 cfl_ctx_workarounds_init(engine, wal); 623 else if (IS_GEMINILAKE(i915)) 624 glk_ctx_workarounds_init(engine, wal); 625 else if (IS_KABYLAKE(i915)) 626 kbl_ctx_workarounds_init(engine, wal); 627 else if (IS_BROXTON(i915)) 628 bxt_ctx_workarounds_init(engine, wal); 629 else if (IS_SKYLAKE(i915)) 630 skl_ctx_workarounds_init(engine, wal); 631 else if (IS_CHERRYVIEW(i915)) 632 chv_ctx_workarounds_init(engine, wal); 633 else if (IS_BROADWELL(i915)) 634 bdw_ctx_workarounds_init(engine, wal); 635 else if (INTEL_GEN(i915) < 8) 636 return; 637 else 638 MISSING_CASE(INTEL_GEN(i915)); 639 640 wa_init_finish(wal); 641 } 642 643 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 644 { 645 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 646 } 647 648 int intel_engine_emit_ctx_wa(struct i915_request *rq) 649 { 650 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 651 struct i915_wa *wa; 652 unsigned int i; 653 u32 *cs; 654 int ret; 655 656 if (wal->count == 0) 657 return 0; 658 659 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 660 if (ret) 661 return ret; 662 663 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 664 if (IS_ERR(cs)) 665 return PTR_ERR(cs); 666 667 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 668 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 669 *cs++ = i915_mmio_reg_offset(wa->reg); 670 *cs++ = wa->set; 671 } 672 *cs++ = MI_NOOP; 673 674 intel_ring_advance(rq, cs); 675 676 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 677 if (ret) 678 return ret; 679 680 return 0; 681 } 682 683 static void 684 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 685 { 686 /* WaDisableKillLogic:bxt,skl,kbl */ 687 if (!IS_COFFEELAKE(i915)) 688 wa_write_or(wal, 689 GAM_ECOCHK, 690 ECOCHK_DIS_TLB); 691 692 if (HAS_LLC(i915)) { 693 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 694 * 695 * Must match Display Engine. See 696 * WaCompressedResourceDisplayNewHashMode. 697 */ 698 wa_write_or(wal, 699 MMCD_MISC_CTRL, 700 MMCD_PCLA | MMCD_HOTSPOT_EN); 701 } 702 703 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 704 wa_write_or(wal, 705 GAM_ECOCHK, 706 BDW_DISABLE_HDC_INVALIDATION); 707 } 708 709 static void 710 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 711 { 712 gen9_gt_workarounds_init(i915, wal); 713 714 /* WaDisableGafsUnitClkGating:skl */ 715 wa_write_or(wal, 716 GEN7_UCGCTL4, 717 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 718 719 /* WaInPlaceDecompressionHang:skl */ 720 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 721 wa_write_or(wal, 722 GEN9_GAMT_ECO_REG_RW_IA, 723 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 724 } 725 726 static void 727 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 728 { 729 gen9_gt_workarounds_init(i915, wal); 730 731 /* WaInPlaceDecompressionHang:bxt */ 732 wa_write_or(wal, 733 GEN9_GAMT_ECO_REG_RW_IA, 734 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 735 } 736 737 static void 738 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 739 { 740 gen9_gt_workarounds_init(i915, wal); 741 742 /* WaDisableDynamicCreditSharing:kbl */ 743 if (IS_KBL_REVID(i915, 0, KBL_REVID_B0)) 744 wa_write_or(wal, 745 GAMT_CHKN_BIT_REG, 746 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 747 748 /* WaDisableGafsUnitClkGating:kbl */ 749 wa_write_or(wal, 750 GEN7_UCGCTL4, 751 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 752 753 /* WaInPlaceDecompressionHang:kbl */ 754 wa_write_or(wal, 755 GEN9_GAMT_ECO_REG_RW_IA, 756 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 757 } 758 759 static void 760 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 761 { 762 gen9_gt_workarounds_init(i915, wal); 763 } 764 765 static void 766 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 767 { 768 gen9_gt_workarounds_init(i915, wal); 769 770 /* WaDisableGafsUnitClkGating:cfl */ 771 wa_write_or(wal, 772 GEN7_UCGCTL4, 773 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 774 775 /* WaInPlaceDecompressionHang:cfl */ 776 wa_write_or(wal, 777 GEN9_GAMT_ECO_REG_RW_IA, 778 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 779 } 780 781 static void 782 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 783 { 784 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; 785 unsigned int slice, subslice; 786 u32 l3_en, mcr, mcr_mask; 787 788 GEM_BUG_ON(INTEL_GEN(i915) < 10); 789 790 /* 791 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 792 * L3Banks could be fused off in single slice scenario. If that is 793 * the case, we might need to program MCR select to a valid L3Bank 794 * by default, to make sure we correctly read certain registers 795 * later on (in the range 0xB100 - 0xB3FF). 796 * 797 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 798 * Before any MMIO read into slice/subslice specific registers, MCR 799 * packet control register needs to be programmed to point to any 800 * enabled s/ss pair. Otherwise, incorrect values will be returned. 801 * This means each subsequent MMIO read will be forwarded to an 802 * specific s/ss combination, but this is OK since these registers 803 * are consistent across s/ss in almost all cases. In the rare 804 * occasions, such as INSTDONE, where this value is dependent 805 * on s/ss combo, the read should be done with read_subslice_reg. 806 * 807 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 808 * to which subslice, or to which L3 bank, the respective mmio reads 809 * will go, we have to find a common index which works for both 810 * accesses. 811 * 812 * Case where we cannot find a common index fortunately should not 813 * happen in production hardware, so we only emit a warning instead of 814 * implementing something more complex that requires checking the range 815 * of every MMIO read. 816 */ 817 818 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 819 u32 l3_fuse = 820 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 821 GEN10_L3BANK_MASK; 822 823 DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse); 824 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 825 } else { 826 l3_en = ~0; 827 } 828 829 slice = fls(sseu->slice_mask) - 1; 830 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 831 if (!subslice) { 832 DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n", 833 intel_sseu_get_subslices(sseu, slice), l3_en); 834 subslice = fls(l3_en); 835 drm_WARN_ON(&i915->drm, !subslice); 836 } 837 subslice--; 838 839 if (INTEL_GEN(i915) >= 11) { 840 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 841 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 842 } else { 843 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 844 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 845 } 846 847 DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr); 848 849 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 850 } 851 852 static void 853 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 854 { 855 wa_init_mcr(i915, wal); 856 857 /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */ 858 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0)) 859 wa_write_or(wal, 860 GAMT_CHKN_BIT_REG, 861 GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT); 862 863 /* WaInPlaceDecompressionHang:cnl */ 864 wa_write_or(wal, 865 GEN9_GAMT_ECO_REG_RW_IA, 866 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 867 } 868 869 static void 870 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 871 { 872 wa_init_mcr(i915, wal); 873 874 /* WaInPlaceDecompressionHang:icl */ 875 wa_write_or(wal, 876 GEN9_GAMT_ECO_REG_RW_IA, 877 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 878 879 /* WaModifyGamTlbPartitioning:icl */ 880 wa_write_masked_or(wal, 881 GEN11_GACB_PERF_CTRL, 882 GEN11_HASH_CTRL_MASK, 883 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 884 885 /* Wa_1405766107:icl 886 * Formerly known as WaCL2SFHalfMaxAlloc 887 */ 888 wa_write_or(wal, 889 GEN11_LSN_UNSLCVC, 890 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 891 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 892 893 /* Wa_220166154:icl 894 * Formerly known as WaDisCtxReload 895 */ 896 wa_write_or(wal, 897 GEN8_GAMW_ECO_DEV_RW_IA, 898 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 899 900 /* Wa_1405779004:icl (pre-prod) */ 901 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 902 wa_write_or(wal, 903 SLICE_UNIT_LEVEL_CLKGATE, 904 MSCUNIT_CLKGATE_DIS); 905 906 /* Wa_1406680159:icl */ 907 wa_write_or(wal, 908 SUBSLICE_UNIT_LEVEL_CLKGATE, 909 GWUNIT_CLKGATE_DIS); 910 911 /* Wa_1406838659:icl (pre-prod) */ 912 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 913 wa_write_or(wal, 914 INF_UNIT_LEVEL_CLKGATE, 915 CGPSF_CLKGATE_DIS); 916 917 /* Wa_1406463099:icl 918 * Formerly known as WaGamTlbPendError 919 */ 920 wa_write_or(wal, 921 GAMT_CHKN_BIT_REG, 922 GAMT_CHKN_DISABLE_L3_COH_PIPE); 923 924 /* Wa_1607087056:icl */ 925 wa_write_or(wal, 926 SLICE_UNIT_LEVEL_CLKGATE, 927 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 928 } 929 930 static void 931 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 932 { 933 /* Wa_1409420604:tgl */ 934 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 935 wa_write_or(wal, 936 SUBSLICE_UNIT_LEVEL_CLKGATE2, 937 CPSSUNIT_CLKGATE_DIS); 938 939 /* Wa_1409180338:tgl */ 940 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 941 wa_write_or(wal, 942 SLICE_UNIT_LEVEL_CLKGATE, 943 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 944 } 945 946 static void 947 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 948 { 949 if (IS_GEN(i915, 12)) 950 tgl_gt_workarounds_init(i915, wal); 951 else if (IS_GEN(i915, 11)) 952 icl_gt_workarounds_init(i915, wal); 953 else if (IS_CANNONLAKE(i915)) 954 cnl_gt_workarounds_init(i915, wal); 955 else if (IS_COFFEELAKE(i915)) 956 cfl_gt_workarounds_init(i915, wal); 957 else if (IS_GEMINILAKE(i915)) 958 glk_gt_workarounds_init(i915, wal); 959 else if (IS_KABYLAKE(i915)) 960 kbl_gt_workarounds_init(i915, wal); 961 else if (IS_BROXTON(i915)) 962 bxt_gt_workarounds_init(i915, wal); 963 else if (IS_SKYLAKE(i915)) 964 skl_gt_workarounds_init(i915, wal); 965 else if (INTEL_GEN(i915) <= 8) 966 return; 967 else 968 MISSING_CASE(INTEL_GEN(i915)); 969 } 970 971 void intel_gt_init_workarounds(struct drm_i915_private *i915) 972 { 973 struct i915_wa_list *wal = &i915->gt_wa_list; 974 975 wa_init_start(wal, "GT", "global"); 976 gt_init_workarounds(i915, wal); 977 wa_init_finish(wal); 978 } 979 980 static enum forcewake_domains 981 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 982 { 983 enum forcewake_domains fw = 0; 984 struct i915_wa *wa; 985 unsigned int i; 986 987 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 988 fw |= intel_uncore_forcewake_for_reg(uncore, 989 wa->reg, 990 FW_REG_READ | 991 FW_REG_WRITE); 992 993 return fw; 994 } 995 996 static bool 997 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 998 { 999 if ((cur ^ wa->set) & wa->read) { 1000 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n", 1001 name, from, i915_mmio_reg_offset(wa->reg), 1002 cur, cur & wa->read, wa->set); 1003 1004 return false; 1005 } 1006 1007 return true; 1008 } 1009 1010 static void 1011 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1012 { 1013 enum forcewake_domains fw; 1014 unsigned long flags; 1015 struct i915_wa *wa; 1016 unsigned int i; 1017 1018 if (!wal->count) 1019 return; 1020 1021 fw = wal_get_fw_for_rmw(uncore, wal); 1022 1023 spin_lock_irqsave(&uncore->lock, flags); 1024 intel_uncore_forcewake_get__locked(uncore, fw); 1025 1026 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1027 if (wa->clr) 1028 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1029 else 1030 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1031 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1032 wa_verify(wa, 1033 intel_uncore_read_fw(uncore, wa->reg), 1034 wal->name, "application"); 1035 } 1036 1037 intel_uncore_forcewake_put__locked(uncore, fw); 1038 spin_unlock_irqrestore(&uncore->lock, flags); 1039 } 1040 1041 void intel_gt_apply_workarounds(struct intel_gt *gt) 1042 { 1043 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1044 } 1045 1046 static bool wa_list_verify(struct intel_uncore *uncore, 1047 const struct i915_wa_list *wal, 1048 const char *from) 1049 { 1050 struct i915_wa *wa; 1051 unsigned int i; 1052 bool ok = true; 1053 1054 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1055 ok &= wa_verify(wa, 1056 intel_uncore_read(uncore, wa->reg), 1057 wal->name, from); 1058 1059 return ok; 1060 } 1061 1062 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1063 { 1064 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1065 } 1066 1067 static inline bool is_nonpriv_flags_valid(u32 flags) 1068 { 1069 /* Check only valid flag bits are set */ 1070 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1071 return false; 1072 1073 /* NB: Only 3 out of 4 enum values are valid for access field */ 1074 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1075 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1076 return false; 1077 1078 return true; 1079 } 1080 1081 static void 1082 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1083 { 1084 struct i915_wa wa = { 1085 .reg = reg 1086 }; 1087 1088 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1089 return; 1090 1091 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1092 return; 1093 1094 wa.reg.reg |= flags; 1095 _wa_add(wal, &wa); 1096 } 1097 1098 static void 1099 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1100 { 1101 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1102 } 1103 1104 static void gen9_whitelist_build(struct i915_wa_list *w) 1105 { 1106 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1107 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1108 1109 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1110 whitelist_reg(w, GEN8_CS_CHICKEN1); 1111 1112 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1113 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1114 1115 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1116 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1117 } 1118 1119 static void skl_whitelist_build(struct intel_engine_cs *engine) 1120 { 1121 struct i915_wa_list *w = &engine->whitelist; 1122 1123 if (engine->class != RENDER_CLASS) 1124 return; 1125 1126 gen9_whitelist_build(w); 1127 1128 /* WaDisableLSQCROPERFforOCL:skl */ 1129 whitelist_reg(w, GEN8_L3SQCREG4); 1130 } 1131 1132 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1133 { 1134 if (engine->class != RENDER_CLASS) 1135 return; 1136 1137 gen9_whitelist_build(&engine->whitelist); 1138 } 1139 1140 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1141 { 1142 struct i915_wa_list *w = &engine->whitelist; 1143 1144 if (engine->class != RENDER_CLASS) 1145 return; 1146 1147 gen9_whitelist_build(w); 1148 1149 /* WaDisableLSQCROPERFforOCL:kbl */ 1150 whitelist_reg(w, GEN8_L3SQCREG4); 1151 } 1152 1153 static void glk_whitelist_build(struct intel_engine_cs *engine) 1154 { 1155 struct i915_wa_list *w = &engine->whitelist; 1156 1157 if (engine->class != RENDER_CLASS) 1158 return; 1159 1160 gen9_whitelist_build(w); 1161 1162 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1163 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1164 } 1165 1166 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1167 { 1168 struct i915_wa_list *w = &engine->whitelist; 1169 1170 if (engine->class != RENDER_CLASS) 1171 return; 1172 1173 gen9_whitelist_build(w); 1174 1175 /* 1176 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1177 * 1178 * This covers 4 register which are next to one another : 1179 * - PS_INVOCATION_COUNT 1180 * - PS_INVOCATION_COUNT_UDW 1181 * - PS_DEPTH_COUNT 1182 * - PS_DEPTH_COUNT_UDW 1183 */ 1184 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1185 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1186 RING_FORCE_TO_NONPRIV_RANGE_4); 1187 } 1188 1189 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1190 { 1191 struct i915_wa_list *w = &engine->whitelist; 1192 1193 if (engine->class != RENDER_CLASS) 1194 return; 1195 1196 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1197 whitelist_reg(w, GEN8_CS_CHICKEN1); 1198 } 1199 1200 static void icl_whitelist_build(struct intel_engine_cs *engine) 1201 { 1202 struct i915_wa_list *w = &engine->whitelist; 1203 1204 switch (engine->class) { 1205 case RENDER_CLASS: 1206 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1207 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1208 1209 /* WaAllowUMDToModifySamplerMode:icl */ 1210 whitelist_reg(w, GEN10_SAMPLER_MODE); 1211 1212 /* WaEnableStateCacheRedirectToCS:icl */ 1213 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1214 1215 /* 1216 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1217 * 1218 * This covers 4 register which are next to one another : 1219 * - PS_INVOCATION_COUNT 1220 * - PS_INVOCATION_COUNT_UDW 1221 * - PS_DEPTH_COUNT 1222 * - PS_DEPTH_COUNT_UDW 1223 */ 1224 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1225 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1226 RING_FORCE_TO_NONPRIV_RANGE_4); 1227 break; 1228 1229 case VIDEO_DECODE_CLASS: 1230 /* hucStatusRegOffset */ 1231 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1232 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1233 /* hucUKernelHdrInfoRegOffset */ 1234 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1235 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1236 /* hucStatus2RegOffset */ 1237 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1238 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1239 break; 1240 1241 default: 1242 break; 1243 } 1244 } 1245 1246 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1247 { 1248 struct i915_wa_list *w = &engine->whitelist; 1249 1250 switch (engine->class) { 1251 case RENDER_CLASS: 1252 /* 1253 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1254 * 1255 * This covers 4 registers which are next to one another : 1256 * - PS_INVOCATION_COUNT 1257 * - PS_INVOCATION_COUNT_UDW 1258 * - PS_DEPTH_COUNT 1259 * - PS_DEPTH_COUNT_UDW 1260 */ 1261 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1262 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1263 RING_FORCE_TO_NONPRIV_RANGE_4); 1264 1265 /* Wa_1808121037:tgl */ 1266 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1267 break; 1268 default: 1269 break; 1270 } 1271 } 1272 1273 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1274 { 1275 struct drm_i915_private *i915 = engine->i915; 1276 struct i915_wa_list *w = &engine->whitelist; 1277 1278 wa_init_start(w, "whitelist", engine->name); 1279 1280 if (IS_GEN(i915, 12)) 1281 tgl_whitelist_build(engine); 1282 else if (IS_GEN(i915, 11)) 1283 icl_whitelist_build(engine); 1284 else if (IS_CANNONLAKE(i915)) 1285 cnl_whitelist_build(engine); 1286 else if (IS_COFFEELAKE(i915)) 1287 cfl_whitelist_build(engine); 1288 else if (IS_GEMINILAKE(i915)) 1289 glk_whitelist_build(engine); 1290 else if (IS_KABYLAKE(i915)) 1291 kbl_whitelist_build(engine); 1292 else if (IS_BROXTON(i915)) 1293 bxt_whitelist_build(engine); 1294 else if (IS_SKYLAKE(i915)) 1295 skl_whitelist_build(engine); 1296 else if (INTEL_GEN(i915) <= 8) 1297 return; 1298 else 1299 MISSING_CASE(INTEL_GEN(i915)); 1300 1301 wa_init_finish(w); 1302 } 1303 1304 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1305 { 1306 const struct i915_wa_list *wal = &engine->whitelist; 1307 struct intel_uncore *uncore = engine->uncore; 1308 const u32 base = engine->mmio_base; 1309 struct i915_wa *wa; 1310 unsigned int i; 1311 1312 if (!wal->count) 1313 return; 1314 1315 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1316 intel_uncore_write(uncore, 1317 RING_FORCE_TO_NONPRIV(base, i), 1318 i915_mmio_reg_offset(wa->reg)); 1319 1320 /* And clear the rest just in case of garbage */ 1321 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1322 intel_uncore_write(uncore, 1323 RING_FORCE_TO_NONPRIV(base, i), 1324 i915_mmio_reg_offset(RING_NOPID(base))); 1325 } 1326 1327 static void 1328 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1329 { 1330 struct drm_i915_private *i915 = engine->i915; 1331 1332 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1333 /* Wa_1606700617:tgl */ 1334 wa_masked_en(wal, 1335 GEN9_CS_DEBUG_MODE1, 1336 FF_DOP_CLOCK_GATE_DISABLE); 1337 1338 /* Wa_1607138336:tgl */ 1339 wa_write_or(wal, 1340 GEN9_CTX_PREEMPT_REG, 1341 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1342 1343 /* Wa_1607030317:tgl */ 1344 /* Wa_1607186500:tgl */ 1345 /* Wa_1607297627:tgl */ 1346 wa_masked_en(wal, 1347 GEN6_RC_SLEEP_PSMI_CONTROL, 1348 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1349 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1350 1351 /* 1352 * Wa_1606679103:tgl 1353 * (see also Wa_1606682166:icl) 1354 */ 1355 wa_write_or(wal, 1356 GEN7_SARCHKMD, 1357 GEN7_DISABLE_SAMPLER_PREFETCH); 1358 1359 /* Wa_1407928979:tgl */ 1360 wa_write_or(wal, 1361 GEN7_FF_THREAD_MODE, 1362 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1363 1364 /* Wa_1606931601:tgl */ 1365 wa_masked_en(wal, 1366 GEN7_ROW_CHICKEN2, 1367 GEN12_DISABLE_EARLY_READ); 1368 } 1369 1370 if (IS_GEN(i915, 11)) { 1371 /* This is not an Wa. Enable for better image quality */ 1372 wa_masked_en(wal, 1373 _3D_CHICKEN3, 1374 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1375 1376 /* WaPipelineFlushCoherentLines:icl */ 1377 wa_write_or(wal, 1378 GEN8_L3SQCREG4, 1379 GEN8_LQSC_FLUSH_COHERENT_LINES); 1380 1381 /* 1382 * Wa_1405543622:icl 1383 * Formerly known as WaGAPZPriorityScheme 1384 */ 1385 wa_write_or(wal, 1386 GEN8_GARBCNTL, 1387 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1388 1389 /* 1390 * Wa_1604223664:icl 1391 * Formerly known as WaL3BankAddressHashing 1392 */ 1393 wa_write_masked_or(wal, 1394 GEN8_GARBCNTL, 1395 GEN11_HASH_CTRL_EXCL_MASK, 1396 GEN11_HASH_CTRL_EXCL_BIT0); 1397 wa_write_masked_or(wal, 1398 GEN11_GLBLINVL, 1399 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1400 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1401 1402 /* 1403 * Wa_1405733216:icl 1404 * Formerly known as WaDisableCleanEvicts 1405 */ 1406 wa_write_or(wal, 1407 GEN8_L3SQCREG4, 1408 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1409 1410 /* WaForwardProgressSoftReset:icl */ 1411 wa_write_or(wal, 1412 GEN10_SCRATCH_LNCF2, 1413 PMFLUSHDONE_LNICRSDROP | 1414 PMFLUSH_GAPL3UNBLOCK | 1415 PMFLUSHDONE_LNEBLK); 1416 1417 /* Wa_1406609255:icl (pre-prod) */ 1418 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1419 wa_write_or(wal, 1420 GEN7_SARCHKMD, 1421 GEN7_DISABLE_DEMAND_PREFETCH); 1422 1423 /* Wa_1606682166:icl */ 1424 wa_write_or(wal, 1425 GEN7_SARCHKMD, 1426 GEN7_DISABLE_SAMPLER_PREFETCH); 1427 1428 /* Wa_1409178092:icl */ 1429 wa_write_masked_or(wal, 1430 GEN11_SCRATCH2, 1431 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1432 0); 1433 } 1434 1435 if (IS_GEN_RANGE(i915, 9, 11)) { 1436 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl */ 1437 wa_masked_en(wal, 1438 GEN7_FF_SLICE_CS_CHICKEN1, 1439 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1440 } 1441 1442 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { 1443 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1444 wa_write_or(wal, 1445 GEN8_GARBCNTL, 1446 GEN9_GAPS_TSV_CREDIT_DISABLE); 1447 } 1448 1449 if (IS_BROXTON(i915)) { 1450 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1451 wa_masked_en(wal, 1452 FF_SLICE_CS_CHICKEN2, 1453 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1454 } 1455 1456 if (IS_GEN(i915, 9)) { 1457 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1458 wa_masked_en(wal, 1459 GEN9_CSFE_CHICKEN1_RCS, 1460 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1461 1462 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1463 wa_write_or(wal, 1464 BDW_SCRATCH1, 1465 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1466 1467 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1468 if (IS_GEN9_LP(i915)) 1469 wa_write_masked_or(wal, 1470 GEN8_L3SQCREG1, 1471 L3_PRIO_CREDITS_MASK, 1472 L3_GENERAL_PRIO_CREDITS(62) | 1473 L3_HIGH_PRIO_CREDITS(2)); 1474 1475 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1476 wa_write_or(wal, 1477 GEN8_L3SQCREG4, 1478 GEN8_LQSC_FLUSH_COHERENT_LINES); 1479 } 1480 1481 if (IS_GEN(i915, 7)) 1482 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1483 wa_masked_en(wal, 1484 GFX_MODE_GEN7, 1485 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1486 1487 if (IS_GEN_RANGE(i915, 6, 7)) 1488 /* 1489 * We need to disable the AsyncFlip performance optimisations in 1490 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1491 * already be programmed to '1' on all products. 1492 * 1493 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1494 */ 1495 wa_masked_en(wal, 1496 MI_MODE, 1497 ASYNC_FLIP_PERF_DISABLE); 1498 1499 if (IS_GEN(i915, 6)) { 1500 /* 1501 * Required for the hardware to program scanline values for 1502 * waiting 1503 * WaEnableFlushTlbInvalidationMode:snb 1504 */ 1505 wa_masked_en(wal, 1506 GFX_MODE, 1507 GFX_TLB_INVALIDATE_EXPLICIT); 1508 1509 /* 1510 * From the Sandybridge PRM, volume 1 part 3, page 24: 1511 * "If this bit is set, STCunit will have LRA as replacement 1512 * policy. [...] This bit must be reset. LRA replacement 1513 * policy is not supported." 1514 */ 1515 wa_masked_dis(wal, 1516 CACHE_MODE_0, 1517 CM0_STC_EVICT_DISABLE_LRA_SNB); 1518 } 1519 1520 if (IS_GEN_RANGE(i915, 4, 6)) 1521 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 1522 wa_add(wal, MI_MODE, 1523 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 1524 /* XXX bit doesn't stick on Broadwater */ 1525 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 1526 } 1527 1528 static void 1529 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1530 { 1531 struct drm_i915_private *i915 = engine->i915; 1532 1533 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 1534 if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 1535 wa_write(wal, 1536 RING_SEMA_WAIT_POLL(engine->mmio_base), 1537 1); 1538 } 1539 } 1540 1541 static void 1542 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1543 { 1544 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 1545 return; 1546 1547 if (engine->class == RENDER_CLASS) 1548 rcs_engine_wa_init(engine, wal); 1549 else 1550 xcs_engine_wa_init(engine, wal); 1551 } 1552 1553 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 1554 { 1555 struct i915_wa_list *wal = &engine->wa_list; 1556 1557 if (INTEL_GEN(engine->i915) < 4) 1558 return; 1559 1560 wa_init_start(wal, "engine", engine->name); 1561 engine_init_workarounds(engine, wal); 1562 wa_init_finish(wal); 1563 } 1564 1565 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 1566 { 1567 wa_list_apply(engine->uncore, &engine->wa_list); 1568 } 1569 1570 static struct i915_vma * 1571 create_scratch(struct i915_address_space *vm, int count) 1572 { 1573 struct drm_i915_gem_object *obj; 1574 struct i915_vma *vma; 1575 unsigned int size; 1576 int err; 1577 1578 size = round_up(count * sizeof(u32), PAGE_SIZE); 1579 obj = i915_gem_object_create_internal(vm->i915, size); 1580 if (IS_ERR(obj)) 1581 return ERR_CAST(obj); 1582 1583 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 1584 1585 vma = i915_vma_instance(obj, vm, NULL); 1586 if (IS_ERR(vma)) { 1587 err = PTR_ERR(vma); 1588 goto err_obj; 1589 } 1590 1591 err = i915_vma_pin(vma, 0, 0, 1592 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 1593 if (err) 1594 goto err_obj; 1595 1596 return vma; 1597 1598 err_obj: 1599 i915_gem_object_put(obj); 1600 return ERR_PTR(err); 1601 } 1602 1603 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 1604 { 1605 /* 1606 * Registers in this range are affected by the MCR selector 1607 * which only controls CPU initiated MMIO. Routing does not 1608 * work for CS access so we cannot verify them on this path. 1609 */ 1610 if (INTEL_GEN(i915) >= 8 && (offset >= 0xb000 && offset <= 0xb4ff)) 1611 return true; 1612 1613 return false; 1614 } 1615 1616 static int 1617 wa_list_srm(struct i915_request *rq, 1618 const struct i915_wa_list *wal, 1619 struct i915_vma *vma) 1620 { 1621 struct drm_i915_private *i915 = rq->i915; 1622 unsigned int i, count = 0; 1623 const struct i915_wa *wa; 1624 u32 srm, *cs; 1625 1626 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 1627 if (INTEL_GEN(i915) >= 8) 1628 srm++; 1629 1630 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1631 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 1632 count++; 1633 } 1634 1635 cs = intel_ring_begin(rq, 4 * count); 1636 if (IS_ERR(cs)) 1637 return PTR_ERR(cs); 1638 1639 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1640 u32 offset = i915_mmio_reg_offset(wa->reg); 1641 1642 if (mcr_range(i915, offset)) 1643 continue; 1644 1645 *cs++ = srm; 1646 *cs++ = offset; 1647 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 1648 *cs++ = 0; 1649 } 1650 intel_ring_advance(rq, cs); 1651 1652 return 0; 1653 } 1654 1655 static int engine_wa_list_verify(struct intel_context *ce, 1656 const struct i915_wa_list * const wal, 1657 const char *from) 1658 { 1659 const struct i915_wa *wa; 1660 struct i915_request *rq; 1661 struct i915_vma *vma; 1662 unsigned int i; 1663 u32 *results; 1664 int err; 1665 1666 if (!wal->count) 1667 return 0; 1668 1669 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count); 1670 if (IS_ERR(vma)) 1671 return PTR_ERR(vma); 1672 1673 intel_engine_pm_get(ce->engine); 1674 rq = intel_context_create_request(ce); 1675 intel_engine_pm_put(ce->engine); 1676 if (IS_ERR(rq)) { 1677 err = PTR_ERR(rq); 1678 goto err_vma; 1679 } 1680 1681 i915_vma_lock(vma); 1682 err = i915_request_await_object(rq, vma->obj, true); 1683 if (err == 0) 1684 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 1685 i915_vma_unlock(vma); 1686 if (err) { 1687 i915_request_add(rq); 1688 goto err_vma; 1689 } 1690 1691 err = wa_list_srm(rq, wal, vma); 1692 if (err) 1693 goto err_vma; 1694 1695 i915_request_get(rq); 1696 i915_request_add(rq); 1697 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 1698 err = -ETIME; 1699 goto err_rq; 1700 } 1701 1702 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 1703 if (IS_ERR(results)) { 1704 err = PTR_ERR(results); 1705 goto err_rq; 1706 } 1707 1708 err = 0; 1709 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1710 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) 1711 continue; 1712 1713 if (!wa_verify(wa, results[i], wal->name, from)) 1714 err = -ENXIO; 1715 } 1716 1717 i915_gem_object_unpin_map(vma->obj); 1718 1719 err_rq: 1720 i915_request_put(rq); 1721 err_vma: 1722 i915_vma_unpin(vma); 1723 i915_vma_put(vma); 1724 return err; 1725 } 1726 1727 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 1728 const char *from) 1729 { 1730 return engine_wa_list_verify(engine->kernel_context, 1731 &engine->wa_list, 1732 from); 1733 } 1734 1735 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1736 #include "selftest_workarounds.c" 1737 #endif 1738