xref: /linux/drivers/gpu/drm/i915/gt/intel_timeline.h (revision 07fdad3a93756b872da7b53647715c48d0f4a2d0) 
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2016 Intel Corporation
4  */
5 
6 #ifndef I915_TIMELINE_H
7 #define I915_TIMELINE_H
8 
9 #include <linux/lockdep.h>
10 
11 #include "i915_active.h"
12 #include "i915_list_util.h"
13 #include "i915_syncmap.h"
14 #include "intel_timeline_types.h"
15 
16 struct drm_printer;
17 
18 struct intel_timeline *
19 __intel_timeline_create(struct intel_gt *gt,
20 			struct i915_vma *global_hwsp,
21 			unsigned int offset);
22 
23 static inline struct intel_timeline *
24 intel_timeline_create(struct intel_gt *gt)
25 {
26 	return __intel_timeline_create(gt, NULL, 0);
27 }
28 
29 struct intel_timeline *
30 intel_timeline_create_from_engine(struct intel_engine_cs *engine,
31 				  unsigned int offset);
32 
33 static inline struct intel_timeline *
34 intel_timeline_get(struct intel_timeline *timeline)
35 {
36 	kref_get(&timeline->kref);
37 	return timeline;
38 }
39 
40 void __intel_timeline_free(struct kref *kref);
41 static inline void intel_timeline_put(struct intel_timeline *timeline)
42 {
43 	kref_put(&timeline->kref, __intel_timeline_free);
44 }
45 
46 static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
47 					    u64 context, u32 seqno)
48 {
49 	return i915_syncmap_set(&tl->sync, context, seqno);
50 }
51 
52 static inline int intel_timeline_sync_set(struct intel_timeline *tl,
53 					  const struct dma_fence *fence)
54 {
55 	return __intel_timeline_sync_set(tl, fence->context, fence->seqno);
56 }
57 
58 static inline bool __intel_timeline_sync_is_later(struct intel_timeline *tl,
59 						  u64 context, u32 seqno)
60 {
61 	return i915_syncmap_is_later(&tl->sync, context, seqno);
62 }
63 
64 static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl,
65 						const struct dma_fence *fence)
66 {
67 	return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno);
68 }
69 
70 void __intel_timeline_pin(struct intel_timeline *tl);
71 int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww);
72 void intel_timeline_enter(struct intel_timeline *tl);
73 int intel_timeline_get_seqno(struct intel_timeline *tl,
74 			     struct i915_request *rq,
75 			     u32 *seqno);
76 void intel_timeline_exit(struct intel_timeline *tl);
77 void intel_timeline_unpin(struct intel_timeline *tl);
78 
79 void intel_timeline_reset_seqno(const struct intel_timeline *tl);
80 
81 int intel_timeline_read_hwsp(struct i915_request *from,
82 			     struct i915_request *until,
83 			     u32 *hwsp_offset);
84 
85 void intel_gt_init_timelines(struct intel_gt *gt);
86 void intel_gt_fini_timelines(struct intel_gt *gt);
87 
88 void intel_gt_show_timelines(struct intel_gt *gt,
89 			     struct drm_printer *m,
90 			     void (*show_request)(struct drm_printer *m,
91 						  const struct i915_request *rq,
92 						  const char *prefix,
93 						  int indent));
94 
95 static inline bool
96 intel_timeline_is_last(const struct intel_timeline *tl,
97 		       const struct i915_request *rq)
98 {
99 	return list_is_last_rcu(&rq->link, &tl->requests);
100 }
101 
102 I915_SELFTEST_DECLARE(int intel_timeline_pin_map(struct intel_timeline *tl));
103 
104 #endif
105