1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #ifndef __INTEL_SSEU_H__ 8 #define __INTEL_SSEU_H__ 9 10 #include <linux/types.h> 11 #include <linux/kernel.h> 12 13 #include "i915_gem.h" 14 15 struct drm_i915_private; 16 struct intel_gt; 17 struct drm_printer; 18 19 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 20 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ 21 #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) 22 #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) 23 #define GEN_MAX_EUS (16) /* TGL upper bound */ 24 #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS) 25 26 struct sseu_dev_info { 27 u8 slice_mask; 28 u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE]; 29 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE]; 30 u16 eu_total; 31 u8 eu_per_subslice; 32 u8 min_eu_in_pool; 33 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 34 u8 subslice_7eu[3]; 35 u8 has_slice_pg:1; 36 u8 has_subslice_pg:1; 37 u8 has_eu_pg:1; 38 39 /* Topology fields */ 40 u8 max_slices; 41 u8 max_subslices; 42 u8 max_eus_per_subslice; 43 44 u8 ss_stride; 45 u8 eu_stride; 46 }; 47 48 /* 49 * Powergating configuration for a particular (context,engine). 50 */ 51 struct intel_sseu { 52 u8 slice_mask; 53 u8 subslice_mask; 54 u8 min_eus_per_subslice; 55 u8 max_eus_per_subslice; 56 }; 57 58 static inline struct intel_sseu 59 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) 60 { 61 struct intel_sseu value = { 62 .slice_mask = sseu->slice_mask, 63 .subslice_mask = sseu->subslice_mask[0], 64 .min_eus_per_subslice = sseu->max_eus_per_subslice, 65 .max_eus_per_subslice = sseu->max_eus_per_subslice, 66 }; 67 68 return value; 69 } 70 71 static inline bool 72 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, 73 int subslice) 74 { 75 u8 mask; 76 int ss_idx = subslice / BITS_PER_BYTE; 77 78 GEM_BUG_ON(ss_idx >= sseu->ss_stride); 79 80 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; 81 82 return mask & BIT(subslice % BITS_PER_BYTE); 83 } 84 85 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, 86 u8 max_subslices, u8 max_eus_per_subslice); 87 88 unsigned int 89 intel_sseu_subslice_total(const struct sseu_dev_info *sseu); 90 91 unsigned int 92 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); 93 94 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice); 95 96 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, 97 u32 ss_mask); 98 99 void intel_sseu_info_init(struct intel_gt *gt); 100 101 u32 intel_sseu_make_rpcs(struct intel_gt *gt, 102 const struct intel_sseu *req_sseu); 103 104 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); 105 void intel_sseu_print_topology(const struct sseu_dev_info *sseu, 106 struct drm_printer *p); 107 108 #endif /* __INTEL_SSEU_H__ */ 109