1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include <drm/intel/i915_drm.h> 9 10 #include "display/intel_display.h" 11 #include "display/intel_display_irq.h" 12 #include "i915_drv.h" 13 #include "i915_irq.h" 14 #include "i915_reg.h" 15 #include "intel_breadcrumbs.h" 16 #include "intel_gt.h" 17 #include "intel_gt_clock_utils.h" 18 #include "intel_gt_irq.h" 19 #include "intel_gt_pm.h" 20 #include "intel_gt_pm_irq.h" 21 #include "intel_gt_print.h" 22 #include "intel_gt_regs.h" 23 #include "intel_mchbar_regs.h" 24 #include "intel_pcode.h" 25 #include "intel_rps.h" 26 #include "vlv_sideband.h" 27 #include "../../../platform/x86/intel_ips.h" 28 29 #define BUSY_MAX_EI 20u /* ms */ 30 31 /* 32 * Lock protecting IPS related data structures 33 */ 34 static DEFINE_SPINLOCK(mchdev_lock); 35 36 static struct intel_gt *rps_to_gt(struct intel_rps *rps) 37 { 38 return container_of(rps, struct intel_gt, rps); 39 } 40 41 static struct drm_i915_private *rps_to_i915(struct intel_rps *rps) 42 { 43 return rps_to_gt(rps)->i915; 44 } 45 46 static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) 47 { 48 return rps_to_gt(rps)->uncore; 49 } 50 51 static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps) 52 { 53 struct intel_gt *gt = rps_to_gt(rps); 54 55 return >_to_guc(gt)->slpc; 56 } 57 58 static bool rps_uses_slpc(struct intel_rps *rps) 59 { 60 struct intel_gt *gt = rps_to_gt(rps); 61 62 return intel_uc_uses_guc_slpc(>->uc); 63 } 64 65 static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask) 66 { 67 return mask & ~rps->pm_intrmsk_mbz; 68 } 69 70 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) 71 { 72 intel_uncore_write_fw(uncore, reg, val); 73 } 74 75 static void rps_timer(struct timer_list *t) 76 { 77 struct intel_rps *rps = from_timer(rps, t, timer); 78 struct intel_gt *gt = rps_to_gt(rps); 79 struct intel_engine_cs *engine; 80 ktime_t dt, last, timestamp; 81 enum intel_engine_id id; 82 s64 max_busy[3] = {}; 83 84 timestamp = 0; 85 for_each_engine(engine, gt, id) { 86 s64 busy; 87 int i; 88 89 dt = intel_engine_get_busy_time(engine, ×tamp); 90 last = engine->stats.rps; 91 engine->stats.rps = dt; 92 93 busy = ktime_to_ns(ktime_sub(dt, last)); 94 for (i = 0; i < ARRAY_SIZE(max_busy); i++) { 95 if (busy > max_busy[i]) 96 swap(busy, max_busy[i]); 97 } 98 } 99 last = rps->pm_timestamp; 100 rps->pm_timestamp = timestamp; 101 102 if (intel_rps_is_active(rps)) { 103 s64 busy; 104 int i; 105 106 dt = ktime_sub(timestamp, last); 107 108 /* 109 * Our goal is to evaluate each engine independently, so we run 110 * at the lowest clocks required to sustain the heaviest 111 * workload. However, a task may be split into sequential 112 * dependent operations across a set of engines, such that 113 * the independent contributions do not account for high load, 114 * but overall the task is GPU bound. For example, consider 115 * video decode on vcs followed by colour post-processing 116 * on vecs, followed by general post-processing on rcs. 117 * Since multi-engines being active does imply a single 118 * continuous workload across all engines, we hedge our 119 * bets by only contributing a factor of the distributed 120 * load into our busyness calculation. 121 */ 122 busy = max_busy[0]; 123 for (i = 1; i < ARRAY_SIZE(max_busy); i++) { 124 if (!max_busy[i]) 125 break; 126 127 busy += div_u64(max_busy[i], 1 << i); 128 } 129 GT_TRACE(gt, 130 "busy:%lld [%d%%], max:[%lld, %lld, %lld], interval:%d\n", 131 busy, (int)div64_u64(100 * busy, dt), 132 max_busy[0], max_busy[1], max_busy[2], 133 rps->pm_interval); 134 135 if (100 * busy > rps->power.up_threshold * dt && 136 rps->cur_freq < rps->max_freq_softlimit) { 137 rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD; 138 rps->pm_interval = 1; 139 queue_work(gt->i915->unordered_wq, &rps->work); 140 } else if (100 * busy < rps->power.down_threshold * dt && 141 rps->cur_freq > rps->min_freq_softlimit) { 142 rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD; 143 rps->pm_interval = 1; 144 queue_work(gt->i915->unordered_wq, &rps->work); 145 } else { 146 rps->last_adj = 0; 147 } 148 149 mod_timer(&rps->timer, 150 jiffies + msecs_to_jiffies(rps->pm_interval)); 151 rps->pm_interval = min(rps->pm_interval * 2, BUSY_MAX_EI); 152 } 153 } 154 155 static void rps_start_timer(struct intel_rps *rps) 156 { 157 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); 158 rps->pm_interval = 1; 159 mod_timer(&rps->timer, jiffies + 1); 160 } 161 162 static void rps_stop_timer(struct intel_rps *rps) 163 { 164 timer_delete_sync(&rps->timer); 165 rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); 166 cancel_work_sync(&rps->work); 167 } 168 169 static u32 rps_pm_mask(struct intel_rps *rps, u8 val) 170 { 171 u32 mask = 0; 172 173 /* We use UP_EI_EXPIRED interrupts for both up/down in manual mode */ 174 if (val > rps->min_freq_softlimit) 175 mask |= (GEN6_PM_RP_UP_EI_EXPIRED | 176 GEN6_PM_RP_DOWN_THRESHOLD | 177 GEN6_PM_RP_DOWN_TIMEOUT); 178 179 if (val < rps->max_freq_softlimit) 180 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 181 182 mask &= rps->pm_events; 183 184 return rps_pm_sanitize_mask(rps, ~mask); 185 } 186 187 static void rps_reset_ei(struct intel_rps *rps) 188 { 189 memset(&rps->ei, 0, sizeof(rps->ei)); 190 } 191 192 static void rps_enable_interrupts(struct intel_rps *rps) 193 { 194 struct intel_gt *gt = rps_to_gt(rps); 195 196 GEM_BUG_ON(rps_uses_slpc(rps)); 197 198 GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", 199 rps->pm_events, rps_pm_mask(rps, rps->last_freq)); 200 201 rps_reset_ei(rps); 202 203 spin_lock_irq(gt->irq_lock); 204 gen6_gt_pm_enable_irq(gt, rps->pm_events); 205 spin_unlock_irq(gt->irq_lock); 206 207 intel_uncore_write(gt->uncore, 208 GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq)); 209 } 210 211 static void gen6_rps_reset_interrupts(struct intel_rps *rps) 212 { 213 gen6_gt_pm_reset_iir(rps_to_gt(rps), GEN6_PM_RPS_EVENTS); 214 } 215 216 static void gen11_rps_reset_interrupts(struct intel_rps *rps) 217 { 218 while (gen11_gt_reset_one_iir(rps_to_gt(rps), 0, GEN11_GTPM)) 219 ; 220 } 221 222 static void rps_reset_interrupts(struct intel_rps *rps) 223 { 224 struct intel_gt *gt = rps_to_gt(rps); 225 226 spin_lock_irq(gt->irq_lock); 227 if (GRAPHICS_VER(gt->i915) >= 11) 228 gen11_rps_reset_interrupts(rps); 229 else 230 gen6_rps_reset_interrupts(rps); 231 232 rps->pm_iir = 0; 233 spin_unlock_irq(gt->irq_lock); 234 } 235 236 static void rps_disable_interrupts(struct intel_rps *rps) 237 { 238 struct intel_gt *gt = rps_to_gt(rps); 239 240 intel_uncore_write(gt->uncore, 241 GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u)); 242 243 spin_lock_irq(gt->irq_lock); 244 gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS); 245 spin_unlock_irq(gt->irq_lock); 246 247 intel_synchronize_irq(gt->i915); 248 249 /* 250 * Now that we will not be generating any more work, flush any 251 * outstanding tasks. As we are called on the RPS idle path, 252 * we will reset the GPU to minimum frequencies, so the current 253 * state of the worker can be discarded. 254 */ 255 cancel_work_sync(&rps->work); 256 257 rps_reset_interrupts(rps); 258 GT_TRACE(gt, "interrupts:off\n"); 259 } 260 261 static const struct cparams { 262 u16 i; 263 u16 t; 264 u16 m; 265 u16 c; 266 } cparams[] = { 267 { 1, 1333, 301, 28664 }, 268 { 1, 1067, 294, 24460 }, 269 { 1, 800, 294, 25192 }, 270 { 0, 1333, 276, 27605 }, 271 { 0, 1067, 276, 27605 }, 272 { 0, 800, 231, 23784 }, 273 }; 274 275 static void gen5_rps_init(struct intel_rps *rps) 276 { 277 struct drm_i915_private *i915 = rps_to_i915(rps); 278 struct intel_uncore *uncore = rps_to_uncore(rps); 279 u8 fmax, fmin, fstart; 280 u32 rgvmodectl; 281 int c_m, i; 282 283 if (i915->fsb_freq <= 3200000) 284 c_m = 0; 285 else if (i915->fsb_freq <= 4800000) 286 c_m = 1; 287 else 288 c_m = 2; 289 290 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 291 if (cparams[i].i == c_m && 292 cparams[i].t == DIV_ROUND_CLOSEST(i915->mem_freq, 1000)) { 293 rps->ips.m = cparams[i].m; 294 rps->ips.c = cparams[i].c; 295 break; 296 } 297 } 298 299 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 300 301 /* Set up min, max, and cur for interrupt handling */ 302 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 303 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 304 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 305 MEMMODE_FSTART_SHIFT; 306 drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n", 307 fmax, fmin, fstart); 308 309 rps->min_freq = fmax; 310 rps->efficient_freq = fstart; 311 rps->max_freq = fmin; 312 } 313 314 static unsigned long 315 __ips_chipset_val(struct intel_ips *ips) 316 { 317 struct intel_uncore *uncore = 318 rps_to_uncore(container_of(ips, struct intel_rps, ips)); 319 unsigned long now = jiffies_to_msecs(jiffies), dt; 320 unsigned long result; 321 u64 total, delta; 322 323 lockdep_assert_held(&mchdev_lock); 324 325 /* 326 * Prevent division-by-zero if we are asking too fast. 327 * Also, we don't get interesting results if we are polling 328 * faster than once in 10ms, so just return the saved value 329 * in such cases. 330 */ 331 dt = now - ips->last_time1; 332 if (dt <= 10) 333 return ips->chipset_power; 334 335 /* FIXME: handle per-counter overflow */ 336 total = intel_uncore_read(uncore, DMIEC); 337 total += intel_uncore_read(uncore, DDREC); 338 total += intel_uncore_read(uncore, CSIEC); 339 340 delta = total - ips->last_count1; 341 342 result = div_u64(div_u64(ips->m * delta, dt) + ips->c, 10); 343 344 ips->last_count1 = total; 345 ips->last_time1 = now; 346 347 ips->chipset_power = result; 348 349 return result; 350 } 351 352 static unsigned long ips_mch_val(struct intel_uncore *uncore) 353 { 354 unsigned int m, x, b; 355 u32 tsfs; 356 357 tsfs = intel_uncore_read(uncore, TSFS); 358 x = intel_uncore_read8(uncore, TR1); 359 360 b = tsfs & TSFS_INTR_MASK; 361 m = (tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT; 362 363 return m * x / 127 - b; 364 } 365 366 static int _pxvid_to_vd(u8 pxvid) 367 { 368 if (pxvid == 0) 369 return 0; 370 371 if (pxvid >= 8 && pxvid < 31) 372 pxvid = 31; 373 374 return (pxvid + 2) * 125; 375 } 376 377 static u32 pvid_to_extvid(struct drm_i915_private *i915, u8 pxvid) 378 { 379 const int vd = _pxvid_to_vd(pxvid); 380 381 if (INTEL_INFO(i915)->is_mobile) 382 return max(vd - 1125, 0); 383 384 return vd; 385 } 386 387 static void __gen5_ips_update(struct intel_ips *ips) 388 { 389 struct intel_uncore *uncore = 390 rps_to_uncore(container_of(ips, struct intel_rps, ips)); 391 u64 now, delta, dt; 392 u32 count; 393 394 lockdep_assert_held(&mchdev_lock); 395 396 now = ktime_get_raw_ns(); 397 dt = now - ips->last_time2; 398 do_div(dt, NSEC_PER_MSEC); 399 400 /* Don't divide by 0 */ 401 if (dt <= 10) 402 return; 403 404 count = intel_uncore_read(uncore, GFXEC); 405 delta = count - ips->last_count2; 406 407 ips->last_count2 = count; 408 ips->last_time2 = now; 409 410 /* More magic constants... */ 411 ips->gfx_power = div_u64(delta * 1181, dt * 10); 412 } 413 414 static void gen5_rps_update(struct intel_rps *rps) 415 { 416 spin_lock_irq(&mchdev_lock); 417 __gen5_ips_update(&rps->ips); 418 spin_unlock_irq(&mchdev_lock); 419 } 420 421 static unsigned int gen5_invert_freq(struct intel_rps *rps, 422 unsigned int val) 423 { 424 /* Invert the frequency bin into an ips delay */ 425 val = rps->max_freq - val; 426 val = rps->min_freq + val; 427 428 return val; 429 } 430 431 static int __gen5_rps_set(struct intel_rps *rps, u8 val) 432 { 433 struct intel_uncore *uncore = rps_to_uncore(rps); 434 u16 rgvswctl; 435 436 lockdep_assert_held(&mchdev_lock); 437 438 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 439 if (rgvswctl & MEMCTL_CMD_STS) { 440 drm_dbg(&rps_to_i915(rps)->drm, 441 "gpu busy, RCS change rejected\n"); 442 return -EBUSY; /* still busy with another command */ 443 } 444 445 /* Invert the frequency bin into an ips delay */ 446 val = gen5_invert_freq(rps, val); 447 448 rgvswctl = 449 (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 450 (val << MEMCTL_FREQ_SHIFT) | 451 MEMCTL_SFCAVM; 452 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); 453 intel_uncore_posting_read16(uncore, MEMSWCTL); 454 455 rgvswctl |= MEMCTL_CMD_STS; 456 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); 457 458 return 0; 459 } 460 461 static int gen5_rps_set(struct intel_rps *rps, u8 val) 462 { 463 int err; 464 465 spin_lock_irq(&mchdev_lock); 466 err = __gen5_rps_set(rps, val); 467 spin_unlock_irq(&mchdev_lock); 468 469 return err; 470 } 471 472 static unsigned long intel_pxfreq(u32 vidfreq) 473 { 474 int div = (vidfreq & 0x3f0000) >> 16; 475 int post = (vidfreq & 0x3000) >> 12; 476 int pre = (vidfreq & 0x7); 477 478 if (!pre) 479 return 0; 480 481 return div * 133333 / (pre << post); 482 } 483 484 static unsigned int init_emon(struct intel_uncore *uncore) 485 { 486 u8 pxw[16]; 487 int i; 488 489 /* Disable to program */ 490 intel_uncore_write(uncore, ECR, 0); 491 intel_uncore_posting_read(uncore, ECR); 492 493 /* Program energy weights for various events */ 494 intel_uncore_write(uncore, SDEW, 0x15040d00); 495 intel_uncore_write(uncore, CSIEW0, 0x007f0000); 496 intel_uncore_write(uncore, CSIEW1, 0x1e220004); 497 intel_uncore_write(uncore, CSIEW2, 0x04000004); 498 499 for (i = 0; i < 5; i++) 500 intel_uncore_write(uncore, PEW(i), 0); 501 for (i = 0; i < 3; i++) 502 intel_uncore_write(uncore, DEW(i), 0); 503 504 /* Program P-state weights to account for frequency power adjustment */ 505 for (i = 0; i < 16; i++) { 506 u32 pxvidfreq = intel_uncore_read(uncore, PXVFREQ(i)); 507 unsigned int freq = intel_pxfreq(pxvidfreq); 508 unsigned int vid = 509 (pxvidfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT; 510 unsigned int val; 511 512 val = vid * vid * freq / 1000 * 255; 513 val /= 127 * 127 * 900; 514 515 pxw[i] = val; 516 } 517 /* Render standby states get 0 weight */ 518 pxw[14] = 0; 519 pxw[15] = 0; 520 521 for (i = 0; i < 4; i++) { 522 intel_uncore_write(uncore, PXW(i), 523 pxw[i * 4 + 0] << 24 | 524 pxw[i * 4 + 1] << 16 | 525 pxw[i * 4 + 2] << 8 | 526 pxw[i * 4 + 3] << 0); 527 } 528 529 /* Adjust magic regs to magic values (more experimental results) */ 530 intel_uncore_write(uncore, OGW0, 0); 531 intel_uncore_write(uncore, OGW1, 0); 532 intel_uncore_write(uncore, EG0, 0x00007f00); 533 intel_uncore_write(uncore, EG1, 0x0000000e); 534 intel_uncore_write(uncore, EG2, 0x000e0000); 535 intel_uncore_write(uncore, EG3, 0x68000300); 536 intel_uncore_write(uncore, EG4, 0x42000000); 537 intel_uncore_write(uncore, EG5, 0x00140031); 538 intel_uncore_write(uncore, EG6, 0); 539 intel_uncore_write(uncore, EG7, 0); 540 541 for (i = 0; i < 8; i++) 542 intel_uncore_write(uncore, PXWL(i), 0); 543 544 /* Enable PMON + select events */ 545 intel_uncore_write(uncore, ECR, 0x80000019); 546 547 return intel_uncore_read(uncore, LCFUSE02) & LCFUSE_HIV_MASK; 548 } 549 550 static bool gen5_rps_enable(struct intel_rps *rps) 551 { 552 struct drm_i915_private *i915 = rps_to_i915(rps); 553 struct intel_display *display = &i915->display; 554 struct intel_uncore *uncore = rps_to_uncore(rps); 555 u8 fstart, vstart; 556 u32 rgvmodectl; 557 558 spin_lock_irq(&mchdev_lock); 559 560 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 561 562 /* Enable temp reporting */ 563 intel_uncore_write16(uncore, PMMISC, 564 intel_uncore_read16(uncore, PMMISC) | MCPPCE_EN); 565 intel_uncore_write16(uncore, TSC1, 566 intel_uncore_read16(uncore, TSC1) | TSE); 567 568 /* 100ms RC evaluation intervals */ 569 intel_uncore_write(uncore, RCUPEI, 100000); 570 intel_uncore_write(uncore, RCDNEI, 100000); 571 572 /* Set max/min thresholds to 90ms and 80ms respectively */ 573 intel_uncore_write(uncore, RCBMAXAVG, 90000); 574 intel_uncore_write(uncore, RCBMINAVG, 80000); 575 576 intel_uncore_write(uncore, MEMIHYST, 1); 577 578 /* Set up min, max, and cur for interrupt handling */ 579 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 580 MEMMODE_FSTART_SHIFT; 581 582 vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) & 583 PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT; 584 585 intel_uncore_write(uncore, 586 MEMINTREN, 587 MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 588 589 intel_uncore_write(uncore, VIDSTART, vstart); 590 intel_uncore_posting_read(uncore, VIDSTART); 591 592 rgvmodectl |= MEMMODE_SWMODE_EN; 593 intel_uncore_write(uncore, MEMMODECTL, rgvmodectl); 594 595 if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) & 596 MEMCTL_CMD_STS) == 0, 10)) 597 drm_err(&uncore->i915->drm, 598 "stuck trying to change perf mode\n"); 599 mdelay(1); 600 601 __gen5_rps_set(rps, rps->cur_freq); 602 603 rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC); 604 rps->ips.last_count1 += intel_uncore_read(uncore, DDREC); 605 rps->ips.last_count1 += intel_uncore_read(uncore, CSIEC); 606 rps->ips.last_time1 = jiffies_to_msecs(jiffies); 607 608 rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC); 609 rps->ips.last_time2 = ktime_get_raw_ns(); 610 611 spin_lock(&i915->irq_lock); 612 ilk_enable_display_irq(display, DE_PCU_EVENT); 613 spin_unlock(&i915->irq_lock); 614 615 spin_unlock_irq(&mchdev_lock); 616 617 rps->ips.corr = init_emon(uncore); 618 619 return true; 620 } 621 622 static void gen5_rps_disable(struct intel_rps *rps) 623 { 624 struct drm_i915_private *i915 = rps_to_i915(rps); 625 struct intel_display *display = &i915->display; 626 struct intel_uncore *uncore = rps_to_uncore(rps); 627 u16 rgvswctl; 628 629 spin_lock_irq(&mchdev_lock); 630 631 spin_lock(&i915->irq_lock); 632 ilk_disable_display_irq(display, DE_PCU_EVENT); 633 spin_unlock(&i915->irq_lock); 634 635 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 636 637 /* Ack interrupts, disable EFC interrupt */ 638 intel_uncore_rmw(uncore, MEMINTREN, MEMINT_EVAL_CHG_EN, 0); 639 intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG); 640 641 /* Go back to the starting frequency */ 642 __gen5_rps_set(rps, rps->idle_freq); 643 mdelay(1); 644 rgvswctl |= MEMCTL_CMD_STS; 645 intel_uncore_write(uncore, MEMSWCTL, rgvswctl); 646 mdelay(1); 647 648 spin_unlock_irq(&mchdev_lock); 649 } 650 651 static u32 rps_limits(struct intel_rps *rps, u8 val) 652 { 653 u32 limits; 654 655 /* 656 * Only set the down limit when we've reached the lowest level to avoid 657 * getting more interrupts, otherwise leave this clear. This prevents a 658 * race in the hw when coming out of rc6: There's a tiny window where 659 * the hw runs at the minimal clock before selecting the desired 660 * frequency, if the down threshold expires in that window we will not 661 * receive a down interrupt. 662 */ 663 if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) { 664 limits = rps->max_freq_softlimit << 23; 665 if (val <= rps->min_freq_softlimit) 666 limits |= rps->min_freq_softlimit << 14; 667 } else { 668 limits = rps->max_freq_softlimit << 24; 669 if (val <= rps->min_freq_softlimit) 670 limits |= rps->min_freq_softlimit << 16; 671 } 672 673 return limits; 674 } 675 676 static void rps_set_power(struct intel_rps *rps, int new_power) 677 { 678 struct intel_gt *gt = rps_to_gt(rps); 679 struct intel_uncore *uncore = gt->uncore; 680 u32 ei_up = 0, ei_down = 0; 681 682 lockdep_assert_held(&rps->power.mutex); 683 684 if (new_power == rps->power.mode) 685 return; 686 687 /* Note the units here are not exactly 1us, but 1280ns. */ 688 switch (new_power) { 689 case LOW_POWER: 690 ei_up = 16000; 691 ei_down = 32000; 692 break; 693 694 case BETWEEN: 695 ei_up = 13000; 696 ei_down = 32000; 697 break; 698 699 case HIGH_POWER: 700 ei_up = 10000; 701 ei_down = 32000; 702 break; 703 } 704 705 /* When byt can survive without system hang with dynamic 706 * sw freq adjustments, this restriction can be lifted. 707 */ 708 if (IS_VALLEYVIEW(gt->i915)) 709 goto skip_hw_write; 710 711 GT_TRACE(gt, 712 "changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n", 713 new_power, 714 rps->power.up_threshold, ei_up, 715 rps->power.down_threshold, ei_down); 716 717 set(uncore, GEN6_RP_UP_EI, 718 intel_gt_ns_to_pm_interval(gt, ei_up * 1000)); 719 set(uncore, GEN6_RP_UP_THRESHOLD, 720 intel_gt_ns_to_pm_interval(gt, 721 ei_up * rps->power.up_threshold * 10)); 722 723 set(uncore, GEN6_RP_DOWN_EI, 724 intel_gt_ns_to_pm_interval(gt, ei_down * 1000)); 725 set(uncore, GEN6_RP_DOWN_THRESHOLD, 726 intel_gt_ns_to_pm_interval(gt, 727 ei_down * 728 rps->power.down_threshold * 10)); 729 730 set(uncore, GEN6_RP_CONTROL, 731 (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) | 732 GEN6_RP_MEDIA_HW_NORMAL_MODE | 733 GEN6_RP_MEDIA_IS_GFX | 734 GEN6_RP_ENABLE | 735 GEN6_RP_UP_BUSY_AVG | 736 GEN6_RP_DOWN_IDLE_AVG); 737 738 skip_hw_write: 739 rps->power.mode = new_power; 740 } 741 742 static void gen6_rps_set_thresholds(struct intel_rps *rps, u8 val) 743 { 744 int new_power; 745 746 new_power = rps->power.mode; 747 switch (rps->power.mode) { 748 case LOW_POWER: 749 if (val > rps->efficient_freq + 1 && 750 val > rps->cur_freq) 751 new_power = BETWEEN; 752 break; 753 754 case BETWEEN: 755 if (val <= rps->efficient_freq && 756 val < rps->cur_freq) 757 new_power = LOW_POWER; 758 else if (val >= rps->rp0_freq && 759 val > rps->cur_freq) 760 new_power = HIGH_POWER; 761 break; 762 763 case HIGH_POWER: 764 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && 765 val < rps->cur_freq) 766 new_power = BETWEEN; 767 break; 768 } 769 /* Max/min bins are special */ 770 if (val <= rps->min_freq_softlimit) 771 new_power = LOW_POWER; 772 if (val >= rps->max_freq_softlimit) 773 new_power = HIGH_POWER; 774 775 mutex_lock(&rps->power.mutex); 776 if (rps->power.interactive) 777 new_power = HIGH_POWER; 778 rps_set_power(rps, new_power); 779 mutex_unlock(&rps->power.mutex); 780 } 781 782 void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive) 783 { 784 GT_TRACE(rps_to_gt(rps), "mark interactive: %s\n", 785 str_yes_no(interactive)); 786 787 mutex_lock(&rps->power.mutex); 788 if (interactive) { 789 if (!rps->power.interactive++ && intel_rps_is_active(rps)) 790 rps_set_power(rps, HIGH_POWER); 791 } else { 792 GEM_BUG_ON(!rps->power.interactive); 793 rps->power.interactive--; 794 } 795 mutex_unlock(&rps->power.mutex); 796 } 797 798 static int gen6_rps_set(struct intel_rps *rps, u8 val) 799 { 800 struct intel_uncore *uncore = rps_to_uncore(rps); 801 struct drm_i915_private *i915 = rps_to_i915(rps); 802 u32 swreq; 803 804 GEM_BUG_ON(rps_uses_slpc(rps)); 805 806 if (GRAPHICS_VER(i915) >= 9) 807 swreq = GEN9_FREQUENCY(val); 808 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 809 swreq = HSW_FREQUENCY(val); 810 else 811 swreq = (GEN6_FREQUENCY(val) | 812 GEN6_OFFSET(0) | 813 GEN6_AGGRESSIVE_TURBO); 814 set(uncore, GEN6_RPNSWREQ, swreq); 815 816 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n", 817 val, intel_gpu_freq(rps, val), swreq); 818 819 return 0; 820 } 821 822 static int vlv_rps_set(struct intel_rps *rps, u8 val) 823 { 824 struct drm_i915_private *i915 = rps_to_i915(rps); 825 int err; 826 827 vlv_punit_get(i915); 828 err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val); 829 vlv_punit_put(i915); 830 831 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n", 832 val, intel_gpu_freq(rps, val)); 833 834 return err; 835 } 836 837 static int rps_set(struct intel_rps *rps, u8 val, bool update) 838 { 839 struct drm_i915_private *i915 = rps_to_i915(rps); 840 int err; 841 842 if (val == rps->last_freq) 843 return 0; 844 845 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 846 err = vlv_rps_set(rps, val); 847 else if (GRAPHICS_VER(i915) >= 6) 848 err = gen6_rps_set(rps, val); 849 else 850 err = gen5_rps_set(rps, val); 851 if (err) 852 return err; 853 854 if (update && GRAPHICS_VER(i915) >= 6) 855 gen6_rps_set_thresholds(rps, val); 856 rps->last_freq = val; 857 858 return 0; 859 } 860 861 void intel_rps_unpark(struct intel_rps *rps) 862 { 863 if (!intel_rps_is_enabled(rps)) 864 return; 865 866 GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq); 867 868 /* 869 * Use the user's desired frequency as a guide, but for better 870 * performance, jump directly to RPe as our starting frequency. 871 */ 872 mutex_lock(&rps->lock); 873 874 intel_rps_set_active(rps); 875 intel_rps_set(rps, 876 clamp(rps->cur_freq, 877 rps->min_freq_softlimit, 878 rps->max_freq_softlimit)); 879 880 mutex_unlock(&rps->lock); 881 882 rps->pm_iir = 0; 883 if (intel_rps_has_interrupts(rps)) 884 rps_enable_interrupts(rps); 885 if (intel_rps_uses_timer(rps)) 886 rps_start_timer(rps); 887 888 if (GRAPHICS_VER(rps_to_i915(rps)) == 5) 889 gen5_rps_update(rps); 890 } 891 892 void intel_rps_park(struct intel_rps *rps) 893 { 894 int adj; 895 896 if (!intel_rps_is_enabled(rps)) 897 return; 898 899 if (!intel_rps_clear_active(rps)) 900 return; 901 902 if (intel_rps_uses_timer(rps)) 903 rps_stop_timer(rps); 904 if (intel_rps_has_interrupts(rps)) 905 rps_disable_interrupts(rps); 906 907 if (rps->last_freq <= rps->idle_freq) 908 return; 909 910 /* 911 * The punit delays the write of the frequency and voltage until it 912 * determines the GPU is awake. During normal usage we don't want to 913 * waste power changing the frequency if the GPU is sleeping (rc6). 914 * However, the GPU and driver is now idle and we do not want to delay 915 * switching to minimum voltage (reducing power whilst idle) as we do 916 * not expect to be woken in the near future and so must flush the 917 * change by waking the device. 918 * 919 * We choose to take the media powerwell (either would do to trick the 920 * punit into committing the voltage change) as that takes a lot less 921 * power than the render powerwell. 922 */ 923 intel_uncore_forcewake_get(rps_to_uncore(rps), FORCEWAKE_MEDIA); 924 rps_set(rps, rps->idle_freq, false); 925 intel_uncore_forcewake_put(rps_to_uncore(rps), FORCEWAKE_MEDIA); 926 927 /* 928 * Since we will try and restart from the previously requested 929 * frequency on unparking, treat this idle point as a downclock 930 * interrupt and reduce the frequency for resume. If we park/unpark 931 * more frequently than the rps worker can run, we will not respond 932 * to any EI and never see a change in frequency. 933 * 934 * (Note we accommodate Cherryview's limitation of only using an 935 * even bin by applying it to all.) 936 */ 937 adj = rps->last_adj; 938 if (adj < 0) 939 adj *= 2; 940 else /* CHV needs even encode values */ 941 adj = -2; 942 rps->last_adj = adj; 943 rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq); 944 if (rps->cur_freq < rps->efficient_freq) { 945 rps->cur_freq = rps->efficient_freq; 946 rps->last_adj = 0; 947 } 948 949 GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq); 950 } 951 952 u32 intel_rps_get_boost_frequency(struct intel_rps *rps) 953 { 954 struct intel_guc_slpc *slpc; 955 956 if (rps_uses_slpc(rps)) { 957 slpc = rps_to_slpc(rps); 958 959 return slpc->boost_freq; 960 } else { 961 return intel_gpu_freq(rps, rps->boost_freq); 962 } 963 } 964 965 static int rps_set_boost_freq(struct intel_rps *rps, u32 val) 966 { 967 bool boost = false; 968 969 /* Validate against (static) hardware limits */ 970 val = intel_freq_opcode(rps, val); 971 if (val < rps->min_freq || val > rps->max_freq) 972 return -EINVAL; 973 974 mutex_lock(&rps->lock); 975 if (val != rps->boost_freq) { 976 rps->boost_freq = val; 977 boost = atomic_read(&rps->num_waiters); 978 } 979 mutex_unlock(&rps->lock); 980 if (boost) 981 queue_work(rps_to_gt(rps)->i915->unordered_wq, &rps->work); 982 983 return 0; 984 } 985 986 int intel_rps_set_boost_frequency(struct intel_rps *rps, u32 freq) 987 { 988 struct intel_guc_slpc *slpc; 989 990 if (rps_uses_slpc(rps)) { 991 slpc = rps_to_slpc(rps); 992 993 return intel_guc_slpc_set_boost_freq(slpc, freq); 994 } else { 995 return rps_set_boost_freq(rps, freq); 996 } 997 } 998 999 void intel_rps_dec_waiters(struct intel_rps *rps) 1000 { 1001 struct intel_guc_slpc *slpc; 1002 1003 if (rps_uses_slpc(rps)) { 1004 slpc = rps_to_slpc(rps); 1005 1006 intel_guc_slpc_dec_waiters(slpc); 1007 } else { 1008 atomic_dec(&rps->num_waiters); 1009 } 1010 } 1011 1012 void intel_rps_boost(struct i915_request *rq) 1013 { 1014 struct intel_guc_slpc *slpc; 1015 1016 if (i915_request_signaled(rq) || i915_request_has_waitboost(rq)) 1017 return; 1018 1019 /* Waitboost is not needed for contexts marked with a Freq hint */ 1020 if (test_bit(CONTEXT_LOW_LATENCY, &rq->context->flags)) 1021 return; 1022 1023 /* Serializes with i915_request_retire() */ 1024 if (!test_and_set_bit(I915_FENCE_FLAG_BOOST, &rq->fence.flags)) { 1025 struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps; 1026 1027 if (rps_uses_slpc(rps)) { 1028 slpc = rps_to_slpc(rps); 1029 1030 /* Waitboost should not be done with power saving profile */ 1031 if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING) 1032 return; 1033 1034 if (slpc->min_freq_softlimit >= slpc->boost_freq) 1035 return; 1036 1037 /* Return if old value is non zero */ 1038 if (!atomic_fetch_inc(&slpc->num_waiters)) { 1039 GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n", 1040 rq->fence.context, rq->fence.seqno); 1041 queue_work(rps_to_gt(rps)->i915->unordered_wq, 1042 &slpc->boost_work); 1043 } 1044 1045 return; 1046 } 1047 1048 if (atomic_fetch_inc(&rps->num_waiters)) 1049 return; 1050 1051 if (!intel_rps_is_active(rps)) 1052 return; 1053 1054 GT_TRACE(rps_to_gt(rps), "boost fence:%llx:%llx\n", 1055 rq->fence.context, rq->fence.seqno); 1056 1057 if (READ_ONCE(rps->cur_freq) < rps->boost_freq) 1058 queue_work(rps_to_gt(rps)->i915->unordered_wq, &rps->work); 1059 1060 WRITE_ONCE(rps->boosts, rps->boosts + 1); /* debug only */ 1061 } 1062 } 1063 1064 int intel_rps_set(struct intel_rps *rps, u8 val) 1065 { 1066 int err; 1067 1068 lockdep_assert_held(&rps->lock); 1069 GEM_BUG_ON(val > rps->max_freq); 1070 GEM_BUG_ON(val < rps->min_freq); 1071 1072 if (intel_rps_is_active(rps)) { 1073 err = rps_set(rps, val, true); 1074 if (err) 1075 return err; 1076 1077 /* 1078 * Make sure we continue to get interrupts 1079 * until we hit the minimum or maximum frequencies. 1080 */ 1081 if (intel_rps_has_interrupts(rps)) { 1082 struct intel_uncore *uncore = rps_to_uncore(rps); 1083 1084 set(uncore, 1085 GEN6_RP_INTERRUPT_LIMITS, rps_limits(rps, val)); 1086 1087 set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val)); 1088 } 1089 } 1090 1091 rps->cur_freq = val; 1092 return 0; 1093 } 1094 1095 static u32 intel_rps_read_state_cap(struct intel_rps *rps) 1096 { 1097 struct drm_i915_private *i915 = rps_to_i915(rps); 1098 struct intel_uncore *uncore = rps_to_uncore(rps); 1099 1100 if (IS_GEN9_LP(i915)) 1101 return intel_uncore_read(uncore, BXT_RP_STATE_CAP); 1102 else 1103 return intel_uncore_read(uncore, GEN6_RP_STATE_CAP); 1104 } 1105 1106 static void 1107 mtl_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) 1108 { 1109 struct intel_uncore *uncore = rps_to_uncore(rps); 1110 u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ? 1111 intel_uncore_read(uncore, MTL_MEDIAP_STATE_CAP) : 1112 intel_uncore_read(uncore, MTL_RP_STATE_CAP); 1113 u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ? 1114 intel_uncore_read(uncore, MTL_MPE_FREQUENCY) : 1115 intel_uncore_read(uncore, MTL_GT_RPE_FREQUENCY); 1116 1117 /* MTL values are in units of 16.67 MHz */ 1118 caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap); 1119 caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap); 1120 caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe); 1121 } 1122 1123 static void 1124 __gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) 1125 { 1126 struct drm_i915_private *i915 = rps_to_i915(rps); 1127 u32 rp_state_cap; 1128 1129 rp_state_cap = intel_rps_read_state_cap(rps); 1130 1131 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 1132 if (IS_GEN9_LP(i915)) { 1133 caps->rp0_freq = (rp_state_cap >> 16) & 0xff; 1134 caps->rp1_freq = (rp_state_cap >> 8) & 0xff; 1135 caps->min_freq = (rp_state_cap >> 0) & 0xff; 1136 } else { 1137 caps->rp0_freq = (rp_state_cap >> 0) & 0xff; 1138 if (GRAPHICS_VER(i915) >= 10) 1139 caps->rp1_freq = REG_FIELD_GET(RPE_MASK, 1140 intel_uncore_read(to_gt(i915)->uncore, 1141 GEN10_FREQ_INFO_REC)); 1142 else 1143 caps->rp1_freq = (rp_state_cap >> 8) & 0xff; 1144 caps->min_freq = (rp_state_cap >> 16) & 0xff; 1145 } 1146 1147 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 1148 /* 1149 * In this case rp_state_cap register reports frequencies in 1150 * units of 50 MHz. Convert these to the actual "hw unit", i.e. 1151 * units of 16.67 MHz 1152 */ 1153 caps->rp0_freq *= GEN9_FREQ_SCALER; 1154 caps->rp1_freq *= GEN9_FREQ_SCALER; 1155 caps->min_freq *= GEN9_FREQ_SCALER; 1156 } 1157 } 1158 1159 /** 1160 * gen6_rps_get_freq_caps - Get freq caps exposed by HW 1161 * @rps: the intel_rps structure 1162 * @caps: returned freq caps 1163 * 1164 * Returned "caps" frequencies should be converted to MHz using 1165 * intel_gpu_freq() 1166 */ 1167 void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) 1168 { 1169 struct drm_i915_private *i915 = rps_to_i915(rps); 1170 1171 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1172 return mtl_get_freq_caps(rps, caps); 1173 else 1174 return __gen6_rps_get_freq_caps(rps, caps); 1175 } 1176 1177 static void gen6_rps_init(struct intel_rps *rps) 1178 { 1179 struct drm_i915_private *i915 = rps_to_i915(rps); 1180 struct intel_rps_freq_caps caps; 1181 1182 gen6_rps_get_freq_caps(rps, &caps); 1183 rps->rp0_freq = caps.rp0_freq; 1184 rps->rp1_freq = caps.rp1_freq; 1185 rps->min_freq = caps.min_freq; 1186 1187 /* hw_max = RP0 until we check for overclocking */ 1188 rps->max_freq = rps->rp0_freq; 1189 1190 rps->efficient_freq = rps->rp1_freq; 1191 if (IS_HASWELL(i915) || IS_BROADWELL(i915) || 1192 IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 1193 u32 ddcc_status = 0; 1194 u32 mult = 1; 1195 1196 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) 1197 mult = GEN9_FREQ_SCALER; 1198 if (snb_pcode_read(rps_to_gt(rps)->uncore, 1199 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 1200 &ddcc_status, NULL) == 0) 1201 rps->efficient_freq = 1202 clamp_t(u32, 1203 ((ddcc_status >> 8) & 0xff) * mult, 1204 rps->min_freq, 1205 rps->max_freq); 1206 } 1207 } 1208 1209 static bool rps_reset(struct intel_rps *rps) 1210 { 1211 struct drm_i915_private *i915 = rps_to_i915(rps); 1212 1213 /* force a reset */ 1214 rps->power.mode = -1; 1215 rps->last_freq = -1; 1216 1217 if (rps_set(rps, rps->min_freq, true)) { 1218 drm_err(&i915->drm, "Failed to reset RPS to initial values\n"); 1219 return false; 1220 } 1221 1222 rps->cur_freq = rps->min_freq; 1223 return true; 1224 } 1225 1226 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 1227 static bool gen9_rps_enable(struct intel_rps *rps) 1228 { 1229 struct intel_gt *gt = rps_to_gt(rps); 1230 struct intel_uncore *uncore = gt->uncore; 1231 1232 /* Program defaults and thresholds for RPS */ 1233 if (GRAPHICS_VER(gt->i915) == 9) 1234 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ, 1235 GEN9_FREQUENCY(rps->rp1_freq)); 1236 1237 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 0xa); 1238 1239 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; 1240 1241 return rps_reset(rps); 1242 } 1243 1244 static bool gen8_rps_enable(struct intel_rps *rps) 1245 { 1246 struct intel_uncore *uncore = rps_to_uncore(rps); 1247 1248 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ, 1249 HSW_FREQUENCY(rps->rp1_freq)); 1250 1251 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1252 1253 rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; 1254 1255 return rps_reset(rps); 1256 } 1257 1258 static bool gen6_rps_enable(struct intel_rps *rps) 1259 { 1260 struct intel_uncore *uncore = rps_to_uncore(rps); 1261 1262 /* Power down if completely idle for over 50ms */ 1263 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000); 1264 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1265 1266 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | 1267 GEN6_PM_RP_DOWN_THRESHOLD | 1268 GEN6_PM_RP_DOWN_TIMEOUT); 1269 1270 return rps_reset(rps); 1271 } 1272 1273 static int chv_rps_max_freq(struct intel_rps *rps) 1274 { 1275 struct drm_i915_private *i915 = rps_to_i915(rps); 1276 struct intel_gt *gt = rps_to_gt(rps); 1277 u32 val; 1278 1279 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); 1280 1281 switch (gt->info.sseu.eu_total) { 1282 case 8: 1283 /* (2 * 4) config */ 1284 val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT; 1285 break; 1286 case 12: 1287 /* (2 * 6) config */ 1288 val >>= FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT; 1289 break; 1290 case 16: 1291 /* (2 * 8) config */ 1292 default: 1293 /* Setting (2 * 8) Min RP0 for any other combination */ 1294 val >>= FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT; 1295 break; 1296 } 1297 1298 return val & FB_GFX_FREQ_FUSE_MASK; 1299 } 1300 1301 static int chv_rps_rpe_freq(struct intel_rps *rps) 1302 { 1303 struct drm_i915_private *i915 = rps_to_i915(rps); 1304 u32 val; 1305 1306 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); 1307 val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT; 1308 1309 return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 1310 } 1311 1312 static int chv_rps_guar_freq(struct intel_rps *rps) 1313 { 1314 struct drm_i915_private *i915 = rps_to_i915(rps); 1315 u32 val; 1316 1317 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); 1318 1319 return val & FB_GFX_FREQ_FUSE_MASK; 1320 } 1321 1322 static u32 chv_rps_min_freq(struct intel_rps *rps) 1323 { 1324 struct drm_i915_private *i915 = rps_to_i915(rps); 1325 u32 val; 1326 1327 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); 1328 val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT; 1329 1330 return val & FB_GFX_FREQ_FUSE_MASK; 1331 } 1332 1333 static bool chv_rps_enable(struct intel_rps *rps) 1334 { 1335 struct intel_uncore *uncore = rps_to_uncore(rps); 1336 struct drm_i915_private *i915 = rps_to_i915(rps); 1337 u32 val; 1338 1339 /* 1: Program defaults and thresholds for RPS*/ 1340 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000); 1341 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400); 1342 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000); 1343 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000); 1344 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000); 1345 1346 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1347 1348 /* 2: Enable RPS */ 1349 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL, 1350 GEN6_RP_MEDIA_HW_NORMAL_MODE | 1351 GEN6_RP_MEDIA_IS_GFX | 1352 GEN6_RP_ENABLE | 1353 GEN6_RP_UP_BUSY_AVG | 1354 GEN6_RP_DOWN_IDLE_AVG); 1355 1356 rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | 1357 GEN6_PM_RP_DOWN_THRESHOLD | 1358 GEN6_PM_RP_DOWN_TIMEOUT); 1359 1360 /* Setting Fixed Bias */ 1361 vlv_punit_get(i915); 1362 1363 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50; 1364 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); 1365 1366 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1367 1368 vlv_punit_put(i915); 1369 1370 /* RPS code assumes GPLL is used */ 1371 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, 1372 "GPLL not enabled\n"); 1373 1374 drm_dbg(&i915->drm, "GPLL enabled? %s\n", 1375 str_yes_no(val & GPLLENABLE)); 1376 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); 1377 1378 return rps_reset(rps); 1379 } 1380 1381 static int vlv_rps_guar_freq(struct intel_rps *rps) 1382 { 1383 struct drm_i915_private *i915 = rps_to_i915(rps); 1384 u32 val, rp1; 1385 1386 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); 1387 1388 rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK; 1389 rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 1390 1391 return rp1; 1392 } 1393 1394 static int vlv_rps_max_freq(struct intel_rps *rps) 1395 { 1396 struct drm_i915_private *i915 = rps_to_i915(rps); 1397 u32 val, rp0; 1398 1399 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); 1400 1401 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 1402 /* Clamp to max */ 1403 rp0 = min_t(u32, rp0, 0xea); 1404 1405 return rp0; 1406 } 1407 1408 static int vlv_rps_rpe_freq(struct intel_rps *rps) 1409 { 1410 struct drm_i915_private *i915 = rps_to_i915(rps); 1411 u32 val, rpe; 1412 1413 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 1414 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 1415 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 1416 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 1417 1418 return rpe; 1419 } 1420 1421 static int vlv_rps_min_freq(struct intel_rps *rps) 1422 { 1423 struct drm_i915_private *i915 = rps_to_i915(rps); 1424 u32 val; 1425 1426 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; 1427 /* 1428 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value 1429 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on 1430 * a BYT-M B0 the above register contains 0xbf. Moreover when setting 1431 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 1432 * to make sure it matches what Punit accepts. 1433 */ 1434 return max_t(u32, val, 0xc0); 1435 } 1436 1437 static bool vlv_rps_enable(struct intel_rps *rps) 1438 { 1439 struct intel_uncore *uncore = rps_to_uncore(rps); 1440 struct drm_i915_private *i915 = rps_to_i915(rps); 1441 u32 val; 1442 1443 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000); 1444 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400); 1445 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000); 1446 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000); 1447 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000); 1448 1449 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); 1450 1451 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL, 1452 GEN6_RP_MEDIA_TURBO | 1453 GEN6_RP_MEDIA_HW_NORMAL_MODE | 1454 GEN6_RP_MEDIA_IS_GFX | 1455 GEN6_RP_ENABLE | 1456 GEN6_RP_UP_BUSY_AVG | 1457 GEN6_RP_DOWN_IDLE_CONT); 1458 1459 /* WaGsvRC0ResidencyMethod:vlv */ 1460 rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED; 1461 1462 vlv_punit_get(i915); 1463 1464 /* Setting Fixed Bias */ 1465 val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875; 1466 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); 1467 1468 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 1469 1470 vlv_punit_put(i915); 1471 1472 /* RPS code assumes GPLL is used */ 1473 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, 1474 "GPLL not enabled\n"); 1475 1476 drm_dbg(&i915->drm, "GPLL enabled? %s\n", 1477 str_yes_no(val & GPLLENABLE)); 1478 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); 1479 1480 return rps_reset(rps); 1481 } 1482 1483 static unsigned long __ips_gfx_val(struct intel_ips *ips) 1484 { 1485 struct intel_rps *rps = container_of(ips, typeof(*rps), ips); 1486 struct intel_uncore *uncore = rps_to_uncore(rps); 1487 unsigned int t, state1, state2; 1488 u32 pxvid, ext_v; 1489 u64 corr, corr2; 1490 1491 lockdep_assert_held(&mchdev_lock); 1492 1493 pxvid = intel_uncore_read(uncore, PXVFREQ(rps->cur_freq)); 1494 pxvid = (pxvid >> 24) & 0x7f; 1495 ext_v = pvid_to_extvid(rps_to_i915(rps), pxvid); 1496 1497 state1 = ext_v; 1498 1499 /* Revel in the empirically derived constants */ 1500 1501 /* Correction factor in 1/100000 units */ 1502 t = ips_mch_val(uncore); 1503 if (t > 80) 1504 corr = t * 2349 + 135940; 1505 else if (t >= 50) 1506 corr = t * 964 + 29317; 1507 else /* < 50 */ 1508 corr = t * 301 + 1004; 1509 1510 corr = div_u64(corr * 150142 * state1, 10000) - 78642; 1511 corr2 = div_u64(corr, 100000) * ips->corr; 1512 1513 state2 = div_u64(corr2 * state1, 10000); 1514 state2 /= 100; /* convert to mW */ 1515 1516 __gen5_ips_update(ips); 1517 1518 return ips->gfx_power + state2; 1519 } 1520 1521 static bool has_busy_stats(struct intel_rps *rps) 1522 { 1523 struct intel_engine_cs *engine; 1524 enum intel_engine_id id; 1525 1526 for_each_engine(engine, rps_to_gt(rps), id) { 1527 if (!intel_engine_supports_stats(engine)) 1528 return false; 1529 } 1530 1531 return true; 1532 } 1533 1534 void intel_rps_enable(struct intel_rps *rps) 1535 { 1536 struct drm_i915_private *i915 = rps_to_i915(rps); 1537 struct intel_uncore *uncore = rps_to_uncore(rps); 1538 bool enabled = false; 1539 1540 if (!HAS_RPS(i915)) 1541 return; 1542 1543 if (rps_uses_slpc(rps)) 1544 return; 1545 1546 intel_gt_check_clock_frequency(rps_to_gt(rps)); 1547 1548 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 1549 if (rps->max_freq <= rps->min_freq) 1550 /* leave disabled, no room for dynamic reclocking */; 1551 else if (IS_CHERRYVIEW(i915)) 1552 enabled = chv_rps_enable(rps); 1553 else if (IS_VALLEYVIEW(i915)) 1554 enabled = vlv_rps_enable(rps); 1555 else if (GRAPHICS_VER(i915) >= 9) 1556 enabled = gen9_rps_enable(rps); 1557 else if (GRAPHICS_VER(i915) >= 8) 1558 enabled = gen8_rps_enable(rps); 1559 else if (GRAPHICS_VER(i915) >= 6) 1560 enabled = gen6_rps_enable(rps); 1561 else if (IS_IRONLAKE_M(i915)) 1562 enabled = gen5_rps_enable(rps); 1563 else 1564 MISSING_CASE(GRAPHICS_VER(i915)); 1565 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 1566 if (!enabled) 1567 return; 1568 1569 GT_TRACE(rps_to_gt(rps), 1570 "min:%x, max:%x, freq:[%d, %d], thresholds:[%u, %u]\n", 1571 rps->min_freq, rps->max_freq, 1572 intel_gpu_freq(rps, rps->min_freq), 1573 intel_gpu_freq(rps, rps->max_freq), 1574 rps->power.up_threshold, 1575 rps->power.down_threshold); 1576 1577 GEM_BUG_ON(rps->max_freq < rps->min_freq); 1578 GEM_BUG_ON(rps->idle_freq > rps->max_freq); 1579 1580 GEM_BUG_ON(rps->efficient_freq < rps->min_freq); 1581 GEM_BUG_ON(rps->efficient_freq > rps->max_freq); 1582 1583 if (has_busy_stats(rps)) 1584 intel_rps_set_timer(rps); 1585 else if (GRAPHICS_VER(i915) >= 6 && GRAPHICS_VER(i915) <= 11) 1586 intel_rps_set_interrupts(rps); 1587 else 1588 /* Ironlake currently uses intel_ips.ko */ {} 1589 1590 intel_rps_set_enabled(rps); 1591 } 1592 1593 static void gen6_rps_disable(struct intel_rps *rps) 1594 { 1595 set(rps_to_uncore(rps), GEN6_RP_CONTROL, 0); 1596 } 1597 1598 void intel_rps_disable(struct intel_rps *rps) 1599 { 1600 struct drm_i915_private *i915 = rps_to_i915(rps); 1601 1602 if (!intel_rps_is_enabled(rps)) 1603 return; 1604 1605 intel_rps_clear_enabled(rps); 1606 intel_rps_clear_interrupts(rps); 1607 intel_rps_clear_timer(rps); 1608 1609 if (GRAPHICS_VER(i915) >= 6) 1610 gen6_rps_disable(rps); 1611 else if (IS_IRONLAKE_M(i915)) 1612 gen5_rps_disable(rps); 1613 } 1614 1615 static int byt_gpu_freq(struct intel_rps *rps, int val) 1616 { 1617 /* 1618 * N = val - 0xb7 1619 * Slow = Fast = GPLL ref * N 1620 */ 1621 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); 1622 } 1623 1624 static int byt_freq_opcode(struct intel_rps *rps, int val) 1625 { 1626 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; 1627 } 1628 1629 static int chv_gpu_freq(struct intel_rps *rps, int val) 1630 { 1631 /* 1632 * N = val / 2 1633 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 1634 */ 1635 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); 1636 } 1637 1638 static int chv_freq_opcode(struct intel_rps *rps, int val) 1639 { 1640 /* CHV needs even values */ 1641 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; 1642 } 1643 1644 int intel_gpu_freq(struct intel_rps *rps, int val) 1645 { 1646 struct drm_i915_private *i915 = rps_to_i915(rps); 1647 1648 if (GRAPHICS_VER(i915) >= 9) 1649 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 1650 GEN9_FREQ_SCALER); 1651 else if (IS_CHERRYVIEW(i915)) 1652 return chv_gpu_freq(rps, val); 1653 else if (IS_VALLEYVIEW(i915)) 1654 return byt_gpu_freq(rps, val); 1655 else if (GRAPHICS_VER(i915) >= 6) 1656 return val * GT_FREQUENCY_MULTIPLIER; 1657 else 1658 return val; 1659 } 1660 1661 int intel_freq_opcode(struct intel_rps *rps, int val) 1662 { 1663 struct drm_i915_private *i915 = rps_to_i915(rps); 1664 1665 if (GRAPHICS_VER(i915) >= 9) 1666 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 1667 GT_FREQUENCY_MULTIPLIER); 1668 else if (IS_CHERRYVIEW(i915)) 1669 return chv_freq_opcode(rps, val); 1670 else if (IS_VALLEYVIEW(i915)) 1671 return byt_freq_opcode(rps, val); 1672 else if (GRAPHICS_VER(i915) >= 6) 1673 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 1674 else 1675 return val; 1676 } 1677 1678 static void vlv_init_gpll_ref_freq(struct intel_rps *rps) 1679 { 1680 struct drm_i915_private *i915 = rps_to_i915(rps); 1681 1682 rps->gpll_ref_freq = 1683 vlv_get_cck_clock(i915, "GPLL ref", 1684 CCK_GPLL_CLOCK_CONTROL, 1685 i915->czclk_freq); 1686 1687 drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n", 1688 rps->gpll_ref_freq); 1689 } 1690 1691 static void vlv_rps_init(struct intel_rps *rps) 1692 { 1693 struct drm_i915_private *i915 = rps_to_i915(rps); 1694 1695 vlv_iosf_sb_get(i915, 1696 BIT(VLV_IOSF_SB_PUNIT) | 1697 BIT(VLV_IOSF_SB_NC) | 1698 BIT(VLV_IOSF_SB_CCK)); 1699 1700 vlv_init_gpll_ref_freq(rps); 1701 1702 rps->max_freq = vlv_rps_max_freq(rps); 1703 rps->rp0_freq = rps->max_freq; 1704 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", 1705 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); 1706 1707 rps->efficient_freq = vlv_rps_rpe_freq(rps); 1708 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", 1709 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); 1710 1711 rps->rp1_freq = vlv_rps_guar_freq(rps); 1712 drm_dbg(&i915->drm, "RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 1713 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); 1714 1715 rps->min_freq = vlv_rps_min_freq(rps); 1716 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", 1717 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); 1718 1719 vlv_iosf_sb_put(i915, 1720 BIT(VLV_IOSF_SB_PUNIT) | 1721 BIT(VLV_IOSF_SB_NC) | 1722 BIT(VLV_IOSF_SB_CCK)); 1723 } 1724 1725 static void chv_rps_init(struct intel_rps *rps) 1726 { 1727 struct drm_i915_private *i915 = rps_to_i915(rps); 1728 1729 vlv_iosf_sb_get(i915, 1730 BIT(VLV_IOSF_SB_PUNIT) | 1731 BIT(VLV_IOSF_SB_NC) | 1732 BIT(VLV_IOSF_SB_CCK)); 1733 1734 vlv_init_gpll_ref_freq(rps); 1735 1736 rps->max_freq = chv_rps_max_freq(rps); 1737 rps->rp0_freq = rps->max_freq; 1738 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", 1739 intel_gpu_freq(rps, rps->max_freq), rps->max_freq); 1740 1741 rps->efficient_freq = chv_rps_rpe_freq(rps); 1742 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", 1743 intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq); 1744 1745 rps->rp1_freq = chv_rps_guar_freq(rps); 1746 drm_dbg(&i915->drm, "RP1(Guar) GPU freq: %d MHz (%u)\n", 1747 intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq); 1748 1749 rps->min_freq = chv_rps_min_freq(rps); 1750 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", 1751 intel_gpu_freq(rps, rps->min_freq), rps->min_freq); 1752 1753 vlv_iosf_sb_put(i915, 1754 BIT(VLV_IOSF_SB_PUNIT) | 1755 BIT(VLV_IOSF_SB_NC) | 1756 BIT(VLV_IOSF_SB_CCK)); 1757 1758 drm_WARN_ONCE(&i915->drm, (rps->max_freq | rps->efficient_freq | 1759 rps->rp1_freq | rps->min_freq) & 1, 1760 "Odd GPU freq values\n"); 1761 } 1762 1763 static void vlv_c0_read(struct intel_uncore *uncore, struct intel_rps_ei *ei) 1764 { 1765 ei->ktime = ktime_get_raw(); 1766 ei->render_c0 = intel_uncore_read(uncore, VLV_RENDER_C0_COUNT); 1767 ei->media_c0 = intel_uncore_read(uncore, VLV_MEDIA_C0_COUNT); 1768 } 1769 1770 static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir) 1771 { 1772 struct intel_uncore *uncore = rps_to_uncore(rps); 1773 const struct intel_rps_ei *prev = &rps->ei; 1774 struct intel_rps_ei now; 1775 u32 events = 0; 1776 1777 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) 1778 return 0; 1779 1780 vlv_c0_read(uncore, &now); 1781 1782 if (prev->ktime) { 1783 u64 time, c0; 1784 u32 render, media; 1785 1786 time = ktime_us_delta(now.ktime, prev->ktime); 1787 1788 time *= rps_to_i915(rps)->czclk_freq; 1789 1790 /* Workload can be split between render + media, 1791 * e.g. SwapBuffers being blitted in X after being rendered in 1792 * mesa. To account for this we need to combine both engines 1793 * into our activity counter. 1794 */ 1795 render = now.render_c0 - prev->render_c0; 1796 media = now.media_c0 - prev->media_c0; 1797 c0 = max(render, media); 1798 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */ 1799 1800 if (c0 > time * rps->power.up_threshold) 1801 events = GEN6_PM_RP_UP_THRESHOLD; 1802 else if (c0 < time * rps->power.down_threshold) 1803 events = GEN6_PM_RP_DOWN_THRESHOLD; 1804 } 1805 1806 rps->ei = now; 1807 return events; 1808 } 1809 1810 static void rps_work(struct work_struct *work) 1811 { 1812 struct intel_rps *rps = container_of(work, typeof(*rps), work); 1813 struct intel_gt *gt = rps_to_gt(rps); 1814 struct drm_i915_private *i915 = rps_to_i915(rps); 1815 bool client_boost = false; 1816 int new_freq, adj, min, max; 1817 u32 pm_iir = 0; 1818 1819 spin_lock_irq(gt->irq_lock); 1820 pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events; 1821 client_boost = atomic_read(&rps->num_waiters); 1822 spin_unlock_irq(gt->irq_lock); 1823 1824 /* Make sure we didn't queue anything we're not going to process. */ 1825 if (!pm_iir && !client_boost) 1826 goto out; 1827 1828 mutex_lock(&rps->lock); 1829 if (!intel_rps_is_active(rps)) { 1830 mutex_unlock(&rps->lock); 1831 return; 1832 } 1833 1834 pm_iir |= vlv_wa_c0_ei(rps, pm_iir); 1835 1836 adj = rps->last_adj; 1837 new_freq = rps->cur_freq; 1838 min = rps->min_freq_softlimit; 1839 max = rps->max_freq_softlimit; 1840 if (client_boost) 1841 max = rps->max_freq; 1842 1843 GT_TRACE(gt, 1844 "pm_iir:%x, client_boost:%s, last:%d, cur:%x, min:%x, max:%x\n", 1845 pm_iir, str_yes_no(client_boost), 1846 adj, new_freq, min, max); 1847 1848 if (client_boost && new_freq < rps->boost_freq) { 1849 new_freq = rps->boost_freq; 1850 adj = 0; 1851 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 1852 if (adj > 0) 1853 adj *= 2; 1854 else /* CHV needs even encode values */ 1855 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; 1856 1857 if (new_freq >= rps->max_freq_softlimit) 1858 adj = 0; 1859 } else if (client_boost) { 1860 adj = 0; 1861 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { 1862 if (rps->cur_freq > rps->efficient_freq) 1863 new_freq = rps->efficient_freq; 1864 else if (rps->cur_freq > rps->min_freq_softlimit) 1865 new_freq = rps->min_freq_softlimit; 1866 adj = 0; 1867 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1868 if (adj < 0) 1869 adj *= 2; 1870 else /* CHV needs even encode values */ 1871 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; 1872 1873 if (new_freq <= rps->min_freq_softlimit) 1874 adj = 0; 1875 } else { /* unknown event */ 1876 adj = 0; 1877 } 1878 1879 /* 1880 * sysfs frequency limits may have snuck in while 1881 * servicing the interrupt 1882 */ 1883 new_freq += adj; 1884 new_freq = clamp_t(int, new_freq, min, max); 1885 1886 if (intel_rps_set(rps, new_freq)) { 1887 drm_dbg(&i915->drm, "Failed to set new GPU frequency\n"); 1888 adj = 0; 1889 } 1890 rps->last_adj = adj; 1891 1892 mutex_unlock(&rps->lock); 1893 1894 out: 1895 spin_lock_irq(gt->irq_lock); 1896 gen6_gt_pm_unmask_irq(gt, rps->pm_events); 1897 spin_unlock_irq(gt->irq_lock); 1898 } 1899 1900 void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) 1901 { 1902 struct intel_gt *gt = rps_to_gt(rps); 1903 const u32 events = rps->pm_events & pm_iir; 1904 1905 lockdep_assert_held(gt->irq_lock); 1906 1907 if (unlikely(!events)) 1908 return; 1909 1910 GT_TRACE(gt, "irq events:%x\n", events); 1911 1912 gen6_gt_pm_mask_irq(gt, events); 1913 1914 rps->pm_iir |= events; 1915 queue_work(gt->i915->unordered_wq, &rps->work); 1916 } 1917 1918 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) 1919 { 1920 struct intel_gt *gt = rps_to_gt(rps); 1921 u32 events; 1922 1923 events = pm_iir & rps->pm_events; 1924 if (events) { 1925 spin_lock(gt->irq_lock); 1926 1927 GT_TRACE(gt, "irq events:%x\n", events); 1928 1929 gen6_gt_pm_mask_irq(gt, events); 1930 rps->pm_iir |= events; 1931 1932 queue_work(gt->i915->unordered_wq, &rps->work); 1933 spin_unlock(gt->irq_lock); 1934 } 1935 1936 if (GRAPHICS_VER(gt->i915) >= 8) 1937 return; 1938 1939 if (pm_iir & PM_VEBOX_USER_INTERRUPT) 1940 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); 1941 1942 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) 1943 drm_dbg(&rps_to_i915(rps)->drm, 1944 "Command parser error, pm_iir 0x%08x\n", pm_iir); 1945 } 1946 1947 void gen5_rps_irq_handler(struct intel_rps *rps) 1948 { 1949 struct intel_uncore *uncore = rps_to_uncore(rps); 1950 u32 busy_up, busy_down, max_avg, min_avg; 1951 u8 new_freq; 1952 1953 spin_lock(&mchdev_lock); 1954 1955 intel_uncore_write16(uncore, 1956 MEMINTRSTS, 1957 intel_uncore_read(uncore, MEMINTRSTS)); 1958 1959 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG); 1960 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG); 1961 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG); 1962 max_avg = intel_uncore_read(uncore, RCBMAXAVG); 1963 min_avg = intel_uncore_read(uncore, RCBMINAVG); 1964 1965 /* Handle RCS change request from hw */ 1966 new_freq = rps->cur_freq; 1967 if (busy_up > max_avg) 1968 new_freq++; 1969 else if (busy_down < min_avg) 1970 new_freq--; 1971 new_freq = clamp(new_freq, 1972 rps->min_freq_softlimit, 1973 rps->max_freq_softlimit); 1974 1975 if (new_freq != rps->cur_freq && !__gen5_rps_set(rps, new_freq)) 1976 rps->cur_freq = new_freq; 1977 1978 spin_unlock(&mchdev_lock); 1979 } 1980 1981 void intel_rps_init_early(struct intel_rps *rps) 1982 { 1983 mutex_init(&rps->lock); 1984 mutex_init(&rps->power.mutex); 1985 1986 INIT_WORK(&rps->work, rps_work); 1987 timer_setup(&rps->timer, rps_timer, 0); 1988 1989 atomic_set(&rps->num_waiters, 0); 1990 } 1991 1992 void intel_rps_init(struct intel_rps *rps) 1993 { 1994 struct drm_i915_private *i915 = rps_to_i915(rps); 1995 1996 if (rps_uses_slpc(rps)) 1997 return; 1998 1999 if (IS_CHERRYVIEW(i915)) 2000 chv_rps_init(rps); 2001 else if (IS_VALLEYVIEW(i915)) 2002 vlv_rps_init(rps); 2003 else if (GRAPHICS_VER(i915) >= 6) 2004 gen6_rps_init(rps); 2005 else if (IS_IRONLAKE_M(i915)) 2006 gen5_rps_init(rps); 2007 2008 /* Derive initial user preferences/limits from the hardware limits */ 2009 rps->max_freq_softlimit = rps->max_freq; 2010 rps_to_gt(rps)->defaults.max_freq = rps->max_freq_softlimit; 2011 rps->min_freq_softlimit = rps->min_freq; 2012 rps_to_gt(rps)->defaults.min_freq = rps->min_freq_softlimit; 2013 2014 /* After setting max-softlimit, find the overclock max freq */ 2015 if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) { 2016 u32 params = 0; 2017 2018 snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_READ_OC_PARAMS, ¶ms, NULL); 2019 if (params & BIT(31)) { /* OC supported */ 2020 drm_dbg(&i915->drm, 2021 "Overclocking supported, max: %dMHz, overclock: %dMHz\n", 2022 (rps->max_freq & 0xff) * 50, 2023 (params & 0xff) * 50); 2024 rps->max_freq = params & 0xff; 2025 } 2026 } 2027 2028 /* Set default thresholds in % */ 2029 rps->power.up_threshold = 95; 2030 rps_to_gt(rps)->defaults.rps_up_threshold = rps->power.up_threshold; 2031 rps->power.down_threshold = 85; 2032 rps_to_gt(rps)->defaults.rps_down_threshold = rps->power.down_threshold; 2033 2034 /* Finally allow us to boost to max by default */ 2035 rps->boost_freq = rps->max_freq; 2036 rps->idle_freq = rps->min_freq; 2037 2038 /* Start in the middle, from here we will autotune based on workload */ 2039 rps->cur_freq = rps->efficient_freq; 2040 2041 rps->pm_intrmsk_mbz = 0; 2042 2043 /* 2044 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer 2045 * if GEN6_PM_UP_EI_EXPIRED is masked. 2046 * 2047 * TODO: verify if this can be reproduced on VLV,CHV. 2048 */ 2049 if (GRAPHICS_VER(i915) <= 7) 2050 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; 2051 2052 if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11) 2053 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; 2054 2055 /* GuC needs ARAT expired interrupt unmasked */ 2056 if (intel_uc_uses_guc_submission(&rps_to_gt(rps)->uc)) 2057 rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; 2058 } 2059 2060 void intel_rps_sanitize(struct intel_rps *rps) 2061 { 2062 if (rps_uses_slpc(rps)) 2063 return; 2064 2065 if (GRAPHICS_VER(rps_to_i915(rps)) >= 6) 2066 rps_disable_interrupts(rps); 2067 } 2068 2069 u32 intel_rps_read_rpstat(struct intel_rps *rps) 2070 { 2071 struct drm_i915_private *i915 = rps_to_i915(rps); 2072 i915_reg_t rpstat; 2073 2074 rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; 2075 2076 return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); 2077 } 2078 2079 static u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) 2080 { 2081 struct drm_i915_private *i915 = rps_to_i915(rps); 2082 u32 cagf; 2083 2084 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 2085 cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat); 2086 else if (GRAPHICS_VER(i915) >= 12) 2087 cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); 2088 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 2089 cagf = REG_FIELD_GET(RPE_MASK, rpstat); 2090 else if (GRAPHICS_VER(i915) >= 9) 2091 cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat); 2092 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 2093 cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat); 2094 else if (GRAPHICS_VER(i915) >= 6) 2095 cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat); 2096 else 2097 cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat)); 2098 2099 return cagf; 2100 } 2101 2102 static u32 __read_cagf(struct intel_rps *rps, bool take_fw) 2103 { 2104 struct drm_i915_private *i915 = rps_to_i915(rps); 2105 struct intel_uncore *uncore = rps_to_uncore(rps); 2106 i915_reg_t r = INVALID_MMIO_REG; 2107 u32 freq; 2108 2109 /* 2110 * For Gen12+ reading freq from HW does not need a forcewake and 2111 * registers will return 0 freq when GT is in RC6 2112 */ 2113 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { 2114 r = MTL_MIRROR_TARGET_WP1; 2115 } else if (GRAPHICS_VER(i915) >= 12) { 2116 r = GEN12_RPSTAT1; 2117 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 2118 vlv_punit_get(i915); 2119 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 2120 vlv_punit_put(i915); 2121 } else if (GRAPHICS_VER(i915) >= 6) { 2122 r = GEN6_RPSTAT1; 2123 } else { 2124 r = MEMSTAT_ILK; 2125 } 2126 2127 if (i915_mmio_reg_valid(r)) 2128 freq = take_fw ? intel_uncore_read(uncore, r) : intel_uncore_read_fw(uncore, r); 2129 2130 return intel_rps_get_cagf(rps, freq); 2131 } 2132 2133 static u32 read_cagf(struct intel_rps *rps) 2134 { 2135 return __read_cagf(rps, true); 2136 } 2137 2138 u32 intel_rps_read_actual_frequency(struct intel_rps *rps) 2139 { 2140 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; 2141 intel_wakeref_t wakeref; 2142 u32 freq = 0; 2143 2144 with_intel_runtime_pm_if_in_use(rpm, wakeref) 2145 freq = intel_gpu_freq(rps, read_cagf(rps)); 2146 2147 return freq; 2148 } 2149 2150 u32 intel_rps_read_actual_frequency_fw(struct intel_rps *rps) 2151 { 2152 return intel_gpu_freq(rps, __read_cagf(rps, false)); 2153 } 2154 2155 static u32 intel_rps_read_punit_req(struct intel_rps *rps) 2156 { 2157 struct intel_uncore *uncore = rps_to_uncore(rps); 2158 struct intel_runtime_pm *rpm = rps_to_uncore(rps)->rpm; 2159 intel_wakeref_t wakeref; 2160 u32 freq = 0; 2161 2162 with_intel_runtime_pm_if_in_use(rpm, wakeref) 2163 freq = intel_uncore_read(uncore, GEN6_RPNSWREQ); 2164 2165 return freq; 2166 } 2167 2168 static u32 intel_rps_get_req(u32 pureq) 2169 { 2170 u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT; 2171 2172 return req; 2173 } 2174 2175 u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps) 2176 { 2177 u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps)); 2178 2179 return intel_gpu_freq(rps, freq); 2180 } 2181 2182 u32 intel_rps_get_requested_frequency(struct intel_rps *rps) 2183 { 2184 if (rps_uses_slpc(rps)) 2185 return intel_rps_read_punit_req_frequency(rps); 2186 else 2187 return intel_gpu_freq(rps, rps->cur_freq); 2188 } 2189 2190 u32 intel_rps_get_max_frequency(struct intel_rps *rps) 2191 { 2192 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2193 2194 if (rps_uses_slpc(rps)) 2195 return slpc->max_freq_softlimit; 2196 else 2197 return intel_gpu_freq(rps, rps->max_freq_softlimit); 2198 } 2199 2200 /** 2201 * intel_rps_get_max_raw_freq - returns the max frequency in some raw format. 2202 * @rps: the intel_rps structure 2203 * 2204 * Returns the max frequency in a raw format. In newer platforms raw is in 2205 * units of 50 MHz. 2206 */ 2207 u32 intel_rps_get_max_raw_freq(struct intel_rps *rps) 2208 { 2209 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2210 u32 freq; 2211 2212 if (rps_uses_slpc(rps)) { 2213 return DIV_ROUND_CLOSEST(slpc->rp0_freq, 2214 GT_FREQUENCY_MULTIPLIER); 2215 } else { 2216 freq = rps->max_freq; 2217 if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) { 2218 /* Convert GT frequency to 50 MHz units */ 2219 freq /= GEN9_FREQ_SCALER; 2220 } 2221 return freq; 2222 } 2223 } 2224 2225 u32 intel_rps_get_rp0_frequency(struct intel_rps *rps) 2226 { 2227 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2228 2229 if (rps_uses_slpc(rps)) 2230 return slpc->rp0_freq; 2231 else 2232 return intel_gpu_freq(rps, rps->rp0_freq); 2233 } 2234 2235 u32 intel_rps_get_rp1_frequency(struct intel_rps *rps) 2236 { 2237 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2238 2239 if (rps_uses_slpc(rps)) 2240 return slpc->rp1_freq; 2241 else 2242 return intel_gpu_freq(rps, rps->rp1_freq); 2243 } 2244 2245 u32 intel_rps_get_rpn_frequency(struct intel_rps *rps) 2246 { 2247 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2248 2249 if (rps_uses_slpc(rps)) 2250 return slpc->min_freq; 2251 else 2252 return intel_gpu_freq(rps, rps->min_freq); 2253 } 2254 2255 static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) 2256 { 2257 struct intel_gt *gt = rps_to_gt(rps); 2258 struct drm_i915_private *i915 = gt->i915; 2259 struct intel_uncore *uncore = gt->uncore; 2260 struct intel_rps_freq_caps caps; 2261 u32 rp_state_limits; 2262 u32 gt_perf_status; 2263 u32 rpmodectl, rpinclimit, rpdeclimit; 2264 u32 rpstat, cagf, reqf; 2265 u32 rpcurupei, rpcurup, rpprevup; 2266 u32 rpcurdownei, rpcurdown, rpprevdown; 2267 u32 rpupei, rpupt, rpdownei, rpdownt; 2268 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 2269 2270 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS); 2271 gen6_rps_get_freq_caps(rps, &caps); 2272 if (IS_GEN9_LP(i915)) 2273 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS); 2274 else 2275 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS); 2276 2277 /* RPSTAT1 is in the GT power well */ 2278 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 2279 2280 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ); 2281 if (GRAPHICS_VER(i915) >= 9) { 2282 reqf >>= 23; 2283 } else { 2284 reqf &= ~GEN6_TURBO_DISABLE; 2285 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 2286 reqf >>= 24; 2287 else 2288 reqf >>= 25; 2289 } 2290 reqf = intel_gpu_freq(rps, reqf); 2291 2292 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 2293 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 2294 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 2295 2296 rpstat = intel_rps_read_rpstat(rps); 2297 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 2298 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 2299 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 2300 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 2301 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 2302 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 2303 2304 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI); 2305 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); 2306 2307 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI); 2308 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); 2309 2310 cagf = intel_rps_read_actual_frequency(rps); 2311 2312 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 2313 2314 if (GRAPHICS_VER(i915) >= 11) { 2315 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); 2316 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); 2317 /* 2318 * The equivalent to the PM ISR & IIR cannot be read 2319 * without affecting the current state of the system 2320 */ 2321 pm_isr = 0; 2322 pm_iir = 0; 2323 } else if (GRAPHICS_VER(i915) >= 8) { 2324 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2)); 2325 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2)); 2326 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2)); 2327 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2)); 2328 } else { 2329 pm_ier = intel_uncore_read(uncore, GEN6_PMIER); 2330 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR); 2331 pm_isr = intel_uncore_read(uncore, GEN6_PMISR); 2332 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR); 2333 } 2334 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); 2335 2336 drm_printf(p, "Video Turbo Mode: %s\n", 2337 str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO)); 2338 drm_printf(p, "HW control enabled: %s\n", 2339 str_yes_no(rpmodectl & GEN6_RP_ENABLE)); 2340 drm_printf(p, "SW control enabled: %s\n", 2341 str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); 2342 2343 drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", 2344 pm_ier, pm_imr, pm_mask); 2345 if (GRAPHICS_VER(i915) <= 10) 2346 drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n", 2347 pm_isr, pm_iir); 2348 drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", 2349 rps->pm_intrmsk_mbz); 2350 drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 2351 drm_printf(p, "Render p-state ratio: %d\n", 2352 (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8); 2353 drm_printf(p, "Render p-state VID: %d\n", 2354 gt_perf_status & 0xff); 2355 drm_printf(p, "Render p-state limit: %d\n", 2356 rp_state_limits & 0xff); 2357 drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat); 2358 drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl); 2359 drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit); 2360 drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 2361 drm_printf(p, "RPNSWREQ: %dMHz\n", reqf); 2362 drm_printf(p, "CAGF: %dMHz\n", cagf); 2363 drm_printf(p, "RP CUR UP EI: %d (%lldns)\n", 2364 rpcurupei, 2365 intel_gt_pm_interval_to_ns(gt, rpcurupei)); 2366 drm_printf(p, "RP CUR UP: %d (%lldns)\n", 2367 rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); 2368 drm_printf(p, "RP PREV UP: %d (%lldns)\n", 2369 rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); 2370 drm_printf(p, "Up threshold: %d%%\n", 2371 rps->power.up_threshold); 2372 drm_printf(p, "RP UP EI: %d (%lldns)\n", 2373 rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); 2374 drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n", 2375 rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); 2376 2377 drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n", 2378 rpcurdownei, 2379 intel_gt_pm_interval_to_ns(gt, rpcurdownei)); 2380 drm_printf(p, "RP CUR DOWN: %d (%lldns)\n", 2381 rpcurdown, 2382 intel_gt_pm_interval_to_ns(gt, rpcurdown)); 2383 drm_printf(p, "RP PREV DOWN: %d (%lldns)\n", 2384 rpprevdown, 2385 intel_gt_pm_interval_to_ns(gt, rpprevdown)); 2386 drm_printf(p, "Down threshold: %d%%\n", 2387 rps->power.down_threshold); 2388 drm_printf(p, "RP DOWN EI: %d (%lldns)\n", 2389 rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); 2390 drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n", 2391 rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); 2392 2393 drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", 2394 intel_gpu_freq(rps, caps.min_freq)); 2395 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", 2396 intel_gpu_freq(rps, caps.rp1_freq)); 2397 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", 2398 intel_gpu_freq(rps, caps.rp0_freq)); 2399 drm_printf(p, "Max overclocked frequency: %dMHz\n", 2400 intel_gpu_freq(rps, rps->max_freq)); 2401 2402 drm_printf(p, "Current freq: %d MHz\n", 2403 intel_gpu_freq(rps, rps->cur_freq)); 2404 drm_printf(p, "Actual freq: %d MHz\n", cagf); 2405 drm_printf(p, "Idle freq: %d MHz\n", 2406 intel_gpu_freq(rps, rps->idle_freq)); 2407 drm_printf(p, "Min freq: %d MHz\n", 2408 intel_gpu_freq(rps, rps->min_freq)); 2409 drm_printf(p, "Boost freq: %d MHz\n", 2410 intel_gpu_freq(rps, rps->boost_freq)); 2411 drm_printf(p, "Max freq: %d MHz\n", 2412 intel_gpu_freq(rps, rps->max_freq)); 2413 drm_printf(p, 2414 "efficient (RPe) frequency: %d MHz\n", 2415 intel_gpu_freq(rps, rps->efficient_freq)); 2416 } 2417 2418 static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) 2419 { 2420 struct intel_gt *gt = rps_to_gt(rps); 2421 struct intel_uncore *uncore = gt->uncore; 2422 struct intel_rps_freq_caps caps; 2423 u32 pm_mask; 2424 2425 gen6_rps_get_freq_caps(rps, &caps); 2426 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); 2427 2428 drm_printf(p, "PM MASK=0x%08x\n", pm_mask); 2429 drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", 2430 rps->pm_intrmsk_mbz); 2431 drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps)); 2432 drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); 2433 drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", 2434 intel_gpu_freq(rps, caps.min_freq)); 2435 drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", 2436 intel_gpu_freq(rps, caps.rp1_freq)); 2437 drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", 2438 intel_gpu_freq(rps, caps.rp0_freq)); 2439 drm_printf(p, "Current freq: %d MHz\n", 2440 intel_rps_get_requested_frequency(rps)); 2441 drm_printf(p, "Actual freq: %d MHz\n", 2442 intel_rps_read_actual_frequency(rps)); 2443 drm_printf(p, "Min freq: %d MHz\n", 2444 intel_rps_get_min_frequency(rps)); 2445 drm_printf(p, "Boost freq: %d MHz\n", 2446 intel_rps_get_boost_frequency(rps)); 2447 drm_printf(p, "Max freq: %d MHz\n", 2448 intel_rps_get_max_frequency(rps)); 2449 drm_printf(p, 2450 "efficient (RPe) frequency: %d MHz\n", 2451 intel_gpu_freq(rps, caps.rp1_freq)); 2452 } 2453 2454 void gen6_rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) 2455 { 2456 if (rps_uses_slpc(rps)) 2457 return slpc_frequency_dump(rps, p); 2458 else 2459 return rps_frequency_dump(rps, p); 2460 } 2461 2462 static int set_max_freq(struct intel_rps *rps, u32 val) 2463 { 2464 struct drm_i915_private *i915 = rps_to_i915(rps); 2465 int ret = 0; 2466 2467 mutex_lock(&rps->lock); 2468 2469 val = intel_freq_opcode(rps, val); 2470 if (val < rps->min_freq || 2471 val > rps->max_freq || 2472 val < rps->min_freq_softlimit) { 2473 ret = -EINVAL; 2474 goto unlock; 2475 } 2476 2477 if (val > rps->rp0_freq) 2478 drm_dbg(&i915->drm, "User requested overclocking to %d\n", 2479 intel_gpu_freq(rps, val)); 2480 2481 rps->max_freq_softlimit = val; 2482 2483 val = clamp_t(int, rps->cur_freq, 2484 rps->min_freq_softlimit, 2485 rps->max_freq_softlimit); 2486 2487 /* 2488 * We still need *_set_rps to process the new max_delay and 2489 * update the interrupt limits and PMINTRMSK even though 2490 * frequency request may be unchanged. 2491 */ 2492 intel_rps_set(rps, val); 2493 2494 unlock: 2495 mutex_unlock(&rps->lock); 2496 2497 return ret; 2498 } 2499 2500 int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val) 2501 { 2502 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2503 2504 if (rps_uses_slpc(rps)) 2505 return intel_guc_slpc_set_max_freq(slpc, val); 2506 else 2507 return set_max_freq(rps, val); 2508 } 2509 2510 u32 intel_rps_get_min_frequency(struct intel_rps *rps) 2511 { 2512 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2513 2514 if (rps_uses_slpc(rps)) 2515 return slpc->min_freq_softlimit; 2516 else 2517 return intel_gpu_freq(rps, rps->min_freq_softlimit); 2518 } 2519 2520 /** 2521 * intel_rps_get_min_raw_freq - returns the min frequency in some raw format. 2522 * @rps: the intel_rps structure 2523 * 2524 * Returns the min frequency in a raw format. In newer platforms raw is in 2525 * units of 50 MHz. 2526 */ 2527 u32 intel_rps_get_min_raw_freq(struct intel_rps *rps) 2528 { 2529 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2530 u32 freq; 2531 2532 if (rps_uses_slpc(rps)) { 2533 return DIV_ROUND_CLOSEST(slpc->min_freq, 2534 GT_FREQUENCY_MULTIPLIER); 2535 } else { 2536 freq = rps->min_freq; 2537 if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) { 2538 /* Convert GT frequency to 50 MHz units */ 2539 freq /= GEN9_FREQ_SCALER; 2540 } 2541 return freq; 2542 } 2543 } 2544 2545 static int set_min_freq(struct intel_rps *rps, u32 val) 2546 { 2547 int ret = 0; 2548 2549 mutex_lock(&rps->lock); 2550 2551 val = intel_freq_opcode(rps, val); 2552 if (val < rps->min_freq || 2553 val > rps->max_freq || 2554 val > rps->max_freq_softlimit) { 2555 ret = -EINVAL; 2556 goto unlock; 2557 } 2558 2559 rps->min_freq_softlimit = val; 2560 2561 val = clamp_t(int, rps->cur_freq, 2562 rps->min_freq_softlimit, 2563 rps->max_freq_softlimit); 2564 2565 /* 2566 * We still need *_set_rps to process the new min_delay and 2567 * update the interrupt limits and PMINTRMSK even though 2568 * frequency request may be unchanged. 2569 */ 2570 intel_rps_set(rps, val); 2571 2572 unlock: 2573 mutex_unlock(&rps->lock); 2574 2575 return ret; 2576 } 2577 2578 int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val) 2579 { 2580 struct intel_guc_slpc *slpc = rps_to_slpc(rps); 2581 2582 if (rps_uses_slpc(rps)) 2583 return intel_guc_slpc_set_min_freq(slpc, val); 2584 else 2585 return set_min_freq(rps, val); 2586 } 2587 2588 u8 intel_rps_get_up_threshold(struct intel_rps *rps) 2589 { 2590 return rps->power.up_threshold; 2591 } 2592 2593 static int rps_set_threshold(struct intel_rps *rps, u8 *threshold, u8 val) 2594 { 2595 int ret; 2596 2597 if (val > 100) 2598 return -EINVAL; 2599 2600 ret = mutex_lock_interruptible(&rps->lock); 2601 if (ret) 2602 return ret; 2603 2604 if (*threshold == val) 2605 goto out_unlock; 2606 2607 *threshold = val; 2608 2609 /* Force reset. */ 2610 rps->last_freq = -1; 2611 mutex_lock(&rps->power.mutex); 2612 rps->power.mode = -1; 2613 mutex_unlock(&rps->power.mutex); 2614 2615 intel_rps_set(rps, clamp(rps->cur_freq, 2616 rps->min_freq_softlimit, 2617 rps->max_freq_softlimit)); 2618 2619 out_unlock: 2620 mutex_unlock(&rps->lock); 2621 2622 return ret; 2623 } 2624 2625 int intel_rps_set_up_threshold(struct intel_rps *rps, u8 threshold) 2626 { 2627 return rps_set_threshold(rps, &rps->power.up_threshold, threshold); 2628 } 2629 2630 u8 intel_rps_get_down_threshold(struct intel_rps *rps) 2631 { 2632 return rps->power.down_threshold; 2633 } 2634 2635 int intel_rps_set_down_threshold(struct intel_rps *rps, u8 threshold) 2636 { 2637 return rps_set_threshold(rps, &rps->power.down_threshold, threshold); 2638 } 2639 2640 static void intel_rps_set_manual(struct intel_rps *rps, bool enable) 2641 { 2642 struct intel_uncore *uncore = rps_to_uncore(rps); 2643 u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE; 2644 2645 /* Allow punit to process software requests */ 2646 intel_uncore_write(uncore, GEN6_RP_CONTROL, state); 2647 } 2648 2649 void intel_rps_raise_unslice(struct intel_rps *rps) 2650 { 2651 struct intel_uncore *uncore = rps_to_uncore(rps); 2652 2653 mutex_lock(&rps->lock); 2654 2655 if (rps_uses_slpc(rps)) { 2656 /* RP limits have not been initialized yet for SLPC path */ 2657 struct intel_rps_freq_caps caps; 2658 2659 gen6_rps_get_freq_caps(rps, &caps); 2660 2661 intel_rps_set_manual(rps, true); 2662 intel_uncore_write(uncore, GEN6_RPNSWREQ, 2663 ((caps.rp0_freq << 2664 GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | 2665 GEN9_IGNORE_SLICE_RATIO)); 2666 intel_rps_set_manual(rps, false); 2667 } else { 2668 intel_rps_set(rps, rps->rp0_freq); 2669 } 2670 2671 mutex_unlock(&rps->lock); 2672 } 2673 2674 void intel_rps_lower_unslice(struct intel_rps *rps) 2675 { 2676 struct intel_uncore *uncore = rps_to_uncore(rps); 2677 2678 mutex_lock(&rps->lock); 2679 2680 if (rps_uses_slpc(rps)) { 2681 /* RP limits have not been initialized yet for SLPC path */ 2682 struct intel_rps_freq_caps caps; 2683 2684 gen6_rps_get_freq_caps(rps, &caps); 2685 2686 intel_rps_set_manual(rps, true); 2687 intel_uncore_write(uncore, GEN6_RPNSWREQ, 2688 ((caps.min_freq << 2689 GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | 2690 GEN9_IGNORE_SLICE_RATIO)); 2691 intel_rps_set_manual(rps, false); 2692 } else { 2693 intel_rps_set(rps, rps->min_freq); 2694 } 2695 2696 mutex_unlock(&rps->lock); 2697 } 2698 2699 static u32 rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32) 2700 { 2701 struct intel_gt *gt = rps_to_gt(rps); 2702 intel_wakeref_t wakeref; 2703 u32 val; 2704 2705 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 2706 val = intel_uncore_read(gt->uncore, reg32); 2707 2708 return val; 2709 } 2710 2711 bool rps_read_mask_mmio(struct intel_rps *rps, 2712 i915_reg_t reg32, u32 mask) 2713 { 2714 return rps_read_mmio(rps, reg32) & mask; 2715 } 2716 2717 /* External interface for intel_ips.ko */ 2718 2719 static struct drm_i915_private __rcu *ips_mchdev; 2720 2721 /* 2722 * Tells the intel_ips driver that the i915 driver is now loaded, if 2723 * IPS got loaded first. 2724 * 2725 * This awkward dance is so that neither module has to depend on the 2726 * other in order for IPS to do the appropriate communication of 2727 * GPU turbo limits to i915. 2728 */ 2729 static void 2730 ips_ping_for_i915_load(void) 2731 { 2732 void (*link)(void); 2733 2734 link = symbol_get(ips_link_to_i915_driver); 2735 if (link) { 2736 link(); 2737 symbol_put(ips_link_to_i915_driver); 2738 } 2739 } 2740 2741 void intel_rps_driver_register(struct intel_rps *rps) 2742 { 2743 struct intel_gt *gt = rps_to_gt(rps); 2744 2745 /* 2746 * We only register the i915 ips part with intel-ips once everything is 2747 * set up, to avoid intel-ips sneaking in and reading bogus values. 2748 */ 2749 if (GRAPHICS_VER(gt->i915) == 5) { 2750 GEM_BUG_ON(ips_mchdev); 2751 rcu_assign_pointer(ips_mchdev, gt->i915); 2752 ips_ping_for_i915_load(); 2753 } 2754 } 2755 2756 void intel_rps_driver_unregister(struct intel_rps *rps) 2757 { 2758 if (rcu_access_pointer(ips_mchdev) == rps_to_i915(rps)) 2759 rcu_assign_pointer(ips_mchdev, NULL); 2760 } 2761 2762 static struct drm_i915_private *mchdev_get(void) 2763 { 2764 struct drm_i915_private *i915; 2765 2766 rcu_read_lock(); 2767 i915 = rcu_dereference(ips_mchdev); 2768 if (i915 && !kref_get_unless_zero(&i915->drm.ref)) 2769 i915 = NULL; 2770 rcu_read_unlock(); 2771 2772 return i915; 2773 } 2774 2775 /** 2776 * i915_read_mch_val - return value for IPS use 2777 * 2778 * Calculate and return a value for the IPS driver to use when deciding whether 2779 * we have thermal and power headroom to increase CPU or GPU power budget. 2780 */ 2781 unsigned long i915_read_mch_val(void) 2782 { 2783 struct drm_i915_private *i915; 2784 unsigned long chipset_val = 0; 2785 unsigned long graphics_val = 0; 2786 intel_wakeref_t wakeref; 2787 2788 i915 = mchdev_get(); 2789 if (!i915) 2790 return 0; 2791 2792 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 2793 struct intel_ips *ips = &to_gt(i915)->rps.ips; 2794 2795 spin_lock_irq(&mchdev_lock); 2796 chipset_val = __ips_chipset_val(ips); 2797 graphics_val = __ips_gfx_val(ips); 2798 spin_unlock_irq(&mchdev_lock); 2799 } 2800 2801 drm_dev_put(&i915->drm); 2802 return chipset_val + graphics_val; 2803 } 2804 EXPORT_SYMBOL_GPL(i915_read_mch_val); 2805 2806 /** 2807 * i915_gpu_raise - raise GPU frequency limit 2808 * 2809 * Raise the limit; IPS indicates we have thermal headroom. 2810 */ 2811 bool i915_gpu_raise(void) 2812 { 2813 struct drm_i915_private *i915; 2814 struct intel_rps *rps; 2815 2816 i915 = mchdev_get(); 2817 if (!i915) 2818 return false; 2819 2820 rps = &to_gt(i915)->rps; 2821 2822 spin_lock_irq(&mchdev_lock); 2823 if (rps->max_freq_softlimit < rps->max_freq) 2824 rps->max_freq_softlimit++; 2825 spin_unlock_irq(&mchdev_lock); 2826 2827 drm_dev_put(&i915->drm); 2828 return true; 2829 } 2830 EXPORT_SYMBOL_GPL(i915_gpu_raise); 2831 2832 /** 2833 * i915_gpu_lower - lower GPU frequency limit 2834 * 2835 * IPS indicates we're close to a thermal limit, so throttle back the GPU 2836 * frequency maximum. 2837 */ 2838 bool i915_gpu_lower(void) 2839 { 2840 struct drm_i915_private *i915; 2841 struct intel_rps *rps; 2842 2843 i915 = mchdev_get(); 2844 if (!i915) 2845 return false; 2846 2847 rps = &to_gt(i915)->rps; 2848 2849 spin_lock_irq(&mchdev_lock); 2850 if (rps->max_freq_softlimit > rps->min_freq) 2851 rps->max_freq_softlimit--; 2852 spin_unlock_irq(&mchdev_lock); 2853 2854 drm_dev_put(&i915->drm); 2855 return true; 2856 } 2857 EXPORT_SYMBOL_GPL(i915_gpu_lower); 2858 2859 /** 2860 * i915_gpu_busy - indicate GPU business to IPS 2861 * 2862 * Tell the IPS driver whether or not the GPU is busy. 2863 */ 2864 bool i915_gpu_busy(void) 2865 { 2866 struct drm_i915_private *i915; 2867 bool ret; 2868 2869 i915 = mchdev_get(); 2870 if (!i915) 2871 return false; 2872 2873 ret = to_gt(i915)->awake; 2874 2875 drm_dev_put(&i915->drm); 2876 return ret; 2877 } 2878 EXPORT_SYMBOL_GPL(i915_gpu_busy); 2879 2880 /** 2881 * i915_gpu_turbo_disable - disable graphics turbo 2882 * 2883 * Disable graphics turbo by resetting the max frequency and setting the 2884 * current frequency to the default. 2885 */ 2886 bool i915_gpu_turbo_disable(void) 2887 { 2888 struct drm_i915_private *i915; 2889 struct intel_rps *rps; 2890 bool ret; 2891 2892 i915 = mchdev_get(); 2893 if (!i915) 2894 return false; 2895 2896 rps = &to_gt(i915)->rps; 2897 2898 spin_lock_irq(&mchdev_lock); 2899 rps->max_freq_softlimit = rps->min_freq; 2900 ret = !__gen5_rps_set(&to_gt(i915)->rps, rps->min_freq); 2901 spin_unlock_irq(&mchdev_lock); 2902 2903 drm_dev_put(&i915->drm); 2904 return ret; 2905 } 2906 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 2907 2908 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2909 #include "selftest_rps.c" 2910 #include "selftest_slpc.c" 2911 #endif 2912