xref: /linux/drivers/gpu/drm/i915/gt/intel_renderstate.h (revision a4eb44a6435d6d8f9e642407a4a06f65eb90ca04)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2014 Intel Corporation
4  */
5 
6 #ifndef _INTEL_RENDERSTATE_H_
7 #define _INTEL_RENDERSTATE_H_
8 
9 #include <linux/types.h>
10 #include "i915_gem.h"
11 #include "i915_gem_ww.h"
12 
13 struct i915_request;
14 struct intel_context;
15 struct i915_vma;
16 
17 struct intel_renderstate_rodata {
18 	const u32 *reloc;
19 	const u32 *batch;
20 	const u32 batch_items;
21 };
22 
23 #define RO_RENDERSTATE(_g)						\
24 	const struct intel_renderstate_rodata gen ## _g ## _null_state = { \
25 		.reloc = gen ## _g ## _null_state_relocs,		\
26 		.batch = gen ## _g ## _null_state_batch,		\
27 		.batch_items = sizeof(gen ## _g ## _null_state_batch)/4, \
28 	}
29 
30 extern const struct intel_renderstate_rodata gen6_null_state;
31 extern const struct intel_renderstate_rodata gen7_null_state;
32 extern const struct intel_renderstate_rodata gen8_null_state;
33 extern const struct intel_renderstate_rodata gen9_null_state;
34 
35 struct intel_renderstate {
36 	struct i915_gem_ww_ctx ww;
37 	const struct intel_renderstate_rodata *rodata;
38 	struct i915_vma *vma;
39 	u32 batch_offset;
40 	u32 batch_size;
41 	u32 aux_offset;
42 	u32 aux_size;
43 };
44 
45 int intel_renderstate_init(struct intel_renderstate *so,
46 			   struct intel_context *ce);
47 int intel_renderstate_emit(struct intel_renderstate *so,
48 			   struct i915_request *rq);
49 void intel_renderstate_fini(struct intel_renderstate *so,
50 			    struct intel_context *ce);
51 
52 #endif /* _INTEL_RENDERSTATE_H_ */
53