1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #ifndef _INTEL_LRC_REG_H_ 8 #define _INTEL_LRC_REG_H_ 9 10 #include <linux/types.h> 11 12 /* GEN8+ Reg State Context */ 13 #define CTX_LRI_HEADER_0 0x01 14 #define CTX_CONTEXT_CONTROL 0x02 15 #define CTX_RING_HEAD 0x04 16 #define CTX_RING_TAIL 0x06 17 #define CTX_RING_BUFFER_START 0x08 18 #define CTX_RING_BUFFER_CONTROL 0x0a 19 #define CTX_BB_HEAD_U 0x0c 20 #define CTX_BB_HEAD_L 0x0e 21 #define CTX_BB_STATE 0x10 22 #define CTX_SECOND_BB_HEAD_U 0x12 23 #define CTX_SECOND_BB_HEAD_L 0x14 24 #define CTX_SECOND_BB_STATE 0x16 25 #define CTX_BB_PER_CTX_PTR 0x18 26 #define CTX_RCS_INDIRECT_CTX 0x1a 27 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c 28 #define CTX_LRI_HEADER_1 0x21 29 #define CTX_CTX_TIMESTAMP 0x22 30 #define CTX_PDP3_UDW 0x24 31 #define CTX_PDP3_LDW 0x26 32 #define CTX_PDP2_UDW 0x28 33 #define CTX_PDP2_LDW 0x2a 34 #define CTX_PDP1_UDW 0x2c 35 #define CTX_PDP1_LDW 0x2e 36 #define CTX_PDP0_UDW 0x30 37 #define CTX_PDP0_LDW 0x32 38 #define CTX_LRI_HEADER_2 0x41 39 #define CTX_R_PWR_CLK_STATE 0x42 40 #define CTX_END 0x44 41 42 #define CTX_REG(reg_state, pos, reg, val) do { \ 43 u32 *reg_state__ = (reg_state); \ 44 const u32 pos__ = (pos); \ 45 (reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \ 46 (reg_state__)[(pos__) + 1] = (val); \ 47 } while (0) 48 49 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ 50 u32 *reg_state__ = (reg_state); \ 51 const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \ 52 (reg_state__)[CTX_PDP ## n ## _UDW + 1] = upper_32_bits(addr__); \ 53 (reg_state__)[CTX_PDP ## n ## _LDW + 1] = lower_32_bits(addr__); \ 54 } while (0) 55 56 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ 57 u32 *reg_state__ = (reg_state); \ 58 const u64 addr__ = px_dma(ppgtt->pd); \ 59 (reg_state__)[CTX_PDP0_UDW + 1] = upper_32_bits(addr__); \ 60 (reg_state__)[CTX_PDP0_LDW + 1] = lower_32_bits(addr__); \ 61 } while (0) 62 63 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 64 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 65 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 66 #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A 67 68 #endif /* _INTEL_LRC_REG_H_ */ 69