1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <asm/tsc.h> 7 #include <linux/cpufreq.h> 8 9 #include <drm/intel/intel_pcode_regs.h> 10 11 #include "i915_drv.h" 12 #include "i915_reg.h" 13 #include "intel_gt.h" 14 #include "intel_llc.h" 15 #include "intel_mchbar_regs.h" 16 #include "intel_pcode.h" 17 #include "intel_rps.h" 18 19 struct ia_constants { 20 unsigned int min_gpu_freq; 21 unsigned int max_gpu_freq; 22 23 unsigned int min_ring_freq; 24 unsigned int max_ia_freq; 25 }; 26 27 static struct intel_gt *llc_to_gt(struct intel_llc *llc) 28 { 29 return container_of(llc, struct intel_gt, llc); 30 } 31 32 static unsigned int cpu_max_MHz(void) 33 { 34 struct cpufreq_policy *policy; 35 unsigned int max_khz; 36 37 policy = cpufreq_cpu_get(0); 38 if (policy) { 39 max_khz = policy->cpuinfo.max_freq; 40 cpufreq_cpu_put(policy); 41 } else { 42 /* 43 * Default to measured freq if none found, PCU will ensure we 44 * don't go over 45 */ 46 max_khz = tsc_khz; 47 } 48 49 return max_khz / 1000; 50 } 51 52 static bool get_ia_constants(struct intel_llc *llc, 53 struct ia_constants *consts) 54 { 55 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 56 struct intel_rps *rps = &llc_to_gt(llc)->rps; 57 58 if (!HAS_LLC(i915) || IS_DGFX(i915)) 59 return false; 60 61 consts->max_ia_freq = cpu_max_MHz(); 62 63 consts->min_ring_freq = 64 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; 65 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 66 consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3); 67 68 consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps); 69 consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps); 70 71 return true; 72 } 73 74 static void calc_ia_freq(struct intel_llc *llc, 75 unsigned int gpu_freq, 76 const struct ia_constants *consts, 77 unsigned int *out_ia_freq, 78 unsigned int *out_ring_freq) 79 { 80 struct drm_i915_private *i915 = llc_to_gt(llc)->i915; 81 const int diff = consts->max_gpu_freq - gpu_freq; 82 unsigned int ia_freq = 0, ring_freq = 0; 83 84 if (GRAPHICS_VER(i915) >= 9) { 85 /* 86 * ring_freq = 2 * GT. ring_freq is in 100MHz units 87 * No floor required for ring frequency on SKL. 88 */ 89 ring_freq = gpu_freq; 90 } else if (GRAPHICS_VER(i915) >= 8) { 91 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 92 ring_freq = max(consts->min_ring_freq, gpu_freq); 93 } else if (IS_HASWELL(i915)) { 94 ring_freq = mult_frac(gpu_freq, 5, 4); 95 ring_freq = max(consts->min_ring_freq, ring_freq); 96 /* leave ia_freq as the default, chosen by cpufreq */ 97 } else { 98 const int min_freq = 15; 99 const int scale = 180; 100 101 /* 102 * On older processors, there is no separate ring 103 * clock domain, so in order to boost the bandwidth 104 * of the ring, we need to upclock the CPU (ia_freq). 105 * 106 * For GPU frequencies less than 750MHz, 107 * just use the lowest ring freq. 108 */ 109 if (gpu_freq < min_freq) 110 ia_freq = 800; 111 else 112 ia_freq = consts->max_ia_freq - diff * scale / 2; 113 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 114 } 115 116 *out_ia_freq = ia_freq; 117 *out_ring_freq = ring_freq; 118 } 119 120 static void gen6_update_ring_freq(struct intel_llc *llc) 121 { 122 struct ia_constants consts; 123 unsigned int gpu_freq; 124 125 if (!get_ia_constants(llc, &consts)) 126 return; 127 128 /* 129 * Although this is unlikely on any platform during initialization, 130 * let's ensure we don't get accidentally into infinite loop 131 */ 132 if (consts.max_gpu_freq <= consts.min_gpu_freq) 133 return; 134 /* 135 * For each potential GPU frequency, load a ring frequency we'd like 136 * to use for memory access. We do this by specifying the IA frequency 137 * the PCU should use as a reference to determine the ring frequency. 138 */ 139 for (gpu_freq = consts.max_gpu_freq; 140 gpu_freq >= consts.min_gpu_freq; 141 gpu_freq--) { 142 unsigned int ia_freq, ring_freq; 143 144 calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq); 145 snb_pcode_write(llc_to_gt(llc)->uncore, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 146 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 147 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 148 gpu_freq); 149 } 150 } 151 152 void intel_llc_enable(struct intel_llc *llc) 153 { 154 gen6_update_ring_freq(llc); 155 } 156 157 void intel_llc_disable(struct intel_llc *llc) 158 { 159 /* Currently there is no HW configuration to be done to disable. */ 160 } 161 162 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 163 #include "selftest_llc.c" 164 #endif 165