1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/slab.h> /* fault-inject.h is not standalone! */ 7 8 #include <linux/fault-inject.h> 9 10 #include "i915_trace.h" 11 #include "intel_gt.h" 12 #include "intel_gtt.h" 13 14 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) 15 { 16 struct drm_i915_gem_object *obj; 17 18 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) 19 i915_gem_shrink_all(vm->i915); 20 21 obj = i915_gem_object_create_internal(vm->i915, sz); 22 /* ensure all dma objects have the same reservation class */ 23 if (!IS_ERR(obj)) 24 obj->base.resv = &vm->resv; 25 return obj; 26 } 27 28 int pin_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 29 { 30 int err; 31 32 i915_gem_object_lock(obj, NULL); 33 err = i915_gem_object_pin_pages(obj); 34 i915_gem_object_unlock(obj); 35 if (err) 36 return err; 37 38 i915_gem_object_make_unshrinkable(obj); 39 return 0; 40 } 41 42 int pin_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 43 { 44 int err; 45 46 err = i915_gem_object_pin_pages(obj); 47 if (err) 48 return err; 49 50 i915_gem_object_make_unshrinkable(obj); 51 return 0; 52 } 53 54 void __i915_vm_close(struct i915_address_space *vm) 55 { 56 struct i915_vma *vma, *vn; 57 58 if (!atomic_dec_and_mutex_lock(&vm->open, &vm->mutex)) 59 return; 60 61 list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) { 62 struct drm_i915_gem_object *obj = vma->obj; 63 64 /* Keep the obj (and hence the vma) alive as _we_ destroy it */ 65 if (!kref_get_unless_zero(&obj->base.refcount)) 66 continue; 67 68 atomic_and(~I915_VMA_PIN_MASK, &vma->flags); 69 WARN_ON(__i915_vma_unbind(vma)); 70 __i915_vma_put(vma); 71 72 i915_gem_object_put(obj); 73 } 74 GEM_BUG_ON(!list_empty(&vm->bound_list)); 75 76 mutex_unlock(&vm->mutex); 77 } 78 79 /* lock the vm into the current ww, if we lock one, we lock all */ 80 int i915_vm_lock_objects(struct i915_address_space *vm, 81 struct i915_gem_ww_ctx *ww) 82 { 83 if (vm->scratch[0]->base.resv == &vm->resv) { 84 return i915_gem_object_lock(vm->scratch[0], ww); 85 } else { 86 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); 87 88 /* We borrowed the scratch page from ggtt, take the top level object */ 89 return i915_gem_object_lock(ppgtt->pd->pt.base, ww); 90 } 91 } 92 93 void i915_address_space_fini(struct i915_address_space *vm) 94 { 95 drm_mm_takedown(&vm->mm); 96 mutex_destroy(&vm->mutex); 97 } 98 99 static void __i915_vm_release(struct work_struct *work) 100 { 101 struct i915_address_space *vm = 102 container_of(work, struct i915_address_space, rcu.work); 103 104 vm->cleanup(vm); 105 i915_address_space_fini(vm); 106 dma_resv_fini(&vm->resv); 107 108 kfree(vm); 109 } 110 111 void i915_vm_release(struct kref *kref) 112 { 113 struct i915_address_space *vm = 114 container_of(kref, struct i915_address_space, ref); 115 116 GEM_BUG_ON(i915_is_ggtt(vm)); 117 trace_i915_ppgtt_release(vm); 118 119 queue_rcu_work(vm->i915->wq, &vm->rcu); 120 } 121 122 void i915_address_space_init(struct i915_address_space *vm, int subclass) 123 { 124 kref_init(&vm->ref); 125 INIT_RCU_WORK(&vm->rcu, __i915_vm_release); 126 atomic_set(&vm->open, 1); 127 128 /* 129 * The vm->mutex must be reclaim safe (for use in the shrinker). 130 * Do a dummy acquire now under fs_reclaim so that any allocation 131 * attempt holding the lock is immediately reported by lockdep. 132 */ 133 mutex_init(&vm->mutex); 134 lockdep_set_subclass(&vm->mutex, subclass); 135 i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex); 136 dma_resv_init(&vm->resv); 137 138 GEM_BUG_ON(!vm->total); 139 drm_mm_init(&vm->mm, 0, vm->total); 140 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; 141 142 INIT_LIST_HEAD(&vm->bound_list); 143 } 144 145 void clear_pages(struct i915_vma *vma) 146 { 147 GEM_BUG_ON(!vma->pages); 148 149 if (vma->pages != vma->obj->mm.pages) { 150 sg_free_table(vma->pages); 151 kfree(vma->pages); 152 } 153 vma->pages = NULL; 154 155 memset(&vma->page_sizes, 0, sizeof(vma->page_sizes)); 156 } 157 158 dma_addr_t __px_dma(struct drm_i915_gem_object *p) 159 { 160 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 161 return sg_dma_address(p->mm.pages->sgl); 162 } 163 164 struct page *__px_page(struct drm_i915_gem_object *p) 165 { 166 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 167 return sg_page(p->mm.pages->sgl); 168 } 169 170 void 171 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) 172 { 173 struct page *page = __px_page(p); 174 void *vaddr; 175 176 vaddr = kmap(page); 177 memset64(vaddr, val, count); 178 clflush_cache_range(vaddr, PAGE_SIZE); 179 kunmap(page); 180 } 181 182 static void poison_scratch_page(struct drm_i915_gem_object *scratch) 183 { 184 struct sgt_iter sgt; 185 struct page *page; 186 u8 val; 187 188 val = 0; 189 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 190 val = POISON_FREE; 191 192 for_each_sgt_page(page, sgt, scratch->mm.pages) { 193 void *vaddr; 194 195 vaddr = kmap(page); 196 memset(vaddr, val, PAGE_SIZE); 197 kunmap(page); 198 } 199 } 200 201 int setup_scratch_page(struct i915_address_space *vm) 202 { 203 unsigned long size; 204 205 /* 206 * In order to utilize 64K pages for an object with a size < 2M, we will 207 * need to support a 64K scratch page, given that every 16th entry for a 208 * page-table operating in 64K mode must point to a properly aligned 64K 209 * region, including any PTEs which happen to point to scratch. 210 * 211 * This is only relevant for the 48b PPGTT where we support 212 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the 213 * scratch (read-only) between all vm, we create one 64k scratch page 214 * for all. 215 */ 216 size = I915_GTT_PAGE_SIZE_4K; 217 if (i915_vm_is_4lvl(vm) && 218 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) 219 size = I915_GTT_PAGE_SIZE_64K; 220 221 do { 222 struct drm_i915_gem_object *obj; 223 224 obj = vm->alloc_pt_dma(vm, size); 225 if (IS_ERR(obj)) 226 goto skip; 227 228 if (pin_pt_dma(vm, obj)) 229 goto skip_obj; 230 231 /* We need a single contiguous page for our scratch */ 232 if (obj->mm.page_sizes.sg < size) 233 goto skip_obj; 234 235 /* And it needs to be correspondingly aligned */ 236 if (__px_dma(obj) & (size - 1)) 237 goto skip_obj; 238 239 /* 240 * Use a non-zero scratch page for debugging. 241 * 242 * We want a value that should be reasonably obvious 243 * to spot in the error state, while also causing a GPU hang 244 * if executed. We prefer using a clear page in production, so 245 * should it ever be accidentally used, the effect should be 246 * fairly benign. 247 */ 248 poison_scratch_page(obj); 249 250 vm->scratch[0] = obj; 251 vm->scratch_order = get_order(size); 252 return 0; 253 254 skip_obj: 255 i915_gem_object_put(obj); 256 skip: 257 if (size == I915_GTT_PAGE_SIZE_4K) 258 return -ENOMEM; 259 260 size = I915_GTT_PAGE_SIZE_4K; 261 } while (1); 262 } 263 264 void free_scratch(struct i915_address_space *vm) 265 { 266 int i; 267 268 for (i = 0; i <= vm->top; i++) 269 i915_gem_object_put(vm->scratch[i]); 270 } 271 272 void gtt_write_workarounds(struct intel_gt *gt) 273 { 274 struct drm_i915_private *i915 = gt->i915; 275 struct intel_uncore *uncore = gt->uncore; 276 277 /* 278 * This function is for gtt related workarounds. This function is 279 * called on driver load and after a GPU reset, so you can place 280 * workarounds here even if they get overwritten by GPU reset. 281 */ 282 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ 283 if (IS_BROADWELL(i915)) 284 intel_uncore_write(uncore, 285 GEN8_L3_LRA_1_GPGPU, 286 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); 287 else if (IS_CHERRYVIEW(i915)) 288 intel_uncore_write(uncore, 289 GEN8_L3_LRA_1_GPGPU, 290 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); 291 else if (IS_GEN9_LP(i915)) 292 intel_uncore_write(uncore, 293 GEN8_L3_LRA_1_GPGPU, 294 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); 295 else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11) 296 intel_uncore_write(uncore, 297 GEN8_L3_LRA_1_GPGPU, 298 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); 299 300 /* 301 * To support 64K PTEs we need to first enable the use of the 302 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical 303 * mmio, otherwise the page-walker will simply ignore the IPS bit. This 304 * shouldn't be needed after GEN10. 305 * 306 * 64K pages were first introduced from BDW+, although technically they 307 * only *work* from gen9+. For pre-BDW we instead have the option for 308 * 32K pages, but we don't currently have any support for it in our 309 * driver. 310 */ 311 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) && 312 INTEL_GEN(i915) <= 10) 313 intel_uncore_rmw(uncore, 314 GEN8_GAMW_ECO_DEV_RW_IA, 315 0, 316 GAMW_ECO_ENABLE_64K_IPS_FIELD); 317 318 if (IS_GEN_RANGE(i915, 8, 11)) { 319 bool can_use_gtt_cache = true; 320 321 /* 322 * According to the BSpec if we use 2M/1G pages then we also 323 * need to disable the GTT cache. At least on BDW we can see 324 * visual corruption when using 2M pages, and not disabling the 325 * GTT cache. 326 */ 327 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M)) 328 can_use_gtt_cache = false; 329 330 /* WaGttCachingOffByDefault */ 331 intel_uncore_write(uncore, 332 HSW_GTT_CACHE_EN, 333 can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); 334 drm_WARN_ON_ONCE(&i915->drm, can_use_gtt_cache && 335 intel_uncore_read(uncore, 336 HSW_GTT_CACHE_EN) == 0); 337 } 338 } 339 340 static void tgl_setup_private_ppat(struct intel_uncore *uncore) 341 { 342 /* TGL doesn't support LLC or AGE settings */ 343 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); 344 intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC); 345 intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT); 346 intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC); 347 intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB); 348 intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB); 349 intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB); 350 intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); 351 } 352 353 static void cnl_setup_private_ppat(struct intel_uncore *uncore) 354 { 355 intel_uncore_write(uncore, 356 GEN10_PAT_INDEX(0), 357 GEN8_PPAT_WB | GEN8_PPAT_LLC); 358 intel_uncore_write(uncore, 359 GEN10_PAT_INDEX(1), 360 GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); 361 intel_uncore_write(uncore, 362 GEN10_PAT_INDEX(2), 363 GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 364 intel_uncore_write(uncore, 365 GEN10_PAT_INDEX(3), 366 GEN8_PPAT_UC); 367 intel_uncore_write(uncore, 368 GEN10_PAT_INDEX(4), 369 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); 370 intel_uncore_write(uncore, 371 GEN10_PAT_INDEX(5), 372 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); 373 intel_uncore_write(uncore, 374 GEN10_PAT_INDEX(6), 375 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); 376 intel_uncore_write(uncore, 377 GEN10_PAT_INDEX(7), 378 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 379 } 380 381 /* 382 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 383 * bits. When using advanced contexts each context stores its own PAT, but 384 * writing this data shouldn't be harmful even in those cases. 385 */ 386 static void bdw_setup_private_ppat(struct intel_uncore *uncore) 387 { 388 struct drm_i915_private *i915 = uncore->i915; 389 u64 pat; 390 391 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 392 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 393 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 394 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 395 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 396 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 397 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 398 399 /* for scanout with eLLC */ 400 if (INTEL_GEN(i915) >= 9) 401 pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 402 else 403 pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); 404 405 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 406 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 407 } 408 409 static void chv_setup_private_ppat(struct intel_uncore *uncore) 410 { 411 u64 pat; 412 413 /* 414 * Map WB on BDW to snooped on CHV. 415 * 416 * Only the snoop bit has meaning for CHV, the rest is 417 * ignored. 418 * 419 * The hardware will never snoop for certain types of accesses: 420 * - CPU GTT (GMADR->GGTT->no snoop->memory) 421 * - PPGTT page tables 422 * - some other special cycles 423 * 424 * As with BDW, we also need to consider the following for GT accesses: 425 * "For GGTT, there is NO pat_sel[2:0] from the entry, 426 * so RTL will always use the value corresponding to 427 * pat_sel = 000". 428 * Which means we must set the snoop bit in PAT entry 0 429 * in order to keep the global status page working. 430 */ 431 432 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | 433 GEN8_PPAT(1, 0) | 434 GEN8_PPAT(2, 0) | 435 GEN8_PPAT(3, 0) | 436 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 437 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 438 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 439 GEN8_PPAT(7, CHV_PPAT_SNOOP); 440 441 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 442 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 443 } 444 445 void setup_private_pat(struct intel_uncore *uncore) 446 { 447 struct drm_i915_private *i915 = uncore->i915; 448 449 GEM_BUG_ON(INTEL_GEN(i915) < 8); 450 451 if (INTEL_GEN(i915) >= 12) 452 tgl_setup_private_ppat(uncore); 453 else if (INTEL_GEN(i915) >= 10) 454 cnl_setup_private_ppat(uncore); 455 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) 456 chv_setup_private_ppat(uncore); 457 else 458 bdw_setup_private_ppat(uncore); 459 } 460 461 struct i915_vma * 462 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size) 463 { 464 struct drm_i915_gem_object *obj; 465 struct i915_vma *vma; 466 467 obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size)); 468 if (IS_ERR(obj)) 469 return ERR_CAST(obj); 470 471 i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED); 472 473 vma = i915_vma_instance(obj, vm, NULL); 474 if (IS_ERR(vma)) { 475 i915_gem_object_put(obj); 476 return vma; 477 } 478 479 return vma; 480 } 481 482 struct i915_vma * 483 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size) 484 { 485 struct i915_vma *vma; 486 int err; 487 488 vma = __vm_create_scratch_for_read(vm, size); 489 if (IS_ERR(vma)) 490 return vma; 491 492 err = i915_vma_pin(vma, 0, 0, 493 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 494 if (err) { 495 i915_vma_put(vma); 496 return ERR_PTR(err); 497 } 498 499 return vma; 500 } 501 502 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 503 #include "selftests/mock_gtt.c" 504 #endif 505