1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/slab.h> /* fault-inject.h is not standalone! */ 7 8 #include <linux/fault-inject.h> 9 10 #include "gem/i915_gem_lmem.h" 11 #include "i915_trace.h" 12 #include "intel_gt.h" 13 #include "intel_gtt.h" 14 15 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz) 16 { 17 struct drm_i915_gem_object *obj; 18 19 obj = i915_gem_object_create_lmem(vm->i915, sz, 0); 20 /* 21 * Ensure all paging structures for this vm share the same dma-resv 22 * object underneath, with the idea that one object_lock() will lock 23 * them all at once. 24 */ 25 if (!IS_ERR(obj)) 26 obj->base.resv = &vm->resv; 27 return obj; 28 } 29 30 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) 31 { 32 struct drm_i915_gem_object *obj; 33 34 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) 35 i915_gem_shrink_all(vm->i915); 36 37 obj = i915_gem_object_create_internal(vm->i915, sz); 38 /* 39 * Ensure all paging structures for this vm share the same dma-resv 40 * object underneath, with the idea that one object_lock() will lock 41 * them all at once. 42 */ 43 if (!IS_ERR(obj)) 44 obj->base.resv = &vm->resv; 45 return obj; 46 } 47 48 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 49 { 50 enum i915_map_type type; 51 void *vaddr; 52 53 type = i915_coherent_map_type(vm->i915, obj, true); 54 vaddr = i915_gem_object_pin_map_unlocked(obj, type); 55 if (IS_ERR(vaddr)) 56 return PTR_ERR(vaddr); 57 58 i915_gem_object_make_unshrinkable(obj); 59 return 0; 60 } 61 62 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 63 { 64 enum i915_map_type type; 65 void *vaddr; 66 67 type = i915_coherent_map_type(vm->i915, obj, true); 68 vaddr = i915_gem_object_pin_map(obj, type); 69 if (IS_ERR(vaddr)) 70 return PTR_ERR(vaddr); 71 72 i915_gem_object_make_unshrinkable(obj); 73 return 0; 74 } 75 76 void __i915_vm_close(struct i915_address_space *vm) 77 { 78 struct i915_vma *vma, *vn; 79 80 if (!atomic_dec_and_mutex_lock(&vm->open, &vm->mutex)) 81 return; 82 83 list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) { 84 struct drm_i915_gem_object *obj = vma->obj; 85 86 /* Keep the obj (and hence the vma) alive as _we_ destroy it */ 87 if (!kref_get_unless_zero(&obj->base.refcount)) 88 continue; 89 90 atomic_and(~I915_VMA_PIN_MASK, &vma->flags); 91 WARN_ON(__i915_vma_unbind(vma)); 92 __i915_vma_put(vma); 93 94 i915_gem_object_put(obj); 95 } 96 GEM_BUG_ON(!list_empty(&vm->bound_list)); 97 98 mutex_unlock(&vm->mutex); 99 } 100 101 /* lock the vm into the current ww, if we lock one, we lock all */ 102 int i915_vm_lock_objects(struct i915_address_space *vm, 103 struct i915_gem_ww_ctx *ww) 104 { 105 if (vm->scratch[0]->base.resv == &vm->resv) { 106 return i915_gem_object_lock(vm->scratch[0], ww); 107 } else { 108 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); 109 110 /* We borrowed the scratch page from ggtt, take the top level object */ 111 return i915_gem_object_lock(ppgtt->pd->pt.base, ww); 112 } 113 } 114 115 void i915_address_space_fini(struct i915_address_space *vm) 116 { 117 drm_mm_takedown(&vm->mm); 118 mutex_destroy(&vm->mutex); 119 } 120 121 static void __i915_vm_release(struct work_struct *work) 122 { 123 struct i915_address_space *vm = 124 container_of(work, struct i915_address_space, rcu.work); 125 126 vm->cleanup(vm); 127 i915_address_space_fini(vm); 128 dma_resv_fini(&vm->resv); 129 130 kfree(vm); 131 } 132 133 void i915_vm_release(struct kref *kref) 134 { 135 struct i915_address_space *vm = 136 container_of(kref, struct i915_address_space, ref); 137 138 GEM_BUG_ON(i915_is_ggtt(vm)); 139 trace_i915_ppgtt_release(vm); 140 141 queue_rcu_work(vm->i915->wq, &vm->rcu); 142 } 143 144 void i915_address_space_init(struct i915_address_space *vm, int subclass) 145 { 146 kref_init(&vm->ref); 147 INIT_RCU_WORK(&vm->rcu, __i915_vm_release); 148 atomic_set(&vm->open, 1); 149 150 /* 151 * The vm->mutex must be reclaim safe (for use in the shrinker). 152 * Do a dummy acquire now under fs_reclaim so that any allocation 153 * attempt holding the lock is immediately reported by lockdep. 154 */ 155 mutex_init(&vm->mutex); 156 lockdep_set_subclass(&vm->mutex, subclass); 157 158 if (!intel_vm_no_concurrent_access_wa(vm->i915)) { 159 i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex); 160 } else { 161 /* 162 * CHV + BXT VTD workaround use stop_machine(), 163 * which is allowed to allocate memory. This means &vm->mutex 164 * is the outer lock, and in theory we can allocate memory inside 165 * it through stop_machine(). 166 * 167 * Add the annotation for this, we use trylock in shrinker. 168 */ 169 mutex_acquire(&vm->mutex.dep_map, 0, 0, _THIS_IP_); 170 might_alloc(GFP_KERNEL); 171 mutex_release(&vm->mutex.dep_map, _THIS_IP_); 172 } 173 dma_resv_init(&vm->resv); 174 175 GEM_BUG_ON(!vm->total); 176 drm_mm_init(&vm->mm, 0, vm->total); 177 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; 178 179 INIT_LIST_HEAD(&vm->bound_list); 180 } 181 182 void clear_pages(struct i915_vma *vma) 183 { 184 GEM_BUG_ON(!vma->pages); 185 186 if (vma->pages != vma->obj->mm.pages) { 187 sg_free_table(vma->pages); 188 kfree(vma->pages); 189 } 190 vma->pages = NULL; 191 192 memset(&vma->page_sizes, 0, sizeof(vma->page_sizes)); 193 } 194 195 void *__px_vaddr(struct drm_i915_gem_object *p) 196 { 197 enum i915_map_type type; 198 199 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 200 return page_unpack_bits(p->mm.mapping, &type); 201 } 202 203 dma_addr_t __px_dma(struct drm_i915_gem_object *p) 204 { 205 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 206 return sg_dma_address(p->mm.pages->sgl); 207 } 208 209 struct page *__px_page(struct drm_i915_gem_object *p) 210 { 211 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 212 return sg_page(p->mm.pages->sgl); 213 } 214 215 void 216 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) 217 { 218 void *vaddr = __px_vaddr(p); 219 220 memset64(vaddr, val, count); 221 clflush_cache_range(vaddr, PAGE_SIZE); 222 } 223 224 static void poison_scratch_page(struct drm_i915_gem_object *scratch) 225 { 226 void *vaddr = __px_vaddr(scratch); 227 u8 val; 228 229 val = 0; 230 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 231 val = POISON_FREE; 232 233 memset(vaddr, val, scratch->base.size); 234 } 235 236 int setup_scratch_page(struct i915_address_space *vm) 237 { 238 unsigned long size; 239 240 /* 241 * In order to utilize 64K pages for an object with a size < 2M, we will 242 * need to support a 64K scratch page, given that every 16th entry for a 243 * page-table operating in 64K mode must point to a properly aligned 64K 244 * region, including any PTEs which happen to point to scratch. 245 * 246 * This is only relevant for the 48b PPGTT where we support 247 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the 248 * scratch (read-only) between all vm, we create one 64k scratch page 249 * for all. 250 */ 251 size = I915_GTT_PAGE_SIZE_4K; 252 if (i915_vm_is_4lvl(vm) && 253 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) 254 size = I915_GTT_PAGE_SIZE_64K; 255 256 do { 257 struct drm_i915_gem_object *obj; 258 259 obj = vm->alloc_pt_dma(vm, size); 260 if (IS_ERR(obj)) 261 goto skip; 262 263 if (map_pt_dma(vm, obj)) 264 goto skip_obj; 265 266 /* We need a single contiguous page for our scratch */ 267 if (obj->mm.page_sizes.sg < size) 268 goto skip_obj; 269 270 /* And it needs to be correspondingly aligned */ 271 if (__px_dma(obj) & (size - 1)) 272 goto skip_obj; 273 274 /* 275 * Use a non-zero scratch page for debugging. 276 * 277 * We want a value that should be reasonably obvious 278 * to spot in the error state, while also causing a GPU hang 279 * if executed. We prefer using a clear page in production, so 280 * should it ever be accidentally used, the effect should be 281 * fairly benign. 282 */ 283 poison_scratch_page(obj); 284 285 vm->scratch[0] = obj; 286 vm->scratch_order = get_order(size); 287 return 0; 288 289 skip_obj: 290 i915_gem_object_put(obj); 291 skip: 292 if (size == I915_GTT_PAGE_SIZE_4K) 293 return -ENOMEM; 294 295 size = I915_GTT_PAGE_SIZE_4K; 296 } while (1); 297 } 298 299 void free_scratch(struct i915_address_space *vm) 300 { 301 int i; 302 303 for (i = 0; i <= vm->top; i++) 304 i915_gem_object_put(vm->scratch[i]); 305 } 306 307 void gtt_write_workarounds(struct intel_gt *gt) 308 { 309 struct drm_i915_private *i915 = gt->i915; 310 struct intel_uncore *uncore = gt->uncore; 311 312 /* 313 * This function is for gtt related workarounds. This function is 314 * called on driver load and after a GPU reset, so you can place 315 * workarounds here even if they get overwritten by GPU reset. 316 */ 317 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ 318 if (IS_BROADWELL(i915)) 319 intel_uncore_write(uncore, 320 GEN8_L3_LRA_1_GPGPU, 321 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); 322 else if (IS_CHERRYVIEW(i915)) 323 intel_uncore_write(uncore, 324 GEN8_L3_LRA_1_GPGPU, 325 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); 326 else if (IS_GEN9_LP(i915)) 327 intel_uncore_write(uncore, 328 GEN8_L3_LRA_1_GPGPU, 329 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); 330 else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11) 331 intel_uncore_write(uncore, 332 GEN8_L3_LRA_1_GPGPU, 333 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); 334 335 /* 336 * To support 64K PTEs we need to first enable the use of the 337 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical 338 * mmio, otherwise the page-walker will simply ignore the IPS bit. This 339 * shouldn't be needed after GEN10. 340 * 341 * 64K pages were first introduced from BDW+, although technically they 342 * only *work* from gen9+. For pre-BDW we instead have the option for 343 * 32K pages, but we don't currently have any support for it in our 344 * driver. 345 */ 346 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) && 347 INTEL_GEN(i915) <= 10) 348 intel_uncore_rmw(uncore, 349 GEN8_GAMW_ECO_DEV_RW_IA, 350 0, 351 GAMW_ECO_ENABLE_64K_IPS_FIELD); 352 353 if (IS_GEN_RANGE(i915, 8, 11)) { 354 bool can_use_gtt_cache = true; 355 356 /* 357 * According to the BSpec if we use 2M/1G pages then we also 358 * need to disable the GTT cache. At least on BDW we can see 359 * visual corruption when using 2M pages, and not disabling the 360 * GTT cache. 361 */ 362 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M)) 363 can_use_gtt_cache = false; 364 365 /* WaGttCachingOffByDefault */ 366 intel_uncore_write(uncore, 367 HSW_GTT_CACHE_EN, 368 can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); 369 drm_WARN_ON_ONCE(&i915->drm, can_use_gtt_cache && 370 intel_uncore_read(uncore, 371 HSW_GTT_CACHE_EN) == 0); 372 } 373 } 374 375 static void tgl_setup_private_ppat(struct intel_uncore *uncore) 376 { 377 /* TGL doesn't support LLC or AGE settings */ 378 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); 379 intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC); 380 intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT); 381 intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC); 382 intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB); 383 intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB); 384 intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB); 385 intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); 386 } 387 388 static void cnl_setup_private_ppat(struct intel_uncore *uncore) 389 { 390 intel_uncore_write(uncore, 391 GEN10_PAT_INDEX(0), 392 GEN8_PPAT_WB | GEN8_PPAT_LLC); 393 intel_uncore_write(uncore, 394 GEN10_PAT_INDEX(1), 395 GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); 396 intel_uncore_write(uncore, 397 GEN10_PAT_INDEX(2), 398 GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 399 intel_uncore_write(uncore, 400 GEN10_PAT_INDEX(3), 401 GEN8_PPAT_UC); 402 intel_uncore_write(uncore, 403 GEN10_PAT_INDEX(4), 404 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); 405 intel_uncore_write(uncore, 406 GEN10_PAT_INDEX(5), 407 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); 408 intel_uncore_write(uncore, 409 GEN10_PAT_INDEX(6), 410 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); 411 intel_uncore_write(uncore, 412 GEN10_PAT_INDEX(7), 413 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 414 } 415 416 /* 417 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 418 * bits. When using advanced contexts each context stores its own PAT, but 419 * writing this data shouldn't be harmful even in those cases. 420 */ 421 static void bdw_setup_private_ppat(struct intel_uncore *uncore) 422 { 423 struct drm_i915_private *i915 = uncore->i915; 424 u64 pat; 425 426 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 427 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 428 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 429 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 430 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 431 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 432 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 433 434 /* for scanout with eLLC */ 435 if (INTEL_GEN(i915) >= 9) 436 pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 437 else 438 pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); 439 440 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 441 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 442 } 443 444 static void chv_setup_private_ppat(struct intel_uncore *uncore) 445 { 446 u64 pat; 447 448 /* 449 * Map WB on BDW to snooped on CHV. 450 * 451 * Only the snoop bit has meaning for CHV, the rest is 452 * ignored. 453 * 454 * The hardware will never snoop for certain types of accesses: 455 * - CPU GTT (GMADR->GGTT->no snoop->memory) 456 * - PPGTT page tables 457 * - some other special cycles 458 * 459 * As with BDW, we also need to consider the following for GT accesses: 460 * "For GGTT, there is NO pat_sel[2:0] from the entry, 461 * so RTL will always use the value corresponding to 462 * pat_sel = 000". 463 * Which means we must set the snoop bit in PAT entry 0 464 * in order to keep the global status page working. 465 */ 466 467 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | 468 GEN8_PPAT(1, 0) | 469 GEN8_PPAT(2, 0) | 470 GEN8_PPAT(3, 0) | 471 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 472 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 473 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 474 GEN8_PPAT(7, CHV_PPAT_SNOOP); 475 476 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 477 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 478 } 479 480 void setup_private_pat(struct intel_uncore *uncore) 481 { 482 struct drm_i915_private *i915 = uncore->i915; 483 484 GEM_BUG_ON(INTEL_GEN(i915) < 8); 485 486 if (INTEL_GEN(i915) >= 12) 487 tgl_setup_private_ppat(uncore); 488 else if (INTEL_GEN(i915) >= 10) 489 cnl_setup_private_ppat(uncore); 490 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) 491 chv_setup_private_ppat(uncore); 492 else 493 bdw_setup_private_ppat(uncore); 494 } 495 496 struct i915_vma * 497 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size) 498 { 499 struct drm_i915_gem_object *obj; 500 struct i915_vma *vma; 501 502 obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size)); 503 if (IS_ERR(obj)) 504 return ERR_CAST(obj); 505 506 i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED); 507 508 vma = i915_vma_instance(obj, vm, NULL); 509 if (IS_ERR(vma)) { 510 i915_gem_object_put(obj); 511 return vma; 512 } 513 514 return vma; 515 } 516 517 struct i915_vma * 518 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size) 519 { 520 struct i915_vma *vma; 521 int err; 522 523 vma = __vm_create_scratch_for_read(vm, size); 524 if (IS_ERR(vma)) 525 return vma; 526 527 err = i915_vma_pin(vma, 0, 0, 528 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 529 if (err) { 530 i915_vma_put(vma); 531 return ERR_PTR(err); 532 } 533 534 return vma; 535 } 536 537 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 538 #include "selftests/mock_gtt.c" 539 #endif 540