xref: /linux/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c (revision 172cdcaefea5c297fdb3d20b7d5aff60ae4fbce6) 
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_gt.h"
9 #include "intel_gt_irq.h"
10 #include "intel_gt_pm_irq.h"
11 
12 static void write_pm_imr(struct intel_gt *gt)
13 {
14 	struct drm_i915_private *i915 = gt->i915;
15 	struct intel_uncore *uncore = gt->uncore;
16 	u32 mask = gt->pm_imr;
17 	i915_reg_t reg;
18 
19 	if (INTEL_GEN(i915) >= 11) {
20 		reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
21 		mask <<= 16; /* pm is in upper half */
22 	} else if (INTEL_GEN(i915) >= 8) {
23 		reg = GEN8_GT_IMR(2);
24 	} else {
25 		reg = GEN6_PMIMR;
26 	}
27 
28 	intel_uncore_write(uncore, reg, mask);
29 }
30 
31 static void gen6_gt_pm_update_irq(struct intel_gt *gt,
32 				  u32 interrupt_mask,
33 				  u32 enabled_irq_mask)
34 {
35 	u32 new_val;
36 
37 	WARN_ON(enabled_irq_mask & ~interrupt_mask);
38 
39 	lockdep_assert_held(&gt->irq_lock);
40 
41 	new_val = gt->pm_imr;
42 	new_val &= ~interrupt_mask;
43 	new_val |= ~enabled_irq_mask & interrupt_mask;
44 
45 	if (new_val != gt->pm_imr) {
46 		gt->pm_imr = new_val;
47 		write_pm_imr(gt);
48 	}
49 }
50 
51 void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask)
52 {
53 	gen6_gt_pm_update_irq(gt, mask, mask);
54 }
55 
56 void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
57 {
58 	gen6_gt_pm_update_irq(gt, mask, 0);
59 }
60 
61 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
62 {
63 	struct intel_uncore *uncore = gt->uncore;
64 	i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
65 
66 	lockdep_assert_held(&gt->irq_lock);
67 
68 	intel_uncore_write(uncore, reg, reset_mask);
69 	intel_uncore_write(uncore, reg, reset_mask);
70 	intel_uncore_posting_read(uncore, reg);
71 }
72 
73 static void write_pm_ier(struct intel_gt *gt)
74 {
75 	struct drm_i915_private *i915 = gt->i915;
76 	struct intel_uncore *uncore = gt->uncore;
77 	u32 mask = gt->pm_ier;
78 	i915_reg_t reg;
79 
80 	if (INTEL_GEN(i915) >= 11) {
81 		reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
82 		mask <<= 16; /* pm is in upper half */
83 	} else if (INTEL_GEN(i915) >= 8) {
84 		reg = GEN8_GT_IER(2);
85 	} else {
86 		reg = GEN6_PMIER;
87 	}
88 
89 	intel_uncore_write(uncore, reg, mask);
90 }
91 
92 void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
93 {
94 	lockdep_assert_held(&gt->irq_lock);
95 
96 	gt->pm_ier |= enable_mask;
97 	write_pm_ier(gt);
98 	gen6_gt_pm_unmask_irq(gt, enable_mask);
99 }
100 
101 void gen6_gt_pm_disable_irq(struct intel_gt *gt, u32 disable_mask)
102 {
103 	lockdep_assert_held(&gt->irq_lock);
104 
105 	gt->pm_ier &= ~disable_mask;
106 	gen6_gt_pm_mask_irq(gt, disable_mask);
107 	write_pm_ier(gt);
108 }
109