1 // SPDX-License-Identifier: MIT 2 3 /* 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include <linux/seq_file.h> 8 #include <linux/string_helpers.h> 9 10 #include <drm/drm_print.h> 11 #include <drm/intel/intel_pcode_regs.h> 12 13 #include "i915_drv.h" 14 #include "i915_reg.h" 15 #include "intel_gt.h" 16 #include "intel_gt_clock_utils.h" 17 #include "intel_gt_debugfs.h" 18 #include "intel_gt_pm.h" 19 #include "intel_gt_pm_debugfs.h" 20 #include "intel_gt_regs.h" 21 #include "intel_llc.h" 22 #include "intel_mchbar_regs.h" 23 #include "intel_pcode.h" 24 #include "intel_rc6.h" 25 #include "intel_rps.h" 26 #include "intel_runtime_pm.h" 27 #include "intel_uncore.h" 28 #include "vlv_iosf_sb.h" 29 30 void intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt) 31 { 32 atomic_inc(>->user_wakeref); 33 intel_gt_pm_get_untracked(gt); 34 if (GRAPHICS_VER(gt->i915) >= 6) 35 intel_uncore_forcewake_user_get(gt->uncore); 36 } 37 38 void intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt) 39 { 40 if (GRAPHICS_VER(gt->i915) >= 6) 41 intel_uncore_forcewake_user_put(gt->uncore); 42 intel_gt_pm_put_untracked(gt); 43 atomic_dec(>->user_wakeref); 44 } 45 46 static int forcewake_user_open(struct inode *inode, struct file *file) 47 { 48 struct intel_gt *gt = inode->i_private; 49 50 intel_gt_pm_debugfs_forcewake_user_open(gt); 51 52 return 0; 53 } 54 55 static int forcewake_user_release(struct inode *inode, struct file *file) 56 { 57 struct intel_gt *gt = inode->i_private; 58 59 intel_gt_pm_debugfs_forcewake_user_release(gt); 60 61 return 0; 62 } 63 64 static const struct file_operations forcewake_user_fops = { 65 .owner = THIS_MODULE, 66 .open = forcewake_user_open, 67 .release = forcewake_user_release, 68 }; 69 70 static int fw_domains_show(struct seq_file *m, void *data) 71 { 72 struct intel_gt *gt = m->private; 73 struct intel_uncore *uncore = gt->uncore; 74 struct intel_uncore_forcewake_domain *fw_domain; 75 unsigned int tmp; 76 77 spin_lock_irq(&uncore->lock); 78 79 seq_printf(m, "user.bypass_count = %u\n", 80 uncore->user_forcewake_count); 81 82 for_each_fw_domain(fw_domain, uncore, tmp) 83 seq_printf(m, "%s.wake_count = %u\n", 84 intel_uncore_forcewake_domain_to_str(fw_domain->id), 85 READ_ONCE(fw_domain->wake_count)); 86 87 spin_unlock_irq(&uncore->lock); 88 89 return 0; 90 } 91 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains); 92 93 static int vlv_drpc(struct seq_file *m) 94 { 95 struct intel_gt *gt = m->private; 96 struct intel_uncore *uncore = gt->uncore; 97 u32 rcctl1, pw_status, mt_fwake_req; 98 99 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 100 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); 101 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 102 103 seq_printf(m, "RC6 Enabled: %s\n", 104 str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE | 105 GEN6_RC_CTL_EI_MODE(1)))); 106 seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req); 107 seq_printf(m, "Render Power Well: %s\n", 108 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 109 seq_printf(m, "Media Power Well: %s\n", 110 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 111 112 intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6); 113 intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA); 114 115 return fw_domains_show(m, NULL); 116 } 117 118 static int gen6_drpc(struct seq_file *m) 119 { 120 struct intel_gt *gt = m->private; 121 struct drm_i915_private *i915 = gt->i915; 122 struct intel_uncore *uncore = gt->uncore; 123 u32 gt_core_status, mt_fwake_req, rcctl1, rc6vids = 0; 124 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; 125 126 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 127 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); 128 129 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 130 if (GRAPHICS_VER(i915) >= 9) { 131 gen9_powergate_enable = 132 intel_uncore_read(uncore, GEN9_PG_ENABLE); 133 gen9_powergate_status = 134 intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS); 135 } 136 137 if (GRAPHICS_VER(i915) <= 7) 138 snb_pcode_read(gt->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); 139 140 seq_printf(m, "RC1e Enabled: %s\n", 141 str_yes_no(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 142 seq_printf(m, "RC6 Enabled: %s\n", 143 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 144 if (GRAPHICS_VER(i915) >= 9) { 145 seq_printf(m, "Render Well Gating Enabled: %s\n", 146 str_yes_no(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); 147 seq_printf(m, "Media Well Gating Enabled: %s\n", 148 str_yes_no(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 149 } 150 seq_printf(m, "Deep RC6 Enabled: %s\n", 151 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 152 seq_printf(m, "Deepest RC6 Enabled: %s\n", 153 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 154 seq_puts(m, "Current RC state: "); 155 switch (gt_core_status & GEN6_RCn_MASK) { 156 case GEN6_RC0: 157 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 158 seq_puts(m, "Core Power Down\n"); 159 else 160 seq_puts(m, "on\n"); 161 break; 162 case GEN6_RC3: 163 seq_puts(m, "RC3\n"); 164 break; 165 case GEN6_RC6: 166 seq_puts(m, "RC6\n"); 167 break; 168 case GEN6_RC7: 169 seq_puts(m, "RC7\n"); 170 break; 171 default: 172 seq_puts(m, "Unknown\n"); 173 break; 174 } 175 176 seq_printf(m, "Core Power Down: %s\n", 177 str_yes_no(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 178 seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req); 179 if (GRAPHICS_VER(i915) >= 9) { 180 seq_printf(m, "Render Power Well: %s\n", 181 (gen9_powergate_status & 182 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 183 seq_printf(m, "Media Power Well: %s\n", 184 (gen9_powergate_status & 185 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 186 } 187 188 /* Not exactly sure what this is */ 189 intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:", 190 INTEL_RC6_RES_RC6_LOCKED); 191 intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); 192 intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p); 193 intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp); 194 195 if (GRAPHICS_VER(i915) <= 7) { 196 seq_printf(m, "RC6 voltage: %dmV\n", 197 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 198 seq_printf(m, "RC6+ voltage: %dmV\n", 199 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 200 seq_printf(m, "RC6++ voltage: %dmV\n", 201 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 202 } 203 204 return fw_domains_show(m, NULL); 205 } 206 207 static int ilk_drpc(struct seq_file *m) 208 { 209 struct intel_gt *gt = m->private; 210 struct intel_uncore *uncore = gt->uncore; 211 u32 rgvmodectl, rstdbyctl; 212 u16 crstandvid; 213 214 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 215 rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL); 216 crstandvid = intel_uncore_read16(uncore, CRSTANDVID); 217 218 seq_printf(m, "HD boost: %s\n", 219 str_yes_no(rgvmodectl & MEMMODE_BOOST_EN)); 220 seq_printf(m, "Boost freq: %d\n", 221 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 222 MEMMODE_BOOST_FREQ_SHIFT); 223 seq_printf(m, "HW control enabled: %s\n", 224 str_yes_no(rgvmodectl & MEMMODE_HWIDLE_EN)); 225 seq_printf(m, "SW control enabled: %s\n", 226 str_yes_no(rgvmodectl & MEMMODE_SWMODE_EN)); 227 seq_printf(m, "Gated voltage change: %s\n", 228 str_yes_no(rgvmodectl & MEMMODE_RCLK_GATE)); 229 seq_printf(m, "Starting frequency: P%d\n", 230 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 231 seq_printf(m, "Max P-state: P%d\n", 232 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 233 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 234 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 235 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 236 seq_printf(m, "Render standby enabled: %s\n", 237 str_yes_no(!(rstdbyctl & RCX_SW_EXIT))); 238 seq_puts(m, "Current RS state: "); 239 switch (rstdbyctl & RSX_STATUS_MASK) { 240 case RSX_STATUS_ON: 241 seq_puts(m, "on\n"); 242 break; 243 case RSX_STATUS_RC1: 244 seq_puts(m, "RC1\n"); 245 break; 246 case RSX_STATUS_RC1E: 247 seq_puts(m, "RC1E\n"); 248 break; 249 case RSX_STATUS_RS1: 250 seq_puts(m, "RS1\n"); 251 break; 252 case RSX_STATUS_RS2: 253 seq_puts(m, "RS2 (RC6)\n"); 254 break; 255 case RSX_STATUS_RS3: 256 seq_puts(m, "RC3 (RC6+)\n"); 257 break; 258 default: 259 seq_puts(m, "unknown\n"); 260 break; 261 } 262 263 return 0; 264 } 265 266 static int mtl_drpc(struct seq_file *m) 267 { 268 struct intel_gt *gt = m->private; 269 struct intel_uncore *uncore = gt->uncore; 270 u32 gt_core_status, rcctl1, mt_fwake_req; 271 u32 mtl_powergate_enable = 0, mtl_powergate_status = 0; 272 273 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 274 gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); 275 276 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 277 mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); 278 mtl_powergate_status = intel_uncore_read(uncore, 279 GEN9_PWRGT_DOMAIN_STATUS); 280 281 seq_printf(m, "RC6 Enabled: %s\n", 282 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 283 if (gt->type == GT_MEDIA) { 284 seq_printf(m, "Media Well Gating Enabled: %s\n", 285 str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 286 } else { 287 seq_printf(m, "Render Well Gating Enabled: %s\n", 288 str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE)); 289 } 290 291 seq_puts(m, "Current RC state: "); 292 switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) { 293 case MTL_CC0: 294 seq_puts(m, "RC0\n"); 295 break; 296 case MTL_CC6: 297 seq_puts(m, "RC6\n"); 298 break; 299 default: 300 seq_puts(m, "Unknown\n"); 301 break; 302 } 303 304 seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req); 305 if (gt->type == GT_MEDIA) 306 seq_printf(m, "Media Power Well: %s\n", 307 (mtl_powergate_status & 308 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 309 else 310 seq_printf(m, "Render Power Well: %s\n", 311 (mtl_powergate_status & 312 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 313 314 /* Works for both render and media gt's */ 315 intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); 316 317 return fw_domains_show(m, NULL); 318 } 319 320 static int drpc_show(struct seq_file *m, void *unused) 321 { 322 struct intel_gt *gt = m->private; 323 struct drm_i915_private *i915 = gt->i915; 324 intel_wakeref_t wakeref; 325 int err = -ENODEV; 326 327 with_intel_runtime_pm(gt->uncore->rpm, wakeref) { 328 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 329 err = mtl_drpc(m); 330 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 331 err = vlv_drpc(m); 332 else if (GRAPHICS_VER(i915) >= 6) 333 err = gen6_drpc(m); 334 else 335 err = ilk_drpc(m); 336 } 337 338 return err; 339 } 340 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc); 341 342 void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) 343 { 344 struct drm_i915_private *i915 = gt->i915; 345 struct intel_uncore *uncore = gt->uncore; 346 struct intel_rps *rps = >->rps; 347 intel_wakeref_t wakeref; 348 349 wakeref = intel_runtime_pm_get(uncore->rpm); 350 351 if (GRAPHICS_VER(i915) == 5) { 352 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 353 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); 354 355 drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 356 drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f); 357 drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 358 MEMSTAT_VID_SHIFT); 359 drm_printf(p, "Current P-state: %d\n", 360 REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat)); 361 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 362 u32 rpmodectl, freq_sts; 363 364 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 365 drm_printf(p, "Video Turbo Mode: %s\n", 366 str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO)); 367 drm_printf(p, "HW control enabled: %s\n", 368 str_yes_no(rpmodectl & GEN6_RP_ENABLE)); 369 drm_printf(p, "SW control enabled: %s\n", 370 str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); 371 372 vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); 373 freq_sts = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); 374 vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); 375 376 drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 377 378 drm_printf(p, "actual GPU freq: %d MHz\n", 379 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); 380 381 drm_printf(p, "current GPU freq: %d MHz\n", 382 intel_gpu_freq(rps, rps->cur_freq)); 383 384 drm_printf(p, "max GPU freq: %d MHz\n", 385 intel_gpu_freq(rps, rps->max_freq)); 386 387 drm_printf(p, "min GPU freq: %d MHz\n", 388 intel_gpu_freq(rps, rps->min_freq)); 389 390 drm_printf(p, "idle GPU freq: %d MHz\n", 391 intel_gpu_freq(rps, rps->idle_freq)); 392 393 drm_printf(p, "efficient (RPe) frequency: %d MHz\n", 394 intel_gpu_freq(rps, rps->efficient_freq)); 395 } else if (GRAPHICS_VER(i915) >= 6) { 396 gen6_rps_frequency_dump(rps, p); 397 } else { 398 drm_puts(p, "no P-state info available\n"); 399 } 400 401 intel_runtime_pm_put(uncore->rpm, wakeref); 402 } 403 404 static int frequency_show(struct seq_file *m, void *unused) 405 { 406 struct intel_gt *gt = m->private; 407 struct drm_printer p = drm_seq_file_printer(m); 408 409 intel_gt_pm_frequency_dump(gt, &p); 410 411 return 0; 412 } 413 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency); 414 415 static int llc_show(struct seq_file *m, void *data) 416 { 417 struct intel_gt *gt = m->private; 418 struct drm_i915_private *i915 = gt->i915; 419 const bool edram = GRAPHICS_VER(i915) > 8; 420 struct intel_rps *rps = >->rps; 421 unsigned int max_gpu_freq, min_gpu_freq; 422 intel_wakeref_t wakeref; 423 int gpu_freq, ia_freq; 424 425 seq_printf(m, "LLC: %s\n", str_yes_no(HAS_LLC(i915))); 426 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC", 427 i915->edram_size_mb); 428 429 min_gpu_freq = rps->min_freq; 430 max_gpu_freq = rps->max_freq; 431 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 432 /* Convert GT frequency to 50 HZ units */ 433 min_gpu_freq /= GEN9_FREQ_SCALER; 434 max_gpu_freq /= GEN9_FREQ_SCALER; 435 } 436 437 seq_puts(m, "GPU freq (MHz)\tEffective GPU freq (MHz)\tEffective Ring freq (MHz)\n"); 438 439 wakeref = intel_runtime_pm_get(gt->uncore->rpm); 440 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 441 ia_freq = gpu_freq; 442 snb_pcode_read(gt->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE, 443 &ia_freq, NULL); 444 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 445 intel_gpu_freq(rps, 446 (gpu_freq * 447 (IS_GEN9_BC(i915) || 448 GRAPHICS_VER(i915) >= 11 ? 449 GEN9_FREQ_SCALER : 1))), 450 ((ia_freq >> 0) & 0xff) * 100, 451 ((ia_freq >> 8) & 0xff) * 100); 452 } 453 intel_runtime_pm_put(gt->uncore->rpm, wakeref); 454 455 return 0; 456 } 457 458 static bool llc_eval(void *data) 459 { 460 struct intel_gt *gt = data; 461 462 return HAS_LLC(gt->i915); 463 } 464 465 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc); 466 467 static const char *rps_power_to_str(unsigned int power) 468 { 469 static const char * const strings[] = { 470 [LOW_POWER] = "low power", 471 [BETWEEN] = "mixed", 472 [HIGH_POWER] = "high power", 473 }; 474 475 if (power >= ARRAY_SIZE(strings) || !strings[power]) 476 return "unknown"; 477 478 return strings[power]; 479 } 480 481 static int rps_boost_show(struct seq_file *m, void *data) 482 { 483 struct intel_gt *gt = m->private; 484 struct drm_i915_private *i915 = gt->i915; 485 struct intel_rps *rps = >->rps; 486 487 seq_printf(m, "RPS enabled? %s\n", 488 str_yes_no(intel_rps_is_enabled(rps))); 489 seq_printf(m, "RPS active? %s\n", 490 str_yes_no(intel_rps_is_active(rps))); 491 seq_printf(m, "GPU busy? %s, %llums\n", 492 str_yes_no(gt->awake), 493 ktime_to_ms(intel_gt_get_awake_time(gt))); 494 seq_printf(m, "Boosts outstanding? %d\n", 495 atomic_read(&rps->num_waiters)); 496 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 497 seq_printf(m, "Frequency requested %d, actual %d\n", 498 intel_gpu_freq(rps, rps->cur_freq), 499 intel_rps_read_actual_frequency(rps)); 500 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 501 intel_gpu_freq(rps, rps->min_freq), 502 intel_gpu_freq(rps, rps->min_freq_softlimit), 503 intel_gpu_freq(rps, rps->max_freq_softlimit), 504 intel_gpu_freq(rps, rps->max_freq)); 505 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 506 intel_gpu_freq(rps, rps->idle_freq), 507 intel_gpu_freq(rps, rps->efficient_freq), 508 intel_gpu_freq(rps, rps->boost_freq)); 509 510 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 511 512 if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) { 513 struct intel_uncore *uncore = gt->uncore; 514 u32 rpup, rpupei; 515 u32 rpdown, rpdownei; 516 517 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 518 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; 519 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; 520 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; 521 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; 522 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 523 524 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", 525 rps_power_to_str(rps->power.mode)); 526 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", 527 rpup && rpupei ? 100 * rpup / rpupei : 0, 528 rps->power.up_threshold); 529 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", 530 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, 531 rps->power.down_threshold); 532 } else { 533 seq_puts(m, "\nRPS Autotuning inactive\n"); 534 } 535 536 return 0; 537 } 538 539 static bool rps_eval(void *data) 540 { 541 struct intel_gt *gt = data; 542 543 if (intel_guc_slpc_is_used(gt_to_guc(gt))) 544 return false; 545 else 546 return HAS_RPS(gt->i915); 547 } 548 549 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost); 550 551 static int perf_limit_reasons_get(void *data, u64 *val) 552 { 553 struct intel_gt *gt = data; 554 intel_wakeref_t wakeref; 555 556 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 557 *val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt)); 558 559 return 0; 560 } 561 562 static int perf_limit_reasons_clear(void *data, u64 val) 563 { 564 struct intel_gt *gt = data; 565 intel_wakeref_t wakeref; 566 567 /* 568 * Clear the upper 16 "log" bits, the lower 16 "status" bits are 569 * read-only. The upper 16 "log" bits are identical to the lower 16 570 * "status" bits except that the "log" bits remain set until cleared. 571 */ 572 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 573 intel_uncore_rmw(gt->uncore, intel_gt_perf_limit_reasons_reg(gt), 574 GT0_PERF_LIMIT_REASONS_LOG_MASK, 0); 575 576 return 0; 577 } 578 579 static bool perf_limit_reasons_eval(void *data) 580 { 581 struct intel_gt *gt = data; 582 583 return i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt)); 584 } 585 586 DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get, 587 perf_limit_reasons_clear, "0x%llx\n"); 588 589 void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) 590 { 591 static const struct intel_gt_debugfs_file files[] = { 592 { .name = "drpc", .fops = &drpc_fops }, 593 { .name = "frequency", .fops = &frequency_fops }, 594 { .name = "forcewake", .fops = &fw_domains_fops }, 595 { .name = "forcewake_user", .fops = &forcewake_user_fops}, 596 { .name = "llc", .fops = &llc_fops, .eval = llc_eval }, 597 { .name = "rps_boost", .fops = &rps_boost_fops, .eval = rps_eval }, 598 { .name = "perf_limit_reasons", .fops = &perf_limit_reasons_fops, 599 .eval = perf_limit_reasons_eval }, 600 }; 601 602 intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); 603 } 604