1 // SPDX-License-Identifier: MIT 2 3 /* 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #include <linux/seq_file.h> 8 #include <linux/string_helpers.h> 9 10 #include "i915_drv.h" 11 #include "i915_reg.h" 12 #include "intel_gt.h" 13 #include "intel_gt_clock_utils.h" 14 #include "intel_gt_debugfs.h" 15 #include "intel_gt_pm.h" 16 #include "intel_gt_pm_debugfs.h" 17 #include "intel_gt_regs.h" 18 #include "intel_llc.h" 19 #include "intel_mchbar_regs.h" 20 #include "intel_pcode.h" 21 #include "intel_rc6.h" 22 #include "intel_rps.h" 23 #include "intel_runtime_pm.h" 24 #include "intel_uncore.h" 25 #include "vlv_sideband.h" 26 27 void intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt) 28 { 29 atomic_inc(>->user_wakeref); 30 intel_gt_pm_get(gt); 31 if (GRAPHICS_VER(gt->i915) >= 6) 32 intel_uncore_forcewake_user_get(gt->uncore); 33 } 34 35 void intel_gt_pm_debugfs_forcewake_user_release(struct intel_gt *gt) 36 { 37 if (GRAPHICS_VER(gt->i915) >= 6) 38 intel_uncore_forcewake_user_put(gt->uncore); 39 intel_gt_pm_put(gt); 40 atomic_dec(>->user_wakeref); 41 } 42 43 static int forcewake_user_open(struct inode *inode, struct file *file) 44 { 45 struct intel_gt *gt = inode->i_private; 46 47 intel_gt_pm_debugfs_forcewake_user_open(gt); 48 49 return 0; 50 } 51 52 static int forcewake_user_release(struct inode *inode, struct file *file) 53 { 54 struct intel_gt *gt = inode->i_private; 55 56 intel_gt_pm_debugfs_forcewake_user_release(gt); 57 58 return 0; 59 } 60 61 static const struct file_operations forcewake_user_fops = { 62 .owner = THIS_MODULE, 63 .open = forcewake_user_open, 64 .release = forcewake_user_release, 65 }; 66 67 static int fw_domains_show(struct seq_file *m, void *data) 68 { 69 struct intel_gt *gt = m->private; 70 struct intel_uncore *uncore = gt->uncore; 71 struct intel_uncore_forcewake_domain *fw_domain; 72 unsigned int tmp; 73 74 seq_printf(m, "user.bypass_count = %u\n", 75 uncore->user_forcewake_count); 76 77 for_each_fw_domain(fw_domain, uncore, tmp) 78 seq_printf(m, "%s.wake_count = %u\n", 79 intel_uncore_forcewake_domain_to_str(fw_domain->id), 80 READ_ONCE(fw_domain->wake_count)); 81 82 return 0; 83 } 84 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains); 85 86 static int vlv_drpc(struct seq_file *m) 87 { 88 struct intel_gt *gt = m->private; 89 struct intel_uncore *uncore = gt->uncore; 90 u32 rcctl1, pw_status, mt_fwake_req; 91 92 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 93 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); 94 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 95 96 seq_printf(m, "RC6 Enabled: %s\n", 97 str_yes_no(rcctl1 & (GEN7_RC_CTL_TO_MODE | 98 GEN6_RC_CTL_EI_MODE(1)))); 99 seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req); 100 seq_printf(m, "Render Power Well: %s\n", 101 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 102 seq_printf(m, "Media Power Well: %s\n", 103 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 104 105 intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6); 106 intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA); 107 108 return fw_domains_show(m, NULL); 109 } 110 111 static int gen6_drpc(struct seq_file *m) 112 { 113 struct intel_gt *gt = m->private; 114 struct drm_i915_private *i915 = gt->i915; 115 struct intel_uncore *uncore = gt->uncore; 116 u32 gt_core_status, mt_fwake_req, rcctl1, rc6vids = 0; 117 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; 118 119 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 120 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); 121 122 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 123 if (GRAPHICS_VER(i915) >= 9) { 124 gen9_powergate_enable = 125 intel_uncore_read(uncore, GEN9_PG_ENABLE); 126 gen9_powergate_status = 127 intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS); 128 } 129 130 if (GRAPHICS_VER(i915) <= 7) 131 snb_pcode_read(gt->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL); 132 133 seq_printf(m, "RC1e Enabled: %s\n", 134 str_yes_no(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 135 seq_printf(m, "RC6 Enabled: %s\n", 136 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 137 if (GRAPHICS_VER(i915) >= 9) { 138 seq_printf(m, "Render Well Gating Enabled: %s\n", 139 str_yes_no(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); 140 seq_printf(m, "Media Well Gating Enabled: %s\n", 141 str_yes_no(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 142 } 143 seq_printf(m, "Deep RC6 Enabled: %s\n", 144 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 145 seq_printf(m, "Deepest RC6 Enabled: %s\n", 146 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 147 seq_puts(m, "Current RC state: "); 148 switch (gt_core_status & GEN6_RCn_MASK) { 149 case GEN6_RC0: 150 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 151 seq_puts(m, "Core Power Down\n"); 152 else 153 seq_puts(m, "on\n"); 154 break; 155 case GEN6_RC3: 156 seq_puts(m, "RC3\n"); 157 break; 158 case GEN6_RC6: 159 seq_puts(m, "RC6\n"); 160 break; 161 case GEN6_RC7: 162 seq_puts(m, "RC7\n"); 163 break; 164 default: 165 seq_puts(m, "Unknown\n"); 166 break; 167 } 168 169 seq_printf(m, "Core Power Down: %s\n", 170 str_yes_no(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 171 seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req); 172 if (GRAPHICS_VER(i915) >= 9) { 173 seq_printf(m, "Render Power Well: %s\n", 174 (gen9_powergate_status & 175 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 176 seq_printf(m, "Media Power Well: %s\n", 177 (gen9_powergate_status & 178 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 179 } 180 181 /* Not exactly sure what this is */ 182 intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:", 183 INTEL_RC6_RES_RC6_LOCKED); 184 intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); 185 intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p); 186 intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp); 187 188 if (GRAPHICS_VER(i915) <= 7) { 189 seq_printf(m, "RC6 voltage: %dmV\n", 190 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 191 seq_printf(m, "RC6+ voltage: %dmV\n", 192 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 193 seq_printf(m, "RC6++ voltage: %dmV\n", 194 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 195 } 196 197 return fw_domains_show(m, NULL); 198 } 199 200 static int ilk_drpc(struct seq_file *m) 201 { 202 struct intel_gt *gt = m->private; 203 struct intel_uncore *uncore = gt->uncore; 204 u32 rgvmodectl, rstdbyctl; 205 u16 crstandvid; 206 207 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); 208 rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL); 209 crstandvid = intel_uncore_read16(uncore, CRSTANDVID); 210 211 seq_printf(m, "HD boost: %s\n", 212 str_yes_no(rgvmodectl & MEMMODE_BOOST_EN)); 213 seq_printf(m, "Boost freq: %d\n", 214 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 215 MEMMODE_BOOST_FREQ_SHIFT); 216 seq_printf(m, "HW control enabled: %s\n", 217 str_yes_no(rgvmodectl & MEMMODE_HWIDLE_EN)); 218 seq_printf(m, "SW control enabled: %s\n", 219 str_yes_no(rgvmodectl & MEMMODE_SWMODE_EN)); 220 seq_printf(m, "Gated voltage change: %s\n", 221 str_yes_no(rgvmodectl & MEMMODE_RCLK_GATE)); 222 seq_printf(m, "Starting frequency: P%d\n", 223 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 224 seq_printf(m, "Max P-state: P%d\n", 225 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 226 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 227 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 228 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 229 seq_printf(m, "Render standby enabled: %s\n", 230 str_yes_no(!(rstdbyctl & RCX_SW_EXIT))); 231 seq_puts(m, "Current RS state: "); 232 switch (rstdbyctl & RSX_STATUS_MASK) { 233 case RSX_STATUS_ON: 234 seq_puts(m, "on\n"); 235 break; 236 case RSX_STATUS_RC1: 237 seq_puts(m, "RC1\n"); 238 break; 239 case RSX_STATUS_RC1E: 240 seq_puts(m, "RC1E\n"); 241 break; 242 case RSX_STATUS_RS1: 243 seq_puts(m, "RS1\n"); 244 break; 245 case RSX_STATUS_RS2: 246 seq_puts(m, "RS2 (RC6)\n"); 247 break; 248 case RSX_STATUS_RS3: 249 seq_puts(m, "RC3 (RC6+)\n"); 250 break; 251 default: 252 seq_puts(m, "unknown\n"); 253 break; 254 } 255 256 return 0; 257 } 258 259 static int mtl_drpc(struct seq_file *m) 260 { 261 struct intel_gt *gt = m->private; 262 struct intel_uncore *uncore = gt->uncore; 263 u32 gt_core_status, rcctl1, mt_fwake_req; 264 u32 mtl_powergate_enable = 0, mtl_powergate_status = 0; 265 266 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 267 gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); 268 269 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); 270 mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); 271 mtl_powergate_status = intel_uncore_read(uncore, 272 GEN9_PWRGT_DOMAIN_STATUS); 273 274 seq_printf(m, "RC6 Enabled: %s\n", 275 str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 276 if (gt->type == GT_MEDIA) { 277 seq_printf(m, "Media Well Gating Enabled: %s\n", 278 str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 279 } else { 280 seq_printf(m, "Render Well Gating Enabled: %s\n", 281 str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE)); 282 } 283 284 seq_puts(m, "Current RC state: "); 285 switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) { 286 case MTL_CC0: 287 seq_puts(m, "RC0\n"); 288 break; 289 case MTL_CC6: 290 seq_puts(m, "RC6\n"); 291 break; 292 default: 293 MISSING_CASE(REG_FIELD_GET(MTL_CC_MASK, gt_core_status)); 294 seq_puts(m, "Unknown\n"); 295 break; 296 } 297 298 seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req); 299 if (gt->type == GT_MEDIA) 300 seq_printf(m, "Media Power Well: %s\n", 301 (mtl_powergate_status & 302 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 303 else 304 seq_printf(m, "Render Power Well: %s\n", 305 (mtl_powergate_status & 306 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 307 308 /* Works for both render and media gt's */ 309 intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); 310 311 return fw_domains_show(m, NULL); 312 } 313 314 static int drpc_show(struct seq_file *m, void *unused) 315 { 316 struct intel_gt *gt = m->private; 317 struct drm_i915_private *i915 = gt->i915; 318 intel_wakeref_t wakeref; 319 int err = -ENODEV; 320 321 with_intel_runtime_pm(gt->uncore->rpm, wakeref) { 322 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 323 err = mtl_drpc(m); 324 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 325 err = vlv_drpc(m); 326 else if (GRAPHICS_VER(i915) >= 6) 327 err = gen6_drpc(m); 328 else 329 err = ilk_drpc(m); 330 } 331 332 return err; 333 } 334 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(drpc); 335 336 void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) 337 { 338 struct drm_i915_private *i915 = gt->i915; 339 struct intel_uncore *uncore = gt->uncore; 340 struct intel_rps *rps = >->rps; 341 intel_wakeref_t wakeref; 342 343 wakeref = intel_runtime_pm_get(uncore->rpm); 344 345 if (GRAPHICS_VER(i915) == 5) { 346 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 347 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); 348 349 drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 350 drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f); 351 drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 352 MEMSTAT_VID_SHIFT); 353 drm_printf(p, "Current P-state: %d\n", 354 REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat)); 355 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 356 u32 rpmodectl, freq_sts; 357 358 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); 359 drm_printf(p, "Video Turbo Mode: %s\n", 360 str_yes_no(rpmodectl & GEN6_RP_MEDIA_TURBO)); 361 drm_printf(p, "HW control enabled: %s\n", 362 str_yes_no(rpmodectl & GEN6_RP_ENABLE)); 363 drm_printf(p, "SW control enabled: %s\n", 364 str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); 365 366 vlv_punit_get(i915); 367 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); 368 vlv_punit_put(i915); 369 370 drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 371 drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); 372 373 drm_printf(p, "actual GPU freq: %d MHz\n", 374 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); 375 376 drm_printf(p, "current GPU freq: %d MHz\n", 377 intel_gpu_freq(rps, rps->cur_freq)); 378 379 drm_printf(p, "max GPU freq: %d MHz\n", 380 intel_gpu_freq(rps, rps->max_freq)); 381 382 drm_printf(p, "min GPU freq: %d MHz\n", 383 intel_gpu_freq(rps, rps->min_freq)); 384 385 drm_printf(p, "idle GPU freq: %d MHz\n", 386 intel_gpu_freq(rps, rps->idle_freq)); 387 388 drm_printf(p, "efficient (RPe) frequency: %d MHz\n", 389 intel_gpu_freq(rps, rps->efficient_freq)); 390 } else if (GRAPHICS_VER(i915) >= 6) { 391 gen6_rps_frequency_dump(rps, p); 392 } else { 393 drm_puts(p, "no P-state info available\n"); 394 } 395 396 drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); 397 drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); 398 drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); 399 400 intel_runtime_pm_put(uncore->rpm, wakeref); 401 } 402 403 static int frequency_show(struct seq_file *m, void *unused) 404 { 405 struct intel_gt *gt = m->private; 406 struct drm_printer p = drm_seq_file_printer(m); 407 408 intel_gt_pm_frequency_dump(gt, &p); 409 410 return 0; 411 } 412 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(frequency); 413 414 static int llc_show(struct seq_file *m, void *data) 415 { 416 struct intel_gt *gt = m->private; 417 struct drm_i915_private *i915 = gt->i915; 418 const bool edram = GRAPHICS_VER(i915) > 8; 419 struct intel_rps *rps = >->rps; 420 unsigned int max_gpu_freq, min_gpu_freq; 421 intel_wakeref_t wakeref; 422 int gpu_freq, ia_freq; 423 424 seq_printf(m, "LLC: %s\n", str_yes_no(HAS_LLC(i915))); 425 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC", 426 i915->edram_size_mb); 427 428 min_gpu_freq = rps->min_freq; 429 max_gpu_freq = rps->max_freq; 430 if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { 431 /* Convert GT frequency to 50 HZ units */ 432 min_gpu_freq /= GEN9_FREQ_SCALER; 433 max_gpu_freq /= GEN9_FREQ_SCALER; 434 } 435 436 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 437 438 wakeref = intel_runtime_pm_get(gt->uncore->rpm); 439 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 440 ia_freq = gpu_freq; 441 snb_pcode_read(gt->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE, 442 &ia_freq, NULL); 443 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 444 intel_gpu_freq(rps, 445 (gpu_freq * 446 (IS_GEN9_BC(i915) || 447 GRAPHICS_VER(i915) >= 11 ? 448 GEN9_FREQ_SCALER : 1))), 449 ((ia_freq >> 0) & 0xff) * 100, 450 ((ia_freq >> 8) & 0xff) * 100); 451 } 452 intel_runtime_pm_put(gt->uncore->rpm, wakeref); 453 454 return 0; 455 } 456 457 static bool llc_eval(void *data) 458 { 459 struct intel_gt *gt = data; 460 461 return HAS_LLC(gt->i915); 462 } 463 464 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(llc); 465 466 static const char *rps_power_to_str(unsigned int power) 467 { 468 static const char * const strings[] = { 469 [LOW_POWER] = "low power", 470 [BETWEEN] = "mixed", 471 [HIGH_POWER] = "high power", 472 }; 473 474 if (power >= ARRAY_SIZE(strings) || !strings[power]) 475 return "unknown"; 476 477 return strings[power]; 478 } 479 480 static int rps_boost_show(struct seq_file *m, void *data) 481 { 482 struct intel_gt *gt = m->private; 483 struct drm_i915_private *i915 = gt->i915; 484 struct intel_rps *rps = >->rps; 485 486 seq_printf(m, "RPS enabled? %s\n", 487 str_yes_no(intel_rps_is_enabled(rps))); 488 seq_printf(m, "RPS active? %s\n", 489 str_yes_no(intel_rps_is_active(rps))); 490 seq_printf(m, "GPU busy? %s, %llums\n", 491 str_yes_no(gt->awake), 492 ktime_to_ms(intel_gt_get_awake_time(gt))); 493 seq_printf(m, "Boosts outstanding? %d\n", 494 atomic_read(&rps->num_waiters)); 495 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 496 seq_printf(m, "Frequency requested %d, actual %d\n", 497 intel_gpu_freq(rps, rps->cur_freq), 498 intel_rps_read_actual_frequency(rps)); 499 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 500 intel_gpu_freq(rps, rps->min_freq), 501 intel_gpu_freq(rps, rps->min_freq_softlimit), 502 intel_gpu_freq(rps, rps->max_freq_softlimit), 503 intel_gpu_freq(rps, rps->max_freq)); 504 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 505 intel_gpu_freq(rps, rps->idle_freq), 506 intel_gpu_freq(rps, rps->efficient_freq), 507 intel_gpu_freq(rps, rps->boost_freq)); 508 509 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 510 511 if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) { 512 struct intel_uncore *uncore = gt->uncore; 513 u32 rpup, rpupei; 514 u32 rpdown, rpdownei; 515 516 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 517 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; 518 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; 519 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; 520 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; 521 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 522 523 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", 524 rps_power_to_str(rps->power.mode)); 525 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", 526 rpup && rpupei ? 100 * rpup / rpupei : 0, 527 rps->power.up_threshold); 528 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", 529 rpdown && rpdownei ? 100 * rpdown / rpdownei : 0, 530 rps->power.down_threshold); 531 } else { 532 seq_puts(m, "\nRPS Autotuning inactive\n"); 533 } 534 535 return 0; 536 } 537 538 static bool rps_eval(void *data) 539 { 540 struct intel_gt *gt = data; 541 542 if (intel_guc_slpc_is_used(>->uc.guc)) 543 return false; 544 else 545 return HAS_RPS(gt->i915); 546 } 547 548 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost); 549 550 static int perf_limit_reasons_get(void *data, u64 *val) 551 { 552 struct intel_gt *gt = data; 553 intel_wakeref_t wakeref; 554 555 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 556 *val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt)); 557 558 return 0; 559 } 560 561 static int perf_limit_reasons_clear(void *data, u64 val) 562 { 563 struct intel_gt *gt = data; 564 intel_wakeref_t wakeref; 565 566 /* 567 * Clear the upper 16 "log" bits, the lower 16 "status" bits are 568 * read-only. The upper 16 "log" bits are identical to the lower 16 569 * "status" bits except that the "log" bits remain set until cleared. 570 */ 571 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 572 intel_uncore_rmw(gt->uncore, intel_gt_perf_limit_reasons_reg(gt), 573 GT0_PERF_LIMIT_REASONS_LOG_MASK, 0); 574 575 return 0; 576 } 577 578 static bool perf_limit_reasons_eval(void *data) 579 { 580 struct intel_gt *gt = data; 581 582 return i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt)); 583 } 584 585 DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get, 586 perf_limit_reasons_clear, "0x%llx\n"); 587 588 void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) 589 { 590 static const struct intel_gt_debugfs_file files[] = { 591 { "drpc", &drpc_fops, NULL }, 592 { "frequency", &frequency_fops, NULL }, 593 { "forcewake", &fw_domains_fops, NULL }, 594 { "forcewake_user", &forcewake_user_fops, NULL}, 595 { "llc", &llc_fops, llc_eval }, 596 { "rps_boost", &rps_boost_fops, rps_eval }, 597 { "perf_limit_reasons", &perf_limit_reasons_fops, perf_limit_reasons_eval }, 598 }; 599 600 intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); 601 } 602