1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/sched/clock.h> 7 8 #include <drm/intel/intel_gmd_interrupt_regs.h> 9 10 #include "i915_drv.h" 11 #include "i915_irq.h" 12 #include "i915_reg.h" 13 #include "intel_breadcrumbs.h" 14 #include "intel_gt.h" 15 #include "intel_gt_irq.h" 16 #include "intel_gt_print.h" 17 #include "intel_gt_regs.h" 18 #include "intel_uncore.h" 19 #include "intel_rps.h" 20 #include "pxp/intel_pxp_irq.h" 21 #include "uc/intel_gsc_proxy.h" 22 23 static void guc_irq_handler(struct intel_guc *guc, u16 iir) 24 { 25 if (unlikely(!guc->interrupts.enabled)) 26 return; 27 28 if (iir & GUC_INTR_GUC2HOST) 29 intel_guc_to_host_event_handler(guc); 30 } 31 32 static u32 33 gen11_gt_engine_identity(struct intel_gt *gt, 34 const unsigned int bank, const unsigned int bit) 35 { 36 void __iomem * const regs = intel_uncore_regs(gt->uncore); 37 u32 timeout_ts; 38 u32 ident; 39 40 lockdep_assert_held(gt->irq_lock); 41 42 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); 43 44 /* 45 * NB: Specs do not specify how long to spin wait, 46 * so we do ~100us as an educated guess. 47 */ 48 timeout_ts = (local_clock() >> 10) + 100; 49 do { 50 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); 51 } while (!(ident & GEN11_INTR_DATA_VALID) && 52 !time_after32(local_clock() >> 10, timeout_ts)); 53 54 if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) { 55 gt_err(gt, "INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n", 56 bank, bit, ident); 57 return 0; 58 } 59 60 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), 61 GEN11_INTR_DATA_VALID); 62 63 return ident; 64 } 65 66 static void 67 gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, 68 const u16 iir) 69 { 70 struct intel_gt *media_gt = gt->i915->media_gt; 71 72 if (instance == OTHER_GUC_INSTANCE) 73 return guc_irq_handler(gt_to_guc(gt), iir); 74 if (instance == OTHER_MEDIA_GUC_INSTANCE && media_gt) 75 return guc_irq_handler(gt_to_guc(media_gt), iir); 76 77 if (instance == OTHER_GTPM_INSTANCE) 78 return gen11_rps_irq_handler(>->rps, iir); 79 if (instance == OTHER_MEDIA_GTPM_INSTANCE && media_gt) 80 return gen11_rps_irq_handler(&media_gt->rps, iir); 81 82 if (instance == OTHER_KCR_INSTANCE) 83 return intel_pxp_irq_handler(gt->i915->pxp, iir); 84 85 if (instance == OTHER_GSC_INSTANCE) 86 return intel_gsc_irq_handler(gt, iir); 87 88 if (instance == OTHER_GSC_HECI_2_INSTANCE) 89 return intel_gsc_proxy_irq_handler(>->uc.gsc, iir); 90 91 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", 92 instance, iir); 93 } 94 95 static struct intel_gt *pick_gt(struct intel_gt *gt, u8 class, u8 instance) 96 { 97 struct intel_gt *media_gt = gt->i915->media_gt; 98 99 /* we expect the non-media gt to be passed in */ 100 GEM_BUG_ON(gt == media_gt); 101 102 if (!media_gt) 103 return gt; 104 105 switch (class) { 106 case VIDEO_DECODE_CLASS: 107 case VIDEO_ENHANCEMENT_CLASS: 108 return media_gt; 109 case OTHER_CLASS: 110 if (instance == OTHER_GSC_HECI_2_INSTANCE) 111 return media_gt; 112 if ((instance == OTHER_GSC_INSTANCE || instance == OTHER_KCR_INSTANCE) && 113 HAS_ENGINE(media_gt, GSC0)) 114 return media_gt; 115 fallthrough; 116 default: 117 return gt; 118 } 119 } 120 121 static void 122 gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) 123 { 124 const u8 class = GEN11_INTR_ENGINE_CLASS(identity); 125 const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity); 126 const u16 intr = GEN11_INTR_ENGINE_INTR(identity); 127 128 if (unlikely(!intr)) 129 return; 130 131 /* 132 * Platforms with standalone media have the media and GSC engines in 133 * another GT. 134 */ 135 gt = pick_gt(gt, class, instance); 136 137 if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) { 138 struct intel_engine_cs *engine = gt->engine_class[class][instance]; 139 if (engine) 140 return intel_engine_cs_irq(engine, intr); 141 } 142 143 if (class == OTHER_CLASS) 144 return gen11_other_irq_handler(gt, instance, intr); 145 146 WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n", 147 class, instance, intr); 148 } 149 150 static void 151 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) 152 { 153 void __iomem * const regs = intel_uncore_regs(gt->uncore); 154 unsigned long intr_dw; 155 unsigned int bit; 156 157 lockdep_assert_held(gt->irq_lock); 158 159 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 160 161 for_each_set_bit(bit, &intr_dw, 32) { 162 const u32 ident = gen11_gt_engine_identity(gt, bank, bit); 163 164 gen11_gt_identity_handler(gt, ident); 165 } 166 167 /* Clear must be after shared has been served for engine */ 168 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); 169 } 170 171 void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl) 172 { 173 unsigned int bank; 174 175 spin_lock(gt->irq_lock); 176 177 for (bank = 0; bank < 2; bank++) { 178 if (master_ctl & GEN11_GT_DW_IRQ(bank)) 179 gen11_gt_bank_handler(gt, bank); 180 } 181 182 spin_unlock(gt->irq_lock); 183 } 184 185 bool gen11_gt_reset_one_iir(struct intel_gt *gt, 186 const unsigned int bank, const unsigned int bit) 187 { 188 void __iomem * const regs = intel_uncore_regs(gt->uncore); 189 u32 dw; 190 191 lockdep_assert_held(gt->irq_lock); 192 193 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); 194 if (dw & BIT(bit)) { 195 /* 196 * According to the BSpec, DW_IIR bits cannot be cleared without 197 * first servicing the Selector & Shared IIR registers. 198 */ 199 gen11_gt_engine_identity(gt, bank, bit); 200 201 /* 202 * We locked GT INT DW by reading it. If we want to (try 203 * to) recover from this successfully, we need to clear 204 * our bit, otherwise we are locking the register for 205 * everybody. 206 */ 207 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), BIT(bit)); 208 209 return true; 210 } 211 212 return false; 213 } 214 215 void gen11_gt_irq_reset(struct intel_gt *gt) 216 { 217 struct intel_uncore *uncore = gt->uncore; 218 219 /* Disable RCS, BCS, VCS and VECS class engines. */ 220 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); 221 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); 222 if (CCS_MASK(gt)) 223 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); 224 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 225 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0); 226 227 /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ 228 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); 229 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); 230 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 231 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0); 232 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 233 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0); 234 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 235 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0); 236 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 237 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0); 238 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); 239 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); 240 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 241 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~0); 242 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 243 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~0); 244 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); 245 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 246 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); 247 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 248 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); 249 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 250 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); 251 if (HAS_HECI_GSC(gt->i915) || HAS_ENGINE(gt, GSC0)) 252 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0); 253 254 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 255 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 256 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 257 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0); 258 259 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0); 260 intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0); 261 } 262 263 void gen11_gt_irq_postinstall(struct intel_gt *gt) 264 { 265 struct intel_uncore *uncore = gt->uncore; 266 u32 irqs = GT_RENDER_USER_INTERRUPT; 267 u32 guc_mask = intel_uc_wants_guc(>->uc) ? GUC_INTR_GUC2HOST : 0; 268 u32 gsc_mask = 0; 269 u32 heci_mask = 0; 270 u32 dmask; 271 u32 smask; 272 273 if (!intel_uc_wants_guc_submission(>->uc)) 274 irqs |= GT_CS_MASTER_ERROR_INTERRUPT | 275 GT_CONTEXT_SWITCH_INTERRUPT | 276 GT_WAIT_SEMAPHORE_INTERRUPT; 277 278 dmask = irqs << 16 | irqs; 279 smask = irqs << 16; 280 281 if (HAS_ENGINE(gt, GSC0)) { 282 /* 283 * the heci2 interrupt is enabled via the same register as the 284 * GSC interrupt, but it has its own mask register. 285 */ 286 gsc_mask = irqs; 287 heci_mask = GSC_IRQ_INTF(1); /* HECI2 IRQ for SW Proxy*/ 288 } else if (HAS_HECI_GSC(gt->i915)) { 289 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1); 290 } 291 292 BUILD_BUG_ON(irqs & 0xffff0000); 293 294 /* Enable RCS, BCS, VCS and VECS class interrupts. */ 295 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); 296 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); 297 if (CCS_MASK(gt)) 298 intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); 299 if (gsc_mask) 300 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, gsc_mask | heci_mask); 301 302 /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ 303 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); 304 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask); 305 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) 306 intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask); 307 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) 308 intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask); 309 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) 310 intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask); 311 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) 312 intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask); 313 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask); 314 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask); 315 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) 316 intel_uncore_write(uncore, GEN12_VCS4_VCS5_INTR_MASK, ~dmask); 317 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) 318 intel_uncore_write(uncore, GEN12_VCS6_VCS7_INTR_MASK, ~dmask); 319 intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); 320 if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) 321 intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); 322 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) 323 intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); 324 if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) 325 intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); 326 if (gsc_mask) 327 intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask); 328 if (heci_mask) 329 intel_uncore_write(uncore, GEN12_HECI2_RSVD_INTR_MASK, 330 ~REG_FIELD_PREP(ENGINE1_MASK, heci_mask)); 331 332 if (guc_mask) { 333 /* the enable bit is common for both GTs but the masks are separate */ 334 u32 mask = gt->type == GT_MEDIA ? 335 REG_FIELD_PREP(ENGINE0_MASK, guc_mask) : 336 REG_FIELD_PREP(ENGINE1_MASK, guc_mask); 337 338 intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 339 REG_FIELD_PREP(ENGINE1_MASK, guc_mask)); 340 341 /* we might not be the first GT to write this reg */ 342 intel_uncore_rmw(uncore, MTL_GUC_MGUC_INTR_MASK, mask, 0); 343 } 344 345 /* 346 * RPS interrupts will get enabled/disabled on demand when RPS itself 347 * is enabled/disabled. 348 */ 349 gt->pm_ier = 0x0; 350 gt->pm_imr = ~gt->pm_ier; 351 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); 352 intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); 353 } 354 355 void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 356 { 357 if (gt_iir & GT_RENDER_USER_INTERRUPT) 358 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 359 gt_iir); 360 361 if (gt_iir & ILK_BSD_USER_INTERRUPT) 362 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 363 gt_iir); 364 } 365 366 static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) 367 { 368 if (!HAS_L3_DPF(gt->i915)) 369 return; 370 371 spin_lock(gt->irq_lock); 372 gen5_gt_disable_irq(gt, GT_PARITY_ERROR(gt->i915)); 373 spin_unlock(gt->irq_lock); 374 375 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 376 gt->i915->l3_parity.which_slice |= 1 << 1; 377 378 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 379 gt->i915->l3_parity.which_slice |= 1 << 0; 380 381 queue_work(gt->i915->unordered_wq, >->i915->l3_parity.error_work); 382 } 383 384 void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 385 { 386 if (gt_iir & GT_RENDER_USER_INTERRUPT) 387 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 388 gt_iir); 389 390 if (gt_iir & GT_BSD_USER_INTERRUPT) 391 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 392 gt_iir >> 12); 393 394 if (gt_iir & GT_BLT_USER_INTERRUPT) 395 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 396 gt_iir >> 22); 397 398 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 399 GT_BSD_CS_ERROR_INTERRUPT | 400 GT_CS_MASTER_ERROR_INTERRUPT)) 401 gt_dbg(gt, "Command parser error, gt_iir 0x%08x\n", gt_iir); 402 403 if (gt_iir & GT_PARITY_ERROR(gt->i915)) 404 gen7_parity_error_irq_handler(gt, gt_iir); 405 } 406 407 void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl) 408 { 409 void __iomem * const regs = intel_uncore_regs(gt->uncore); 410 u32 iir; 411 412 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 413 iir = raw_reg_read(regs, GEN8_GT_IIR(0)); 414 if (likely(iir)) { 415 intel_engine_cs_irq(gt->engine_class[RENDER_CLASS][0], 416 iir >> GEN8_RCS_IRQ_SHIFT); 417 intel_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0], 418 iir >> GEN8_BCS_IRQ_SHIFT); 419 raw_reg_write(regs, GEN8_GT_IIR(0), iir); 420 } 421 } 422 423 if (master_ctl & (GEN8_GT_VCS0_IRQ | GEN8_GT_VCS1_IRQ)) { 424 iir = raw_reg_read(regs, GEN8_GT_IIR(1)); 425 if (likely(iir)) { 426 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0], 427 iir >> GEN8_VCS0_IRQ_SHIFT); 428 intel_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][1], 429 iir >> GEN8_VCS1_IRQ_SHIFT); 430 raw_reg_write(regs, GEN8_GT_IIR(1), iir); 431 } 432 } 433 434 if (master_ctl & GEN8_GT_VECS_IRQ) { 435 iir = raw_reg_read(regs, GEN8_GT_IIR(3)); 436 if (likely(iir)) { 437 intel_engine_cs_irq(gt->engine_class[VIDEO_ENHANCEMENT_CLASS][0], 438 iir >> GEN8_VECS_IRQ_SHIFT); 439 raw_reg_write(regs, GEN8_GT_IIR(3), iir); 440 } 441 } 442 443 if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) { 444 iir = raw_reg_read(regs, GEN8_GT_IIR(2)); 445 if (likely(iir)) { 446 gen6_rps_irq_handler(>->rps, iir); 447 guc_irq_handler(gt_to_guc(gt), iir >> 16); 448 raw_reg_write(regs, GEN8_GT_IIR(2), iir); 449 } 450 } 451 } 452 453 void gen8_gt_irq_reset(struct intel_gt *gt) 454 { 455 struct intel_uncore *uncore = gt->uncore; 456 457 gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(0)); 458 gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(1)); 459 gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(2)); 460 gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(3)); 461 } 462 463 void gen8_gt_irq_postinstall(struct intel_gt *gt) 464 { 465 /* These are interrupts we'll toggle with the ring mask register */ 466 const u32 irqs = 467 GT_CS_MASTER_ERROR_INTERRUPT | 468 GT_RENDER_USER_INTERRUPT | 469 GT_CONTEXT_SWITCH_INTERRUPT | 470 GT_WAIT_SEMAPHORE_INTERRUPT; 471 const u32 gt_interrupts[] = { 472 irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT, 473 irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT, 474 0, 475 irqs << GEN8_VECS_IRQ_SHIFT, 476 }; 477 struct intel_uncore *uncore = gt->uncore; 478 479 gt->pm_ier = 0x0; 480 gt->pm_imr = ~gt->pm_ier; 481 gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(0), ~gt_interrupts[0], gt_interrupts[0]); 482 gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]); 483 /* 484 * RPS interrupts will get enabled/disabled on demand when RPS itself 485 * is enabled/disabled. Same will be the case for GuC interrupts. 486 */ 487 gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier); 488 gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]); 489 } 490 491 static void gen5_gt_update_irq(struct intel_gt *gt, 492 u32 interrupt_mask, 493 u32 enabled_irq_mask) 494 { 495 lockdep_assert_held(gt->irq_lock); 496 497 GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask); 498 499 gt->gt_imr &= ~interrupt_mask; 500 gt->gt_imr |= (~enabled_irq_mask & interrupt_mask); 501 intel_uncore_write(gt->uncore, GTIMR, gt->gt_imr); 502 } 503 504 void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask) 505 { 506 gen5_gt_update_irq(gt, mask, mask); 507 intel_uncore_posting_read_fw(gt->uncore, GTIMR); 508 } 509 510 void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask) 511 { 512 gen5_gt_update_irq(gt, mask, 0); 513 } 514 515 void gen5_gt_irq_reset(struct intel_gt *gt) 516 { 517 struct intel_uncore *uncore = gt->uncore; 518 519 gen2_irq_reset(uncore, GT_IRQ_REGS); 520 if (GRAPHICS_VER(gt->i915) >= 6) 521 gen2_irq_reset(uncore, GEN6_PM_IRQ_REGS); 522 } 523 524 void gen5_gt_irq_postinstall(struct intel_gt *gt) 525 { 526 struct intel_uncore *uncore = gt->uncore; 527 u32 pm_irqs = 0; 528 u32 gt_irqs = 0; 529 530 gt->gt_imr = ~0; 531 if (HAS_L3_DPF(gt->i915)) { 532 /* L3 parity interrupt is always unmasked. */ 533 gt->gt_imr = ~GT_PARITY_ERROR(gt->i915); 534 gt_irqs |= GT_PARITY_ERROR(gt->i915); 535 } 536 537 gt_irqs |= GT_RENDER_USER_INTERRUPT; 538 if (GRAPHICS_VER(gt->i915) == 5) 539 gt_irqs |= ILK_BSD_USER_INTERRUPT; 540 else 541 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 542 543 gen2_irq_init(uncore, GT_IRQ_REGS, gt->gt_imr, gt_irqs); 544 545 if (GRAPHICS_VER(gt->i915) >= 6) { 546 /* 547 * RPS interrupts will get enabled/disabled on demand when RPS 548 * itself is enabled/disabled. 549 */ 550 if (HAS_ENGINE(gt, VECS0)) { 551 pm_irqs |= PM_VEBOX_USER_INTERRUPT; 552 gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; 553 } 554 555 gt->pm_imr = 0xffffffff; 556 gen2_irq_init(uncore, GEN6_PM_IRQ_REGS, gt->pm_imr, pm_irqs); 557 } 558 } 559