1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT__ 7 #define __INTEL_GT__ 8 9 #include "intel_engine_types.h" 10 #include "intel_gt_types.h" 11 #include "intel_reset.h" 12 13 struct drm_i915_private; 14 struct drm_printer; 15 16 /* 17 * Check that the GT is a graphics GT and has an IP version within the 18 * specified range (inclusive). 19 */ 20 #define IS_GFX_GT_IP_RANGE(gt, from, until) ( \ 21 BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ 22 BUILD_BUG_ON_ZERO((until) < (from)) + \ 23 ((gt)->type != GT_MEDIA && \ 24 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \ 25 GRAPHICS_VER_FULL((gt)->i915) <= (until))) 26 27 /* 28 * Check that the GT is a media GT and has an IP version within the 29 * specified range (inclusive). 30 * 31 * Only usable on platforms with a standalone media design (i.e., IP version 13 32 * and higher). 33 */ 34 #define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \ 35 BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \ 36 BUILD_BUG_ON_ZERO((until) < (from)) + \ 37 ((gt) && (gt)->type == GT_MEDIA && \ 38 MEDIA_VER_FULL((gt)->i915) >= (from) && \ 39 MEDIA_VER_FULL((gt)->i915) <= (until))) 40 41 /* 42 * Check that the GT is a graphics GT with a specific IP version and has 43 * a stepping in the range [from, until). The lower stepping bound is 44 * inclusive, the upper bound is exclusive. The most common use-case of this 45 * macro is for checking bounds for workarounds, which usually have a stepping 46 * ("from") at which the hardware issue is first present and another stepping 47 * ("until") at which a hardware fix is present and the software workaround is 48 * no longer necessary. E.g., 49 * 50 * IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) 51 * IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER) 52 * 53 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 54 * stepping bound for the specified IP version. 55 */ 56 #define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \ 57 BUILD_BUG_ON_ZERO((until) <= (from)) + \ 58 (IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \ 59 IS_GRAPHICS_STEP((gt)->i915, (from), (until)))) 60 61 /* 62 * Check that the GT is a media GT with a specific IP version and has 63 * a stepping in the range [from, until). The lower stepping bound is 64 * inclusive, the upper bound is exclusive. The most common use-case of this 65 * macro is for checking bounds for workarounds, which usually have a stepping 66 * ("from") at which the hardware issue is first present and another stepping 67 * ("until") at which a hardware fix is present and the software workaround is 68 * no longer necessary. "STEP_FOREVER" can be passed as "until" for 69 * workarounds that have no upper stepping bound for the specified IP version. 70 * 71 * This macro may only be used to match on platforms that have a standalone 72 * media design (i.e., media version 13 or higher). 73 */ 74 #define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \ 75 BUILD_BUG_ON_ZERO((until) <= (from)) + \ 76 (IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \ 77 IS_MEDIA_STEP((gt)->i915, (from), (until)))) 78 79 #define GT_TRACE(gt, fmt, ...) do { \ 80 const struct intel_gt *gt__ __maybe_unused = (gt); \ 81 GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \ 82 ##__VA_ARGS__); \ 83 } while (0) 84 85 static inline bool gt_is_root(struct intel_gt *gt) 86 { 87 return !gt->info.id; 88 } 89 90 bool intel_gt_needs_wa_22016122933(struct intel_gt *gt); 91 92 static inline struct intel_gt *uc_to_gt(struct intel_uc *uc) 93 { 94 return container_of(uc, struct intel_gt, uc); 95 } 96 97 static inline struct intel_gt *guc_to_gt(struct intel_guc *guc) 98 { 99 return container_of(guc, struct intel_gt, uc.guc); 100 } 101 102 static inline struct intel_gt *huc_to_gt(struct intel_huc *huc) 103 { 104 return container_of(huc, struct intel_gt, uc.huc); 105 } 106 107 static inline struct intel_gt *gsc_uc_to_gt(struct intel_gsc_uc *gsc_uc) 108 { 109 return container_of(gsc_uc, struct intel_gt, uc.gsc); 110 } 111 112 static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc) 113 { 114 return container_of(gsc, struct intel_gt, gsc); 115 } 116 117 void intel_gt_common_init_early(struct intel_gt *gt); 118 int intel_root_gt_init_early(struct drm_i915_private *i915); 119 int intel_gt_assign_ggtt(struct intel_gt *gt); 120 int intel_gt_init_mmio(struct intel_gt *gt); 121 int __must_check intel_gt_init_hw(struct intel_gt *gt); 122 int intel_gt_init(struct intel_gt *gt); 123 void intel_gt_driver_register(struct intel_gt *gt); 124 125 void intel_gt_driver_unregister(struct intel_gt *gt); 126 void intel_gt_driver_remove(struct intel_gt *gt); 127 void intel_gt_driver_release(struct intel_gt *gt); 128 void intel_gt_driver_late_release_all(struct drm_i915_private *i915); 129 130 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout); 131 132 void intel_gt_check_and_clear_faults(struct intel_gt *gt); 133 i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt); 134 void intel_gt_clear_error_registers(struct intel_gt *gt, 135 intel_engine_mask_t engine_mask); 136 137 void intel_gt_flush_ggtt_writes(struct intel_gt *gt); 138 void intel_gt_chipset_flush(struct intel_gt *gt); 139 140 static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt, 141 enum intel_gt_scratch_field field) 142 { 143 return i915_ggtt_offset(gt->scratch) + field; 144 } 145 146 static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt) 147 { 148 return test_bit(I915_WEDGED_ON_INIT, >->reset.flags) || 149 test_bit(I915_WEDGED_ON_FINI, >->reset.flags); 150 } 151 152 static inline bool intel_gt_is_wedged(const struct intel_gt *gt) 153 { 154 GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) && 155 !test_bit(I915_WEDGED, >->reset.flags)); 156 157 return unlikely(test_bit(I915_WEDGED, >->reset.flags)); 158 } 159 160 int intel_gt_probe_all(struct drm_i915_private *i915); 161 int intel_gt_tiles_init(struct drm_i915_private *i915); 162 void intel_gt_release_all(struct drm_i915_private *i915); 163 164 #define for_each_gt(gt__, i915__, id__) \ 165 for ((id__) = 0; \ 166 (id__) < I915_MAX_GT; \ 167 (id__)++) \ 168 for_each_if(((gt__) = (i915__)->gt[(id__)])) 169 170 /* Simple iterator over all initialised engines */ 171 #define for_each_engine(engine__, gt__, id__) \ 172 for ((id__) = 0; \ 173 (id__) < I915_NUM_ENGINES; \ 174 (id__)++) \ 175 for_each_if ((engine__) = (gt__)->engine[(id__)]) 176 177 /* Iterator over subset of engines selected by mask */ 178 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 179 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 180 (tmp__) ? \ 181 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 182 0;) 183 184 void intel_gt_info_print(const struct intel_gt_info *info, 185 struct drm_printer *p); 186 187 void intel_gt_watchdog_work(struct work_struct *work); 188 189 enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt, 190 struct drm_i915_gem_object *obj, 191 bool always_coherent); 192 193 void intel_gt_bind_context_set_ready(struct intel_gt *gt); 194 void intel_gt_bind_context_set_unready(struct intel_gt *gt); 195 bool intel_gt_is_bind_context_ready(struct intel_gt *gt); 196 #endif /* __INTEL_GT_H__ */ 197