1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "debugfs_gt.h" 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_gt.h" 10 #include "intel_gt_buffer_pool.h" 11 #include "intel_gt_clock_utils.h" 12 #include "intel_gt_pm.h" 13 #include "intel_gt_requests.h" 14 #include "intel_mocs.h" 15 #include "intel_rc6.h" 16 #include "intel_renderstate.h" 17 #include "intel_rps.h" 18 #include "intel_uncore.h" 19 #include "intel_pm.h" 20 #include "shmem_utils.h" 21 22 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) 23 { 24 gt->i915 = i915; 25 gt->uncore = &i915->uncore; 26 27 spin_lock_init(>->irq_lock); 28 29 INIT_LIST_HEAD(>->closed_vma); 30 spin_lock_init(>->closed_lock); 31 32 intel_gt_init_buffer_pool(gt); 33 intel_gt_init_reset(gt); 34 intel_gt_init_requests(gt); 35 intel_gt_init_timelines(gt); 36 intel_gt_pm_init_early(gt); 37 38 intel_rps_init_early(>->rps); 39 intel_uc_init_early(>->uc); 40 } 41 42 void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) 43 { 44 gt->ggtt = ggtt; 45 } 46 47 static void init_unused_ring(struct intel_gt *gt, u32 base) 48 { 49 struct intel_uncore *uncore = gt->uncore; 50 51 intel_uncore_write(uncore, RING_CTL(base), 0); 52 intel_uncore_write(uncore, RING_HEAD(base), 0); 53 intel_uncore_write(uncore, RING_TAIL(base), 0); 54 intel_uncore_write(uncore, RING_START(base), 0); 55 } 56 57 static void init_unused_rings(struct intel_gt *gt) 58 { 59 struct drm_i915_private *i915 = gt->i915; 60 61 if (IS_I830(i915)) { 62 init_unused_ring(gt, PRB1_BASE); 63 init_unused_ring(gt, SRB0_BASE); 64 init_unused_ring(gt, SRB1_BASE); 65 init_unused_ring(gt, SRB2_BASE); 66 init_unused_ring(gt, SRB3_BASE); 67 } else if (IS_GEN(i915, 2)) { 68 init_unused_ring(gt, SRB0_BASE); 69 init_unused_ring(gt, SRB1_BASE); 70 } else if (IS_GEN(i915, 3)) { 71 init_unused_ring(gt, PRB1_BASE); 72 init_unused_ring(gt, PRB2_BASE); 73 } 74 } 75 76 int intel_gt_init_hw(struct intel_gt *gt) 77 { 78 struct drm_i915_private *i915 = gt->i915; 79 struct intel_uncore *uncore = gt->uncore; 80 int ret; 81 82 gt->last_init_time = ktime_get(); 83 84 /* Double layer security blanket, see i915_gem_init() */ 85 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 86 87 if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9) 88 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf)); 89 90 if (IS_HASWELL(i915)) 91 intel_uncore_write(uncore, 92 MI_PREDICATE_RESULT_2, 93 IS_HSW_GT3(i915) ? 94 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); 95 96 /* Apply the GT workarounds... */ 97 intel_gt_apply_workarounds(gt); 98 /* ...and determine whether they are sticking. */ 99 intel_gt_verify_workarounds(gt, "init"); 100 101 intel_gt_init_swizzling(gt); 102 103 /* 104 * At least 830 can leave some of the unused rings 105 * "active" (ie. head != tail) after resume which 106 * will prevent c3 entry. Makes sure all unused rings 107 * are totally idle. 108 */ 109 init_unused_rings(gt); 110 111 ret = i915_ppgtt_init_hw(gt); 112 if (ret) { 113 DRM_ERROR("Enabling PPGTT failed (%d)\n", ret); 114 goto out; 115 } 116 117 /* We can't enable contexts until all firmware is loaded */ 118 ret = intel_uc_init_hw(>->uc); 119 if (ret) { 120 i915_probe_error(i915, "Enabling uc failed (%d)\n", ret); 121 goto out; 122 } 123 124 intel_mocs_init(gt); 125 126 out: 127 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 128 return ret; 129 } 130 131 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set) 132 { 133 intel_uncore_rmw(uncore, reg, 0, set); 134 } 135 136 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) 137 { 138 intel_uncore_rmw(uncore, reg, clr, 0); 139 } 140 141 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg) 142 { 143 intel_uncore_rmw(uncore, reg, 0, 0); 144 } 145 146 static void gen8_clear_engine_error_register(struct intel_engine_cs *engine) 147 { 148 GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0); 149 GEN6_RING_FAULT_REG_POSTING_READ(engine); 150 } 151 152 void 153 intel_gt_clear_error_registers(struct intel_gt *gt, 154 intel_engine_mask_t engine_mask) 155 { 156 struct drm_i915_private *i915 = gt->i915; 157 struct intel_uncore *uncore = gt->uncore; 158 u32 eir; 159 160 if (!IS_GEN(i915, 2)) 161 clear_register(uncore, PGTBL_ER); 162 163 if (INTEL_GEN(i915) < 4) 164 clear_register(uncore, IPEIR(RENDER_RING_BASE)); 165 else 166 clear_register(uncore, IPEIR_I965); 167 168 clear_register(uncore, EIR); 169 eir = intel_uncore_read(uncore, EIR); 170 if (eir) { 171 /* 172 * some errors might have become stuck, 173 * mask them. 174 */ 175 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); 176 rmw_set(uncore, EMR, eir); 177 intel_uncore_write(uncore, GEN2_IIR, 178 I915_MASTER_ERROR_INTERRUPT); 179 } 180 181 if (INTEL_GEN(i915) >= 12) { 182 rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID); 183 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG); 184 } else if (INTEL_GEN(i915) >= 8) { 185 rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID); 186 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG); 187 } else if (INTEL_GEN(i915) >= 6) { 188 struct intel_engine_cs *engine; 189 enum intel_engine_id id; 190 191 for_each_engine_masked(engine, gt, engine_mask, id) 192 gen8_clear_engine_error_register(engine); 193 } 194 } 195 196 static void gen6_check_faults(struct intel_gt *gt) 197 { 198 struct intel_engine_cs *engine; 199 enum intel_engine_id id; 200 u32 fault; 201 202 for_each_engine(engine, gt, id) { 203 fault = GEN6_RING_FAULT_REG_READ(engine); 204 if (fault & RING_FAULT_VALID) { 205 drm_dbg(&engine->i915->drm, "Unexpected fault\n" 206 "\tAddr: 0x%08lx\n" 207 "\tAddress space: %s\n" 208 "\tSource ID: %d\n" 209 "\tType: %d\n", 210 fault & PAGE_MASK, 211 fault & RING_FAULT_GTTSEL_MASK ? 212 "GGTT" : "PPGTT", 213 RING_FAULT_SRCID(fault), 214 RING_FAULT_FAULT_TYPE(fault)); 215 } 216 } 217 } 218 219 static void gen8_check_faults(struct intel_gt *gt) 220 { 221 struct intel_uncore *uncore = gt->uncore; 222 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg; 223 u32 fault; 224 225 if (INTEL_GEN(gt->i915) >= 12) { 226 fault_reg = GEN12_RING_FAULT_REG; 227 fault_data0_reg = GEN12_FAULT_TLB_DATA0; 228 fault_data1_reg = GEN12_FAULT_TLB_DATA1; 229 } else { 230 fault_reg = GEN8_RING_FAULT_REG; 231 fault_data0_reg = GEN8_FAULT_TLB_DATA0; 232 fault_data1_reg = GEN8_FAULT_TLB_DATA1; 233 } 234 235 fault = intel_uncore_read(uncore, fault_reg); 236 if (fault & RING_FAULT_VALID) { 237 u32 fault_data0, fault_data1; 238 u64 fault_addr; 239 240 fault_data0 = intel_uncore_read(uncore, fault_data0_reg); 241 fault_data1 = intel_uncore_read(uncore, fault_data1_reg); 242 243 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 244 ((u64)fault_data0 << 12); 245 246 drm_dbg(&uncore->i915->drm, "Unexpected fault\n" 247 "\tAddr: 0x%08x_%08x\n" 248 "\tAddress space: %s\n" 249 "\tEngine ID: %d\n" 250 "\tSource ID: %d\n" 251 "\tType: %d\n", 252 upper_32_bits(fault_addr), lower_32_bits(fault_addr), 253 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 254 GEN8_RING_FAULT_ENGINE_ID(fault), 255 RING_FAULT_SRCID(fault), 256 RING_FAULT_FAULT_TYPE(fault)); 257 } 258 } 259 260 void intel_gt_check_and_clear_faults(struct intel_gt *gt) 261 { 262 struct drm_i915_private *i915 = gt->i915; 263 264 /* From GEN8 onwards we only have one 'All Engine Fault Register' */ 265 if (INTEL_GEN(i915) >= 8) 266 gen8_check_faults(gt); 267 else if (INTEL_GEN(i915) >= 6) 268 gen6_check_faults(gt); 269 else 270 return; 271 272 intel_gt_clear_error_registers(gt, ALL_ENGINES); 273 } 274 275 void intel_gt_flush_ggtt_writes(struct intel_gt *gt) 276 { 277 struct intel_uncore *uncore = gt->uncore; 278 intel_wakeref_t wakeref; 279 280 /* 281 * No actual flushing is required for the GTT write domain for reads 282 * from the GTT domain. Writes to it "immediately" go to main memory 283 * as far as we know, so there's no chipset flush. It also doesn't 284 * land in the GPU render cache. 285 * 286 * However, we do have to enforce the order so that all writes through 287 * the GTT land before any writes to the device, such as updates to 288 * the GATT itself. 289 * 290 * We also have to wait a bit for the writes to land from the GTT. 291 * An uncached read (i.e. mmio) seems to be ideal for the round-trip 292 * timing. This issue has only been observed when switching quickly 293 * between GTT writes and CPU reads from inside the kernel on recent hw, 294 * and it appears to only affect discrete GTT blocks (i.e. on LLC 295 * system agents we cannot reproduce this behaviour, until Cannonlake 296 * that was!). 297 */ 298 299 wmb(); 300 301 if (INTEL_INFO(gt->i915)->has_coherent_ggtt) 302 return; 303 304 intel_gt_chipset_flush(gt); 305 306 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) { 307 unsigned long flags; 308 309 spin_lock_irqsave(&uncore->lock, flags); 310 intel_uncore_posting_read_fw(uncore, 311 RING_HEAD(RENDER_RING_BASE)); 312 spin_unlock_irqrestore(&uncore->lock, flags); 313 } 314 } 315 316 void intel_gt_chipset_flush(struct intel_gt *gt) 317 { 318 wmb(); 319 if (INTEL_GEN(gt->i915) < 6) 320 intel_gtt_chipset_flush(); 321 } 322 323 void intel_gt_driver_register(struct intel_gt *gt) 324 { 325 intel_rps_driver_register(>->rps); 326 327 debugfs_gt_register(gt); 328 } 329 330 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) 331 { 332 struct drm_i915_private *i915 = gt->i915; 333 struct drm_i915_gem_object *obj; 334 struct i915_vma *vma; 335 int ret; 336 337 obj = i915_gem_object_create_stolen(i915, size); 338 if (IS_ERR(obj)) 339 obj = i915_gem_object_create_internal(i915, size); 340 if (IS_ERR(obj)) { 341 DRM_ERROR("Failed to allocate scratch page\n"); 342 return PTR_ERR(obj); 343 } 344 345 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); 346 if (IS_ERR(vma)) { 347 ret = PTR_ERR(vma); 348 goto err_unref; 349 } 350 351 ret = i915_ggtt_pin(vma, 0, PIN_HIGH); 352 if (ret) 353 goto err_unref; 354 355 gt->scratch = i915_vma_make_unshrinkable(vma); 356 357 return 0; 358 359 err_unref: 360 i915_gem_object_put(obj); 361 return ret; 362 } 363 364 static void intel_gt_fini_scratch(struct intel_gt *gt) 365 { 366 i915_vma_unpin_and_release(>->scratch, 0); 367 } 368 369 static struct i915_address_space *kernel_vm(struct intel_gt *gt) 370 { 371 if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING) 372 return &i915_ppgtt_create(gt)->vm; 373 else 374 return i915_vm_get(>->ggtt->vm); 375 } 376 377 static int __engines_record_defaults(struct intel_gt *gt) 378 { 379 struct i915_request *requests[I915_NUM_ENGINES] = {}; 380 struct intel_engine_cs *engine; 381 enum intel_engine_id id; 382 int err = 0; 383 384 /* 385 * As we reset the gpu during very early sanitisation, the current 386 * register state on the GPU should reflect its defaults values. 387 * We load a context onto the hw (with restore-inhibit), then switch 388 * over to a second context to save that default register state. We 389 * can then prime every new context with that state so they all start 390 * from the same default HW values. 391 */ 392 393 for_each_engine(engine, gt, id) { 394 struct intel_renderstate so; 395 struct intel_context *ce; 396 struct i915_request *rq; 397 398 /* We must be able to switch to something! */ 399 GEM_BUG_ON(!engine->kernel_context); 400 401 err = intel_renderstate_init(&so, engine); 402 if (err) 403 goto out; 404 405 ce = intel_context_create(engine); 406 if (IS_ERR(ce)) { 407 err = PTR_ERR(ce); 408 goto out; 409 } 410 411 rq = intel_context_create_request(ce); 412 if (IS_ERR(rq)) { 413 err = PTR_ERR(rq); 414 intel_context_put(ce); 415 goto out; 416 } 417 418 err = intel_engine_emit_ctx_wa(rq); 419 if (err) 420 goto err_rq; 421 422 err = intel_renderstate_emit(&so, rq); 423 if (err) 424 goto err_rq; 425 426 err_rq: 427 requests[id] = i915_request_get(rq); 428 i915_request_add(rq); 429 intel_renderstate_fini(&so); 430 if (err) 431 goto out; 432 } 433 434 /* Flush the default context image to memory, and enable powersaving. */ 435 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) { 436 err = -EIO; 437 goto out; 438 } 439 440 for (id = 0; id < ARRAY_SIZE(requests); id++) { 441 struct i915_request *rq; 442 struct file *state; 443 444 rq = requests[id]; 445 if (!rq) 446 continue; 447 448 if (rq->fence.error) { 449 err = -EIO; 450 goto out; 451 } 452 453 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags)); 454 if (!rq->context->state) 455 continue; 456 457 /* Keep a copy of the state's backing pages; free the obj */ 458 state = shmem_create_from_object(rq->context->state->obj); 459 if (IS_ERR(state)) { 460 err = PTR_ERR(state); 461 goto out; 462 } 463 rq->engine->default_state = state; 464 } 465 466 out: 467 /* 468 * If we have to abandon now, we expect the engines to be idle 469 * and ready to be torn-down. The quickest way we can accomplish 470 * this is by declaring ourselves wedged. 471 */ 472 if (err) 473 intel_gt_set_wedged(gt); 474 475 for (id = 0; id < ARRAY_SIZE(requests); id++) { 476 struct intel_context *ce; 477 struct i915_request *rq; 478 479 rq = requests[id]; 480 if (!rq) 481 continue; 482 483 ce = rq->context; 484 i915_request_put(rq); 485 intel_context_put(ce); 486 } 487 return err; 488 } 489 490 static int __engines_verify_workarounds(struct intel_gt *gt) 491 { 492 struct intel_engine_cs *engine; 493 enum intel_engine_id id; 494 int err = 0; 495 496 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 497 return 0; 498 499 for_each_engine(engine, gt, id) { 500 if (intel_engine_verify_workarounds(engine, "load")) 501 err = -EIO; 502 } 503 504 /* Flush and restore the kernel context for safety */ 505 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) 506 err = -EIO; 507 508 return err; 509 } 510 511 static void __intel_gt_disable(struct intel_gt *gt) 512 { 513 intel_gt_set_wedged_on_init(gt); 514 515 intel_gt_suspend_prepare(gt); 516 intel_gt_suspend_late(gt); 517 518 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 519 } 520 521 int intel_gt_init(struct intel_gt *gt) 522 { 523 int err; 524 525 err = i915_inject_probe_error(gt->i915, -ENODEV); 526 if (err) 527 return err; 528 529 /* 530 * This is just a security blanket to placate dragons. 531 * On some systems, we very sporadically observe that the first TLBs 532 * used by the CS may be stale, despite us poking the TLB reset. If 533 * we hold the forcewake during initialisation these problems 534 * just magically go away. 535 */ 536 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); 537 538 intel_gt_init_clock_frequency(gt); 539 540 err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K); 541 if (err) 542 goto out_fw; 543 544 intel_gt_pm_init(gt); 545 546 gt->vm = kernel_vm(gt); 547 if (!gt->vm) { 548 err = -ENOMEM; 549 goto err_pm; 550 } 551 552 err = intel_engines_init(gt); 553 if (err) 554 goto err_engines; 555 556 err = intel_uc_init(>->uc); 557 if (err) 558 goto err_engines; 559 560 err = intel_gt_resume(gt); 561 if (err) 562 goto err_uc_init; 563 564 err = __engines_record_defaults(gt); 565 if (err) 566 goto err_gt; 567 568 err = __engines_verify_workarounds(gt); 569 if (err) 570 goto err_gt; 571 572 err = i915_inject_probe_error(gt->i915, -EIO); 573 if (err) 574 goto err_gt; 575 576 goto out_fw; 577 err_gt: 578 __intel_gt_disable(gt); 579 intel_uc_fini_hw(>->uc); 580 err_uc_init: 581 intel_uc_fini(>->uc); 582 err_engines: 583 intel_engines_release(gt); 584 i915_vm_put(fetch_and_zero(>->vm)); 585 err_pm: 586 intel_gt_pm_fini(gt); 587 intel_gt_fini_scratch(gt); 588 out_fw: 589 if (err) 590 intel_gt_set_wedged_on_init(gt); 591 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); 592 return err; 593 } 594 595 void intel_gt_driver_remove(struct intel_gt *gt) 596 { 597 __intel_gt_disable(gt); 598 599 intel_uc_driver_remove(>->uc); 600 601 intel_engines_release(gt); 602 } 603 604 void intel_gt_driver_unregister(struct intel_gt *gt) 605 { 606 intel_rps_driver_unregister(>->rps); 607 608 /* 609 * Upon unregistering the device to prevent any new users, cancel 610 * all in-flight requests so that we can quickly unbind the active 611 * resources. 612 */ 613 intel_gt_set_wedged(gt); 614 } 615 616 void intel_gt_driver_release(struct intel_gt *gt) 617 { 618 struct i915_address_space *vm; 619 620 vm = fetch_and_zero(>->vm); 621 if (vm) /* FIXME being called twice on error paths :( */ 622 i915_vm_put(vm); 623 624 intel_gt_pm_fini(gt); 625 intel_gt_fini_scratch(gt); 626 intel_gt_fini_buffer_pool(gt); 627 } 628 629 void intel_gt_driver_late_release(struct intel_gt *gt) 630 { 631 /* We need to wait for inflight RCU frees to release their grip */ 632 rcu_barrier(); 633 634 intel_uc_driver_late_release(>->uc); 635 intel_gt_fini_requests(gt); 636 intel_gt_fini_reset(gt); 637 intel_gt_fini_timelines(gt); 638 intel_engines_free(gt); 639 } 640