1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <drm/drm_managed.h> 7 #include <drm/intel-gtt.h> 8 9 #include "gem/i915_gem_internal.h" 10 #include "gem/i915_gem_lmem.h" 11 12 #include "i915_drv.h" 13 #include "i915_perf_oa_regs.h" 14 #include "i915_reg.h" 15 #include "intel_context.h" 16 #include "intel_engine_pm.h" 17 #include "intel_engine_regs.h" 18 #include "intel_ggtt_gmch.h" 19 #include "intel_gt.h" 20 #include "intel_gt_buffer_pool.h" 21 #include "intel_gt_clock_utils.h" 22 #include "intel_gt_debugfs.h" 23 #include "intel_gt_mcr.h" 24 #include "intel_gt_pm.h" 25 #include "intel_gt_print.h" 26 #include "intel_gt_regs.h" 27 #include "intel_gt_requests.h" 28 #include "intel_migrate.h" 29 #include "intel_mocs.h" 30 #include "intel_pci_config.h" 31 #include "intel_rc6.h" 32 #include "intel_renderstate.h" 33 #include "intel_rps.h" 34 #include "intel_sa_media.h" 35 #include "intel_gt_sysfs.h" 36 #include "intel_uncore.h" 37 #include "shmem_utils.h" 38 39 void intel_gt_common_init_early(struct intel_gt *gt) 40 { 41 spin_lock_init(gt->irq_lock); 42 43 INIT_LIST_HEAD(>->closed_vma); 44 spin_lock_init(>->closed_lock); 45 46 init_llist_head(>->watchdog.list); 47 INIT_WORK(>->watchdog.work, intel_gt_watchdog_work); 48 49 intel_gt_init_buffer_pool(gt); 50 intel_gt_init_reset(gt); 51 intel_gt_init_requests(gt); 52 intel_gt_init_timelines(gt); 53 mutex_init(>->tlb.invalidate_lock); 54 seqcount_mutex_init(>->tlb.seqno, >->tlb.invalidate_lock); 55 intel_gt_pm_init_early(gt); 56 57 intel_wopcm_init_early(>->wopcm); 58 intel_uc_init_early(>->uc); 59 intel_rps_init_early(>->rps); 60 } 61 62 /* Preliminary initialization of Tile 0 */ 63 int intel_root_gt_init_early(struct drm_i915_private *i915) 64 { 65 struct intel_gt *gt = to_gt(i915); 66 67 gt->i915 = i915; 68 gt->uncore = &i915->uncore; 69 gt->irq_lock = drmm_kzalloc(&i915->drm, sizeof(*gt->irq_lock), GFP_KERNEL); 70 if (!gt->irq_lock) 71 return -ENOMEM; 72 73 intel_gt_common_init_early(gt); 74 75 return 0; 76 } 77 78 static int intel_gt_probe_lmem(struct intel_gt *gt) 79 { 80 struct drm_i915_private *i915 = gt->i915; 81 unsigned int instance = gt->info.id; 82 int id = INTEL_REGION_LMEM_0 + instance; 83 struct intel_memory_region *mem; 84 int err; 85 86 mem = intel_gt_setup_lmem(gt); 87 if (IS_ERR(mem)) { 88 err = PTR_ERR(mem); 89 if (err == -ENODEV) 90 return 0; 91 92 gt_err(gt, "Failed to setup region(%d) type=%d\n", 93 err, INTEL_MEMORY_LOCAL); 94 return err; 95 } 96 97 mem->id = id; 98 mem->instance = instance; 99 100 intel_memory_region_set_name(mem, "local%u", mem->instance); 101 102 GEM_BUG_ON(!HAS_REGION(i915, id)); 103 GEM_BUG_ON(i915->mm.regions[id]); 104 i915->mm.regions[id] = mem; 105 106 return 0; 107 } 108 109 int intel_gt_assign_ggtt(struct intel_gt *gt) 110 { 111 /* Media GT shares primary GT's GGTT */ 112 if (gt->type == GT_MEDIA) { 113 gt->ggtt = to_gt(gt->i915)->ggtt; 114 } else { 115 gt->ggtt = i915_ggtt_create(gt->i915); 116 if (IS_ERR(gt->ggtt)) 117 return PTR_ERR(gt->ggtt); 118 } 119 120 list_add_tail(>->ggtt_link, >->ggtt->gt_list); 121 122 return 0; 123 } 124 125 int intel_gt_init_mmio(struct intel_gt *gt) 126 { 127 intel_gt_init_clock_frequency(gt); 128 129 intel_uc_init_mmio(>->uc); 130 intel_sseu_info_init(gt); 131 intel_gt_mcr_init(gt); 132 133 return intel_engines_init_mmio(gt); 134 } 135 136 static void init_unused_ring(struct intel_gt *gt, u32 base) 137 { 138 struct intel_uncore *uncore = gt->uncore; 139 140 intel_uncore_write(uncore, RING_CTL(base), 0); 141 intel_uncore_write(uncore, RING_HEAD(base), 0); 142 intel_uncore_write(uncore, RING_TAIL(base), 0); 143 intel_uncore_write(uncore, RING_START(base), 0); 144 } 145 146 static void init_unused_rings(struct intel_gt *gt) 147 { 148 struct drm_i915_private *i915 = gt->i915; 149 150 if (IS_I830(i915)) { 151 init_unused_ring(gt, PRB1_BASE); 152 init_unused_ring(gt, SRB0_BASE); 153 init_unused_ring(gt, SRB1_BASE); 154 init_unused_ring(gt, SRB2_BASE); 155 init_unused_ring(gt, SRB3_BASE); 156 } else if (GRAPHICS_VER(i915) == 2) { 157 init_unused_ring(gt, SRB0_BASE); 158 init_unused_ring(gt, SRB1_BASE); 159 } else if (GRAPHICS_VER(i915) == 3) { 160 init_unused_ring(gt, PRB1_BASE); 161 init_unused_ring(gt, PRB2_BASE); 162 } 163 } 164 165 int intel_gt_init_hw(struct intel_gt *gt) 166 { 167 struct drm_i915_private *i915 = gt->i915; 168 struct intel_uncore *uncore = gt->uncore; 169 int ret; 170 171 gt->last_init_time = ktime_get(); 172 173 /* Double layer security blanket, see i915_gem_init() */ 174 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 175 176 if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9) 177 intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf)); 178 179 if (IS_HASWELL(i915)) 180 intel_uncore_write(uncore, 181 HSW_MI_PREDICATE_RESULT_2, 182 IS_HSW_GT3(i915) ? 183 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); 184 185 /* Apply the GT workarounds... */ 186 intel_gt_apply_workarounds(gt); 187 /* ...and determine whether they are sticking. */ 188 intel_gt_verify_workarounds(gt, "init"); 189 190 intel_gt_init_swizzling(gt); 191 192 /* 193 * At least 830 can leave some of the unused rings 194 * "active" (ie. head != tail) after resume which 195 * will prevent c3 entry. Makes sure all unused rings 196 * are totally idle. 197 */ 198 init_unused_rings(gt); 199 200 ret = i915_ppgtt_init_hw(gt); 201 if (ret) { 202 gt_err(gt, "Enabling PPGTT failed (%d)\n", ret); 203 goto out; 204 } 205 206 /* We can't enable contexts until all firmware is loaded */ 207 ret = intel_uc_init_hw(>->uc); 208 if (ret) { 209 gt_probe_error(gt, "Enabling uc failed (%d)\n", ret); 210 goto out; 211 } 212 213 intel_mocs_init(gt); 214 215 out: 216 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 217 return ret; 218 } 219 220 static void gen6_clear_engine_error_register(struct intel_engine_cs *engine) 221 { 222 GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0); 223 GEN6_RING_FAULT_REG_POSTING_READ(engine); 224 } 225 226 i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt) 227 { 228 /* GT0_PERF_LIMIT_REASONS is available only for Gen11+ */ 229 if (GRAPHICS_VER(gt->i915) < 11) 230 return INVALID_MMIO_REG; 231 232 return gt->type == GT_MEDIA ? 233 MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS; 234 } 235 236 void 237 intel_gt_clear_error_registers(struct intel_gt *gt, 238 intel_engine_mask_t engine_mask) 239 { 240 struct drm_i915_private *i915 = gt->i915; 241 struct intel_uncore *uncore = gt->uncore; 242 u32 eir; 243 244 if (GRAPHICS_VER(i915) != 2) 245 intel_uncore_write(uncore, PGTBL_ER, 0); 246 247 if (GRAPHICS_VER(i915) < 4) 248 intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0); 249 else 250 intel_uncore_write(uncore, IPEIR_I965, 0); 251 252 intel_uncore_write(uncore, EIR, 0); 253 eir = intel_uncore_read(uncore, EIR); 254 if (eir) { 255 /* 256 * some errors might have become stuck, 257 * mask them. 258 */ 259 gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir); 260 intel_uncore_rmw(uncore, EMR, 0, eir); 261 intel_uncore_write(uncore, GEN2_IIR, 262 I915_MASTER_ERROR_INTERRUPT); 263 } 264 265 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 266 intel_gt_mcr_multicast_rmw(gt, XEHP_RING_FAULT_REG, 267 RING_FAULT_VALID, 0); 268 intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG); 269 } else if (GRAPHICS_VER(i915) >= 12) { 270 intel_uncore_rmw(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID, 0); 271 intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG); 272 } else if (GRAPHICS_VER(i915) >= 8) { 273 intel_uncore_rmw(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID, 0); 274 intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG); 275 } else if (GRAPHICS_VER(i915) >= 6) { 276 struct intel_engine_cs *engine; 277 enum intel_engine_id id; 278 279 for_each_engine_masked(engine, gt, engine_mask, id) 280 gen6_clear_engine_error_register(engine); 281 } 282 } 283 284 static void gen6_check_faults(struct intel_gt *gt) 285 { 286 struct intel_engine_cs *engine; 287 enum intel_engine_id id; 288 u32 fault; 289 290 for_each_engine(engine, gt, id) { 291 fault = GEN6_RING_FAULT_REG_READ(engine); 292 if (fault & RING_FAULT_VALID) { 293 gt_dbg(gt, "Unexpected fault\n" 294 "\tAddr: 0x%08lx\n" 295 "\tAddress space: %s\n" 296 "\tSource ID: %d\n" 297 "\tType: %d\n", 298 fault & PAGE_MASK, 299 fault & RING_FAULT_GTTSEL_MASK ? 300 "GGTT" : "PPGTT", 301 RING_FAULT_SRCID(fault), 302 RING_FAULT_FAULT_TYPE(fault)); 303 } 304 } 305 } 306 307 static void xehp_check_faults(struct intel_gt *gt) 308 { 309 u32 fault; 310 311 /* 312 * Although the fault register now lives in an MCR register range, 313 * the GAM registers are special and we only truly need to read 314 * the "primary" GAM instance rather than handling each instance 315 * individually. intel_gt_mcr_read_any() will automatically steer 316 * toward the primary instance. 317 */ 318 fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG); 319 if (fault & RING_FAULT_VALID) { 320 u32 fault_data0, fault_data1; 321 u64 fault_addr; 322 323 fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0); 324 fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1); 325 326 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 327 ((u64)fault_data0 << 12); 328 329 gt_dbg(gt, "Unexpected fault\n" 330 "\tAddr: 0x%08x_%08x\n" 331 "\tAddress space: %s\n" 332 "\tEngine ID: %d\n" 333 "\tSource ID: %d\n" 334 "\tType: %d\n", 335 upper_32_bits(fault_addr), lower_32_bits(fault_addr), 336 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 337 GEN8_RING_FAULT_ENGINE_ID(fault), 338 RING_FAULT_SRCID(fault), 339 RING_FAULT_FAULT_TYPE(fault)); 340 } 341 } 342 343 static void gen8_check_faults(struct intel_gt *gt) 344 { 345 struct intel_uncore *uncore = gt->uncore; 346 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg; 347 u32 fault; 348 349 if (GRAPHICS_VER(gt->i915) >= 12) { 350 fault_reg = GEN12_RING_FAULT_REG; 351 fault_data0_reg = GEN12_FAULT_TLB_DATA0; 352 fault_data1_reg = GEN12_FAULT_TLB_DATA1; 353 } else { 354 fault_reg = GEN8_RING_FAULT_REG; 355 fault_data0_reg = GEN8_FAULT_TLB_DATA0; 356 fault_data1_reg = GEN8_FAULT_TLB_DATA1; 357 } 358 359 fault = intel_uncore_read(uncore, fault_reg); 360 if (fault & RING_FAULT_VALID) { 361 u32 fault_data0, fault_data1; 362 u64 fault_addr; 363 364 fault_data0 = intel_uncore_read(uncore, fault_data0_reg); 365 fault_data1 = intel_uncore_read(uncore, fault_data1_reg); 366 367 fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 368 ((u64)fault_data0 << 12); 369 370 gt_dbg(gt, "Unexpected fault\n" 371 "\tAddr: 0x%08x_%08x\n" 372 "\tAddress space: %s\n" 373 "\tEngine ID: %d\n" 374 "\tSource ID: %d\n" 375 "\tType: %d\n", 376 upper_32_bits(fault_addr), lower_32_bits(fault_addr), 377 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 378 GEN8_RING_FAULT_ENGINE_ID(fault), 379 RING_FAULT_SRCID(fault), 380 RING_FAULT_FAULT_TYPE(fault)); 381 } 382 } 383 384 void intel_gt_check_and_clear_faults(struct intel_gt *gt) 385 { 386 struct drm_i915_private *i915 = gt->i915; 387 388 /* From GEN8 onwards we only have one 'All Engine Fault Register' */ 389 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 390 xehp_check_faults(gt); 391 else if (GRAPHICS_VER(i915) >= 8) 392 gen8_check_faults(gt); 393 else if (GRAPHICS_VER(i915) >= 6) 394 gen6_check_faults(gt); 395 else 396 return; 397 398 intel_gt_clear_error_registers(gt, ALL_ENGINES); 399 } 400 401 void intel_gt_flush_ggtt_writes(struct intel_gt *gt) 402 { 403 struct intel_uncore *uncore = gt->uncore; 404 intel_wakeref_t wakeref; 405 406 /* 407 * No actual flushing is required for the GTT write domain for reads 408 * from the GTT domain. Writes to it "immediately" go to main memory 409 * as far as we know, so there's no chipset flush. It also doesn't 410 * land in the GPU render cache. 411 * 412 * However, we do have to enforce the order so that all writes through 413 * the GTT land before any writes to the device, such as updates to 414 * the GATT itself. 415 * 416 * We also have to wait a bit for the writes to land from the GTT. 417 * An uncached read (i.e. mmio) seems to be ideal for the round-trip 418 * timing. This issue has only been observed when switching quickly 419 * between GTT writes and CPU reads from inside the kernel on recent hw, 420 * and it appears to only affect discrete GTT blocks (i.e. on LLC 421 * system agents we cannot reproduce this behaviour, until Cannonlake 422 * that was!). 423 */ 424 425 wmb(); 426 427 if (INTEL_INFO(gt->i915)->has_coherent_ggtt) 428 return; 429 430 intel_gt_chipset_flush(gt); 431 432 with_intel_runtime_pm_if_in_use(uncore->rpm, wakeref) { 433 unsigned long flags; 434 435 spin_lock_irqsave(&uncore->lock, flags); 436 intel_uncore_posting_read_fw(uncore, 437 RING_HEAD(RENDER_RING_BASE)); 438 spin_unlock_irqrestore(&uncore->lock, flags); 439 } 440 } 441 442 void intel_gt_chipset_flush(struct intel_gt *gt) 443 { 444 wmb(); 445 if (GRAPHICS_VER(gt->i915) < 6) 446 intel_ggtt_gmch_flush(); 447 } 448 449 void intel_gt_driver_register(struct intel_gt *gt) 450 { 451 intel_gsc_init(>->gsc, gt->i915); 452 453 intel_rps_driver_register(>->rps); 454 455 intel_gt_debugfs_register(gt); 456 intel_gt_sysfs_register(gt); 457 } 458 459 static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) 460 { 461 struct drm_i915_private *i915 = gt->i915; 462 struct drm_i915_gem_object *obj; 463 struct i915_vma *vma; 464 int ret; 465 466 obj = i915_gem_object_create_lmem(i915, size, 467 I915_BO_ALLOC_VOLATILE | 468 I915_BO_ALLOC_GPU_ONLY); 469 if (IS_ERR(obj)) 470 obj = i915_gem_object_create_stolen(i915, size); 471 if (IS_ERR(obj)) 472 obj = i915_gem_object_create_internal(i915, size); 473 if (IS_ERR(obj)) { 474 gt_err(gt, "Failed to allocate scratch page\n"); 475 return PTR_ERR(obj); 476 } 477 478 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); 479 if (IS_ERR(vma)) { 480 ret = PTR_ERR(vma); 481 goto err_unref; 482 } 483 484 ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); 485 if (ret) 486 goto err_unref; 487 488 gt->scratch = i915_vma_make_unshrinkable(vma); 489 490 return 0; 491 492 err_unref: 493 i915_gem_object_put(obj); 494 return ret; 495 } 496 497 static void intel_gt_fini_scratch(struct intel_gt *gt) 498 { 499 i915_vma_unpin_and_release(>->scratch, 0); 500 } 501 502 static struct i915_address_space *kernel_vm(struct intel_gt *gt) 503 { 504 if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING) 505 return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm; 506 else 507 return i915_vm_get(>->ggtt->vm); 508 } 509 510 static int __engines_record_defaults(struct intel_gt *gt) 511 { 512 struct i915_request *requests[I915_NUM_ENGINES] = {}; 513 struct intel_engine_cs *engine; 514 enum intel_engine_id id; 515 int err = 0; 516 517 /* 518 * As we reset the gpu during very early sanitisation, the current 519 * register state on the GPU should reflect its defaults values. 520 * We load a context onto the hw (with restore-inhibit), then switch 521 * over to a second context to save that default register state. We 522 * can then prime every new context with that state so they all start 523 * from the same default HW values. 524 */ 525 526 for_each_engine(engine, gt, id) { 527 struct intel_renderstate so; 528 struct intel_context *ce; 529 struct i915_request *rq; 530 531 /* We must be able to switch to something! */ 532 GEM_BUG_ON(!engine->kernel_context); 533 534 ce = intel_context_create(engine); 535 if (IS_ERR(ce)) { 536 err = PTR_ERR(ce); 537 goto out; 538 } 539 540 err = intel_renderstate_init(&so, ce); 541 if (err) 542 goto err; 543 544 rq = i915_request_create(ce); 545 if (IS_ERR(rq)) { 546 err = PTR_ERR(rq); 547 goto err_fini; 548 } 549 550 err = intel_engine_emit_ctx_wa(rq); 551 if (err) 552 goto err_rq; 553 554 err = intel_renderstate_emit(&so, rq); 555 if (err) 556 goto err_rq; 557 558 err_rq: 559 requests[id] = i915_request_get(rq); 560 i915_request_add(rq); 561 err_fini: 562 intel_renderstate_fini(&so, ce); 563 err: 564 if (err) { 565 intel_context_put(ce); 566 goto out; 567 } 568 } 569 570 /* Flush the default context image to memory, and enable powersaving. */ 571 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) { 572 err = -EIO; 573 goto out; 574 } 575 576 for (id = 0; id < ARRAY_SIZE(requests); id++) { 577 struct i915_request *rq; 578 struct file *state; 579 580 rq = requests[id]; 581 if (!rq) 582 continue; 583 584 if (rq->fence.error) { 585 err = -EIO; 586 goto out; 587 } 588 589 GEM_BUG_ON(!test_bit(CONTEXT_ALLOC_BIT, &rq->context->flags)); 590 if (!rq->context->state) 591 continue; 592 593 /* Keep a copy of the state's backing pages; free the obj */ 594 state = shmem_create_from_object(rq->context->state->obj); 595 if (IS_ERR(state)) { 596 err = PTR_ERR(state); 597 goto out; 598 } 599 rq->engine->default_state = state; 600 } 601 602 out: 603 /* 604 * If we have to abandon now, we expect the engines to be idle 605 * and ready to be torn-down. The quickest way we can accomplish 606 * this is by declaring ourselves wedged. 607 */ 608 if (err) 609 intel_gt_set_wedged(gt); 610 611 for (id = 0; id < ARRAY_SIZE(requests); id++) { 612 struct intel_context *ce; 613 struct i915_request *rq; 614 615 rq = requests[id]; 616 if (!rq) 617 continue; 618 619 ce = rq->context; 620 i915_request_put(rq); 621 intel_context_put(ce); 622 } 623 return err; 624 } 625 626 static int __engines_verify_workarounds(struct intel_gt *gt) 627 { 628 struct intel_engine_cs *engine; 629 enum intel_engine_id id; 630 int err = 0; 631 632 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 633 return 0; 634 635 for_each_engine(engine, gt, id) { 636 if (intel_engine_verify_workarounds(engine, "load")) 637 err = -EIO; 638 } 639 640 /* Flush and restore the kernel context for safety */ 641 if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) 642 err = -EIO; 643 644 return err; 645 } 646 647 static void __intel_gt_disable(struct intel_gt *gt) 648 { 649 intel_gt_set_wedged_on_fini(gt); 650 651 intel_gt_suspend_prepare(gt); 652 intel_gt_suspend_late(gt); 653 654 GEM_BUG_ON(intel_gt_pm_is_awake(gt)); 655 } 656 657 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout) 658 { 659 long remaining_timeout; 660 661 /* If the device is asleep, we have no requests outstanding */ 662 if (!intel_gt_pm_is_awake(gt)) 663 return 0; 664 665 while ((timeout = intel_gt_retire_requests_timeout(gt, timeout, 666 &remaining_timeout)) > 0) { 667 cond_resched(); 668 if (signal_pending(current)) 669 return -EINTR; 670 } 671 672 if (timeout) 673 return timeout; 674 675 if (remaining_timeout < 0) 676 remaining_timeout = 0; 677 678 return intel_uc_wait_for_idle(>->uc, remaining_timeout); 679 } 680 681 int intel_gt_init(struct intel_gt *gt) 682 { 683 int err; 684 685 err = i915_inject_probe_error(gt->i915, -ENODEV); 686 if (err) 687 return err; 688 689 intel_gt_init_workarounds(gt); 690 691 /* 692 * This is just a security blanket to placate dragons. 693 * On some systems, we very sporadically observe that the first TLBs 694 * used by the CS may be stale, despite us poking the TLB reset. If 695 * we hold the forcewake during initialisation these problems 696 * just magically go away. 697 */ 698 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); 699 700 err = intel_gt_init_scratch(gt, 701 GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K); 702 if (err) 703 goto out_fw; 704 705 intel_gt_pm_init(gt); 706 707 gt->vm = kernel_vm(gt); 708 if (!gt->vm) { 709 err = -ENOMEM; 710 goto err_pm; 711 } 712 713 intel_set_mocs_index(gt); 714 715 err = intel_engines_init(gt); 716 if (err) 717 goto err_engines; 718 719 err = intel_uc_init(>->uc); 720 if (err) 721 goto err_engines; 722 723 err = intel_gt_resume(gt); 724 if (err) 725 goto err_uc_init; 726 727 err = intel_gt_init_hwconfig(gt); 728 if (err) 729 gt_err(gt, "Failed to retrieve hwconfig table: %pe\n", ERR_PTR(err)); 730 731 err = __engines_record_defaults(gt); 732 if (err) 733 goto err_gt; 734 735 err = __engines_verify_workarounds(gt); 736 if (err) 737 goto err_gt; 738 739 intel_uc_init_late(>->uc); 740 741 err = i915_inject_probe_error(gt->i915, -EIO); 742 if (err) 743 goto err_gt; 744 745 intel_migrate_init(>->migrate, gt); 746 747 goto out_fw; 748 err_gt: 749 __intel_gt_disable(gt); 750 intel_uc_fini_hw(>->uc); 751 err_uc_init: 752 intel_uc_fini(>->uc); 753 err_engines: 754 intel_engines_release(gt); 755 i915_vm_put(fetch_and_zero(>->vm)); 756 err_pm: 757 intel_gt_pm_fini(gt); 758 intel_gt_fini_scratch(gt); 759 out_fw: 760 if (err) 761 intel_gt_set_wedged_on_init(gt); 762 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); 763 return err; 764 } 765 766 void intel_gt_driver_remove(struct intel_gt *gt) 767 { 768 __intel_gt_disable(gt); 769 770 intel_migrate_fini(>->migrate); 771 intel_uc_driver_remove(>->uc); 772 773 intel_engines_release(gt); 774 775 intel_gt_flush_buffer_pool(gt); 776 } 777 778 void intel_gt_driver_unregister(struct intel_gt *gt) 779 { 780 intel_wakeref_t wakeref; 781 782 intel_gt_sysfs_unregister(gt); 783 intel_rps_driver_unregister(>->rps); 784 intel_gsc_fini(>->gsc); 785 786 /* 787 * Upon unregistering the device to prevent any new users, cancel 788 * all in-flight requests so that we can quickly unbind the active 789 * resources. 790 */ 791 intel_gt_set_wedged_on_fini(gt); 792 793 /* Scrub all HW state upon release */ 794 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 795 __intel_gt_reset(gt, ALL_ENGINES); 796 } 797 798 void intel_gt_driver_release(struct intel_gt *gt) 799 { 800 struct i915_address_space *vm; 801 802 vm = fetch_and_zero(>->vm); 803 if (vm) /* FIXME being called twice on error paths :( */ 804 i915_vm_put(vm); 805 806 intel_wa_list_free(>->wa_list); 807 intel_gt_pm_fini(gt); 808 intel_gt_fini_scratch(gt); 809 intel_gt_fini_buffer_pool(gt); 810 intel_gt_fini_hwconfig(gt); 811 } 812 813 void intel_gt_driver_late_release_all(struct drm_i915_private *i915) 814 { 815 struct intel_gt *gt; 816 unsigned int id; 817 818 /* We need to wait for inflight RCU frees to release their grip */ 819 rcu_barrier(); 820 821 for_each_gt(gt, i915, id) { 822 intel_uc_driver_late_release(>->uc); 823 intel_gt_fini_requests(gt); 824 intel_gt_fini_reset(gt); 825 intel_gt_fini_timelines(gt); 826 mutex_destroy(>->tlb.invalidate_lock); 827 intel_engines_free(gt); 828 } 829 } 830 831 static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr) 832 { 833 int ret; 834 835 if (!gt_is_root(gt)) { 836 struct intel_uncore *uncore; 837 spinlock_t *irq_lock; 838 839 uncore = drmm_kzalloc(>->i915->drm, sizeof(*uncore), GFP_KERNEL); 840 if (!uncore) 841 return -ENOMEM; 842 843 irq_lock = drmm_kzalloc(>->i915->drm, sizeof(*irq_lock), GFP_KERNEL); 844 if (!irq_lock) 845 return -ENOMEM; 846 847 gt->uncore = uncore; 848 gt->irq_lock = irq_lock; 849 850 intel_gt_common_init_early(gt); 851 } 852 853 intel_uncore_init_early(gt->uncore, gt); 854 855 ret = intel_uncore_setup_mmio(gt->uncore, phys_addr); 856 if (ret) 857 return ret; 858 859 gt->phys_addr = phys_addr; 860 861 return 0; 862 } 863 864 int intel_gt_probe_all(struct drm_i915_private *i915) 865 { 866 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 867 struct intel_gt *gt = &i915->gt0; 868 const struct intel_gt_definition *gtdef; 869 phys_addr_t phys_addr; 870 unsigned int mmio_bar; 871 unsigned int i; 872 int ret; 873 874 mmio_bar = intel_mmio_bar(GRAPHICS_VER(i915)); 875 phys_addr = pci_resource_start(pdev, mmio_bar); 876 877 /* 878 * We always have at least one primary GT on any device 879 * and it has been already initialized early during probe 880 * in i915_driver_probe() 881 */ 882 gt->i915 = i915; 883 gt->name = "Primary GT"; 884 gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask; 885 886 gt_dbg(gt, "Setting up %s\n", gt->name); 887 ret = intel_gt_tile_setup(gt, phys_addr); 888 if (ret) 889 return ret; 890 891 i915->gt[0] = gt; 892 893 if (!HAS_EXTRA_GT_LIST(i915)) 894 return 0; 895 896 for (i = 1, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]; 897 gtdef->name != NULL; 898 i++, gtdef = &INTEL_INFO(i915)->extra_gt_list[i - 1]) { 899 gt = drmm_kzalloc(&i915->drm, sizeof(*gt), GFP_KERNEL); 900 if (!gt) { 901 ret = -ENOMEM; 902 goto err; 903 } 904 905 gt->i915 = i915; 906 gt->name = gtdef->name; 907 gt->type = gtdef->type; 908 gt->info.engine_mask = gtdef->engine_mask; 909 gt->info.id = i; 910 911 gt_dbg(gt, "Setting up %s\n", gt->name); 912 if (GEM_WARN_ON(range_overflows_t(resource_size_t, 913 gtdef->mapping_base, 914 SZ_16M, 915 pci_resource_len(pdev, mmio_bar)))) { 916 ret = -ENODEV; 917 goto err; 918 } 919 920 switch (gtdef->type) { 921 case GT_TILE: 922 ret = intel_gt_tile_setup(gt, phys_addr + gtdef->mapping_base); 923 break; 924 925 case GT_MEDIA: 926 ret = intel_sa_mediagt_setup(gt, phys_addr + gtdef->mapping_base, 927 gtdef->gsi_offset); 928 break; 929 930 case GT_PRIMARY: 931 /* Primary GT should not appear in extra GT list */ 932 default: 933 MISSING_CASE(gtdef->type); 934 ret = -ENODEV; 935 } 936 937 if (ret) 938 goto err; 939 940 i915->gt[i] = gt; 941 } 942 943 return 0; 944 945 err: 946 i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name, ret); 947 intel_gt_release_all(i915); 948 949 return ret; 950 } 951 952 int intel_gt_tiles_init(struct drm_i915_private *i915) 953 { 954 struct intel_gt *gt; 955 unsigned int id; 956 int ret; 957 958 for_each_gt(gt, i915, id) { 959 ret = intel_gt_probe_lmem(gt); 960 if (ret) 961 return ret; 962 } 963 964 return 0; 965 } 966 967 void intel_gt_release_all(struct drm_i915_private *i915) 968 { 969 struct intel_gt *gt; 970 unsigned int id; 971 972 for_each_gt(gt, i915, id) 973 i915->gt[id] = NULL; 974 } 975 976 void intel_gt_info_print(const struct intel_gt_info *info, 977 struct drm_printer *p) 978 { 979 drm_printf(p, "available engines: %x\n", info->engine_mask); 980 981 intel_sseu_dump(&info->sseu, p); 982 } 983 984 struct reg_and_bit { 985 union { 986 i915_reg_t reg; 987 i915_mcr_reg_t mcr_reg; 988 }; 989 u32 bit; 990 }; 991 992 static struct reg_and_bit 993 get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, 994 const i915_reg_t *regs, const unsigned int num) 995 { 996 const unsigned int class = engine->class; 997 struct reg_and_bit rb = { }; 998 999 if (gt_WARN_ON_ONCE(engine->gt, class >= num || !regs[class].reg)) 1000 return rb; 1001 1002 rb.reg = regs[class]; 1003 if (gen8 && class == VIDEO_DECODE_CLASS) 1004 rb.reg.reg += 4 * engine->instance; /* GEN8_M2TCR */ 1005 else 1006 rb.bit = engine->instance; 1007 1008 rb.bit = BIT(rb.bit); 1009 1010 return rb; 1011 } 1012 1013 /* 1014 * HW architecture suggest typical invalidation time at 40us, 1015 * with pessimistic cases up to 100us and a recommendation to 1016 * cap at 1ms. We go a bit higher just in case. 1017 */ 1018 #define TLB_INVAL_TIMEOUT_US 100 1019 #define TLB_INVAL_TIMEOUT_MS 4 1020 1021 /* 1022 * On Xe_HP the TLB invalidation registers are located at the same MMIO offsets 1023 * but are now considered MCR registers. Since they exist within a GAM range, 1024 * the primary instance of the register rolls up the status from each unit. 1025 */ 1026 static int wait_for_invalidate(struct intel_gt *gt, struct reg_and_bit rb) 1027 { 1028 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) 1029 return intel_gt_mcr_wait_for_reg(gt, rb.mcr_reg, rb.bit, 0, 1030 TLB_INVAL_TIMEOUT_US, 1031 TLB_INVAL_TIMEOUT_MS); 1032 else 1033 return __intel_wait_for_register_fw(gt->uncore, rb.reg, rb.bit, 0, 1034 TLB_INVAL_TIMEOUT_US, 1035 TLB_INVAL_TIMEOUT_MS, 1036 NULL); 1037 } 1038 1039 static void mmio_invalidate_full(struct intel_gt *gt) 1040 { 1041 static const i915_reg_t gen8_regs[] = { 1042 [RENDER_CLASS] = GEN8_RTCR, 1043 [VIDEO_DECODE_CLASS] = GEN8_M1TCR, /* , GEN8_M2TCR */ 1044 [VIDEO_ENHANCEMENT_CLASS] = GEN8_VTCR, 1045 [COPY_ENGINE_CLASS] = GEN8_BTCR, 1046 }; 1047 static const i915_reg_t gen12_regs[] = { 1048 [RENDER_CLASS] = GEN12_GFX_TLB_INV_CR, 1049 [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR, 1050 [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR, 1051 [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR, 1052 [COMPUTE_CLASS] = GEN12_COMPCTX_TLB_INV_CR, 1053 }; 1054 static const i915_mcr_reg_t xehp_regs[] = { 1055 [RENDER_CLASS] = XEHP_GFX_TLB_INV_CR, 1056 [VIDEO_DECODE_CLASS] = XEHP_VD_TLB_INV_CR, 1057 [VIDEO_ENHANCEMENT_CLASS] = XEHP_VE_TLB_INV_CR, 1058 [COPY_ENGINE_CLASS] = XEHP_BLT_TLB_INV_CR, 1059 [COMPUTE_CLASS] = XEHP_COMPCTX_TLB_INV_CR, 1060 }; 1061 struct drm_i915_private *i915 = gt->i915; 1062 struct intel_uncore *uncore = gt->uncore; 1063 struct intel_engine_cs *engine; 1064 intel_engine_mask_t awake, tmp; 1065 enum intel_engine_id id; 1066 const i915_reg_t *regs; 1067 unsigned int num = 0; 1068 unsigned long flags; 1069 1070 /* 1071 * New platforms should not be added with catch-all-newer (>=) 1072 * condition so that any later platform added triggers the below warning 1073 * and in turn mandates a human cross-check of whether the invalidation 1074 * flows have compatible semantics. 1075 * 1076 * For instance with the 11.00 -> 12.00 transition three out of five 1077 * respective engine registers were moved to masked type. Then after the 1078 * 12.00 -> 12.50 transition multi cast handling is required too. 1079 */ 1080 1081 if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) || 1082 GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) { 1083 regs = NULL; 1084 num = ARRAY_SIZE(xehp_regs); 1085 } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) || 1086 GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) { 1087 regs = gen12_regs; 1088 num = ARRAY_SIZE(gen12_regs); 1089 } else if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) <= 11) { 1090 regs = gen8_regs; 1091 num = ARRAY_SIZE(gen8_regs); 1092 } else if (GRAPHICS_VER(i915) < 8) { 1093 return; 1094 } 1095 1096 if (gt_WARN_ONCE(gt, !num, "Platform does not implement TLB invalidation!")) 1097 return; 1098 1099 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 1100 1101 intel_gt_mcr_lock(gt, &flags); 1102 spin_lock(&uncore->lock); /* serialise invalidate with GT reset */ 1103 1104 awake = 0; 1105 for_each_engine(engine, gt, id) { 1106 struct reg_and_bit rb; 1107 1108 if (!intel_engine_pm_is_awake(engine)) 1109 continue; 1110 1111 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 1112 u32 val = BIT(engine->instance); 1113 1114 if (engine->class == VIDEO_DECODE_CLASS || 1115 engine->class == VIDEO_ENHANCEMENT_CLASS || 1116 engine->class == COMPUTE_CLASS) 1117 val = _MASKED_BIT_ENABLE(val); 1118 intel_gt_mcr_multicast_write_fw(gt, 1119 xehp_regs[engine->class], 1120 val); 1121 } else { 1122 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); 1123 if (!i915_mmio_reg_offset(rb.reg)) 1124 continue; 1125 1126 if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || 1127 engine->class == VIDEO_ENHANCEMENT_CLASS || 1128 engine->class == COMPUTE_CLASS)) 1129 rb.bit = _MASKED_BIT_ENABLE(rb.bit); 1130 1131 intel_uncore_write_fw(uncore, rb.reg, rb.bit); 1132 } 1133 awake |= engine->mask; 1134 } 1135 1136 GT_TRACE(gt, "invalidated engines %08x\n", awake); 1137 1138 /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */ 1139 if (awake && 1140 (IS_TIGERLAKE(i915) || 1141 IS_DG1(i915) || 1142 IS_ROCKETLAKE(i915) || 1143 IS_ALDERLAKE_S(i915) || 1144 IS_ALDERLAKE_P(i915))) 1145 intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1); 1146 1147 spin_unlock(&uncore->lock); 1148 intel_gt_mcr_unlock(gt, flags); 1149 1150 for_each_engine_masked(engine, gt, awake, tmp) { 1151 struct reg_and_bit rb; 1152 1153 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 1154 rb.mcr_reg = xehp_regs[engine->class]; 1155 rb.bit = BIT(engine->instance); 1156 } else { 1157 rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); 1158 } 1159 1160 if (wait_for_invalidate(gt, rb)) 1161 gt_err_ratelimited(gt, "%s TLB invalidation did not complete in %ums!\n", 1162 engine->name, TLB_INVAL_TIMEOUT_MS); 1163 } 1164 1165 /* 1166 * Use delayed put since a) we mostly expect a flurry of TLB 1167 * invalidations so it is good to avoid paying the forcewake cost and 1168 * b) it works around a bug in Icelake which cannot cope with too rapid 1169 * transitions. 1170 */ 1171 intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL); 1172 } 1173 1174 static bool tlb_seqno_passed(const struct intel_gt *gt, u32 seqno) 1175 { 1176 u32 cur = intel_gt_tlb_seqno(gt); 1177 1178 /* Only skip if a *full* TLB invalidate barrier has passed */ 1179 return (s32)(cur - ALIGN(seqno, 2)) > 0; 1180 } 1181 1182 void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno) 1183 { 1184 intel_wakeref_t wakeref; 1185 1186 if (I915_SELFTEST_ONLY(gt->awake == -ENODEV)) 1187 return; 1188 1189 if (intel_gt_is_wedged(gt)) 1190 return; 1191 1192 if (tlb_seqno_passed(gt, seqno)) 1193 return; 1194 1195 with_intel_gt_pm_if_awake(gt, wakeref) { 1196 mutex_lock(>->tlb.invalidate_lock); 1197 if (tlb_seqno_passed(gt, seqno)) 1198 goto unlock; 1199 1200 mmio_invalidate_full(gt); 1201 1202 write_seqcount_invalidate(>->tlb.seqno); 1203 unlock: 1204 mutex_unlock(>->tlb.invalidate_lock); 1205 } 1206 } 1207