1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "intel_ggtt_gmch.h" 7 8 #include <drm/drm_print.h> 9 #include <drm/intel/intel-gtt.h> 10 11 #include <linux/agp_backend.h> 12 13 #include "i915_drv.h" 14 #include "i915_utils.h" 15 #include "intel_gtt.h" 16 #include "intel_gt_regs.h" 17 #include "intel_gt.h" 18 19 static void gmch_ggtt_insert_page(struct i915_address_space *vm, 20 dma_addr_t addr, 21 u64 offset, 22 unsigned int pat_index, 23 u32 unused) 24 { 25 unsigned int flags = (pat_index == I915_CACHE_NONE) ? 26 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; 27 28 intel_gmch_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); 29 } 30 31 static dma_addr_t gmch_ggtt_read_entry(struct i915_address_space *vm, 32 u64 offset, bool *is_present, bool *is_local) 33 { 34 return intel_gmch_gtt_read_entry(offset >> PAGE_SHIFT, 35 is_present, is_local); 36 } 37 38 static void gmch_ggtt_insert_entries(struct i915_address_space *vm, 39 struct i915_vma_resource *vma_res, 40 unsigned int pat_index, 41 u32 unused) 42 { 43 unsigned int flags = (pat_index == I915_CACHE_NONE) ? 44 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; 45 46 intel_gmch_gtt_insert_sg_entries(vma_res->bi.pages, vma_res->start >> PAGE_SHIFT, 47 flags); 48 } 49 50 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt) 51 { 52 intel_gmch_gtt_flush(); 53 } 54 55 static void gmch_ggtt_clear_range(struct i915_address_space *vm, 56 u64 start, u64 length) 57 { 58 intel_gmch_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); 59 } 60 61 static void gmch_ggtt_remove(struct i915_address_space *vm) 62 { 63 intel_gmch_remove(); 64 } 65 66 /* 67 * Certain Gen5 chipsets require idling the GPU before unmapping anything from 68 * the GTT when VT-d is enabled. 69 */ 70 static bool needs_idle_maps(struct drm_i915_private *i915) 71 { 72 /* 73 * Query intel_iommu to see if we need the workaround. Presumably that 74 * was loaded first. 75 */ 76 if (!i915_vtd_active(i915)) 77 return false; 78 79 if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915)) 80 return true; 81 82 return false; 83 } 84 85 int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt) 86 { 87 struct drm_i915_private *i915 = ggtt->vm.i915; 88 phys_addr_t gmadr_base; 89 int ret; 90 91 ret = intel_gmch_probe(i915->gmch.pdev, to_pci_dev(i915->drm.dev), NULL); 92 if (!ret) { 93 drm_err(&i915->drm, "failed to set up gmch\n"); 94 return -EIO; 95 } 96 97 intel_gmch_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end); 98 99 ggtt->gmadr = DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end); 100 101 ggtt->vm.alloc_pt_dma = alloc_pt_dma; 102 ggtt->vm.alloc_scratch_dma = alloc_pt_dma; 103 104 if (needs_idle_maps(i915)) { 105 drm_notice(&i915->drm, 106 "Flushing DMA requests before IOMMU unmaps; performance may be degraded\n"); 107 ggtt->do_idle_maps = true; 108 } 109 110 ggtt->vm.insert_page = gmch_ggtt_insert_page; 111 ggtt->vm.insert_entries = gmch_ggtt_insert_entries; 112 ggtt->vm.clear_range = gmch_ggtt_clear_range; 113 ggtt->vm.scratch_range = gmch_ggtt_clear_range; 114 ggtt->vm.read_entry = gmch_ggtt_read_entry; 115 ggtt->vm.cleanup = gmch_ggtt_remove; 116 117 ggtt->invalidate = gmch_ggtt_invalidate; 118 119 ggtt->vm.vma_ops.bind_vma = intel_ggtt_bind_vma; 120 ggtt->vm.vma_ops.unbind_vma = intel_ggtt_unbind_vma; 121 122 if (unlikely(ggtt->do_idle_maps)) 123 drm_notice(&i915->drm, 124 "Applying Ironlake quirks for intel_iommu\n"); 125 126 return 0; 127 } 128 129 int intel_ggtt_gmch_enable_hw(struct drm_i915_private *i915) 130 { 131 if (!intel_gmch_enable_gtt()) 132 return -EIO; 133 134 return 0; 135 } 136 137 void intel_ggtt_gmch_flush(void) 138 { 139 intel_gmch_gtt_flush(); 140 } 141