1 /* SPDX-License-Identifier: MIT */ 2 #ifndef _INTEL_RINGBUFFER_H_ 3 #define _INTEL_RINGBUFFER_H_ 4 5 #include <drm/drm_util.h> 6 7 #include <linux/hashtable.h> 8 #include <linux/irq_work.h> 9 #include <linux/random.h> 10 #include <linux/seqlock.h> 11 12 #include "i915_pmu.h" 13 #include "i915_reg.h" 14 #include "i915_request.h" 15 #include "i915_selftest.h" 16 #include "gt/intel_timeline.h" 17 #include "intel_engine_types.h" 18 #include "intel_gpu_commands.h" 19 #include "intel_workarounds.h" 20 21 struct drm_printer; 22 struct intel_gt; 23 24 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, 25 * but keeps the logic simple. Indeed, the whole purpose of this macro is just 26 * to give some inclination as to some of the magic values used in the various 27 * workarounds! 28 */ 29 #define CACHELINE_BYTES 64 30 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32)) 31 32 /* 33 * The register defines to be used with the following macros need to accept a 34 * base param, e.g: 35 * 36 * REG_FOO(base) _MMIO((base) + <relative offset>) 37 * ENGINE_READ(engine, REG_FOO); 38 * 39 * register arrays are to be defined and accessed as follows: 40 * 41 * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>) 42 * ENGINE_READ_IDX(engine, REG_BAR, i) 43 */ 44 45 #define __ENGINE_REG_OP(op__, engine__, ...) \ 46 intel_uncore_##op__((engine__)->uncore, __VA_ARGS__) 47 48 #define __ENGINE_READ_OP(op__, engine__, reg__) \ 49 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base)) 50 51 #define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__) 52 #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__) 53 #define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__) 54 #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__) 55 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__) 56 57 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \ 58 __ENGINE_REG_OP(read64_2x32, (engine__), \ 59 lower_reg__((engine__)->mmio_base), \ 60 upper_reg__((engine__)->mmio_base)) 61 62 #define ENGINE_READ_IDX(engine__, reg__, idx__) \ 63 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__))) 64 65 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \ 66 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__)) 67 68 #define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__) 69 #define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__) 70 #define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__) 71 72 #define GEN6_RING_FAULT_REG_READ(engine__) \ 73 intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__)) 74 75 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \ 76 intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__)) 77 78 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \ 79 ({ \ 80 u32 __val; \ 81 \ 82 __val = intel_uncore_read((engine__)->uncore, \ 83 RING_FAULT_REG(engine__)); \ 84 __val &= ~(clear__); \ 85 __val |= (set__); \ 86 intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \ 87 __val); \ 88 }) 89 90 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to 91 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. 92 */ 93 94 static inline unsigned int 95 execlists_num_ports(const struct intel_engine_execlists * const execlists) 96 { 97 return execlists->port_mask + 1; 98 } 99 100 static inline struct i915_request * 101 execlists_active(const struct intel_engine_execlists *execlists) 102 { 103 return *READ_ONCE(execlists->active); 104 } 105 106 static inline void 107 execlists_active_lock_bh(struct intel_engine_execlists *execlists) 108 { 109 local_bh_disable(); /* prevent local softirq and lock recursion */ 110 tasklet_lock(&execlists->tasklet); 111 } 112 113 static inline void 114 execlists_active_unlock_bh(struct intel_engine_execlists *execlists) 115 { 116 tasklet_unlock(&execlists->tasklet); 117 local_bh_enable(); /* restore softirq, and kick ksoftirqd! */ 118 } 119 120 struct i915_request * 121 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists); 122 123 static inline u32 124 intel_read_status_page(const struct intel_engine_cs *engine, int reg) 125 { 126 /* Ensure that the compiler doesn't optimize away the load. */ 127 return READ_ONCE(engine->status_page.addr[reg]); 128 } 129 130 static inline void 131 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) 132 { 133 /* Writing into the status page should be done sparingly. Since 134 * we do when we are uncertain of the device state, we take a bit 135 * of extra paranoia to try and ensure that the HWS takes the value 136 * we give and that it doesn't end up trapped inside the CPU! 137 */ 138 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 139 mb(); 140 clflush(&engine->status_page.addr[reg]); 141 engine->status_page.addr[reg] = value; 142 clflush(&engine->status_page.addr[reg]); 143 mb(); 144 } else { 145 WRITE_ONCE(engine->status_page.addr[reg], value); 146 } 147 } 148 149 /* 150 * Reads a dword out of the status page, which is written to from the command 151 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 152 * MI_STORE_DATA_IMM. 153 * 154 * The following dwords have a reserved meaning: 155 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 156 * 0x04: ring 0 head pointer 157 * 0x05: ring 1 head pointer (915-class) 158 * 0x06: ring 2 head pointer (915-class) 159 * 0x10-0x1b: Context status DWords (GM45) 160 * 0x1f: Last written status offset. (GM45) 161 * 0x20-0x2f: Reserved (Gen6+) 162 * 163 * The area from dword 0x30 to 0x3ff is available for driver usage. 164 */ 165 #define I915_GEM_HWS_PREEMPT 0x32 166 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32)) 167 #define I915_GEM_HWS_SEQNO 0x40 168 #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32)) 169 #define I915_GEM_HWS_SCRATCH 0x80 170 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) 171 172 #define I915_HWS_CSB_BUF0_INDEX 0x10 173 #define I915_HWS_CSB_WRITE_INDEX 0x1f 174 #define CNL_HWS_CSB_WRITE_INDEX 0x2f 175 176 void intel_engine_stop(struct intel_engine_cs *engine); 177 void intel_engine_cleanup(struct intel_engine_cs *engine); 178 179 int intel_engines_init_mmio(struct intel_gt *gt); 180 int intel_engines_setup(struct intel_gt *gt); 181 int intel_engines_init(struct intel_gt *gt); 182 void intel_engines_cleanup(struct intel_gt *gt); 183 184 int intel_engine_init_common(struct intel_engine_cs *engine); 185 void intel_engine_cleanup_common(struct intel_engine_cs *engine); 186 187 int intel_ring_submission_setup(struct intel_engine_cs *engine); 188 int intel_ring_submission_init(struct intel_engine_cs *engine); 189 190 int intel_engine_stop_cs(struct intel_engine_cs *engine); 191 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); 192 193 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask); 194 195 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine); 196 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine); 197 198 void intel_engine_get_instdone(struct intel_engine_cs *engine, 199 struct intel_instdone *instdone); 200 201 void intel_engine_init_execlists(struct intel_engine_cs *engine); 202 203 void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); 204 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); 205 206 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); 207 208 static inline void 209 intel_engine_queue_breadcrumbs(struct intel_engine_cs *engine) 210 { 211 irq_work_queue(&engine->breadcrumbs.irq_work); 212 } 213 214 void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine); 215 216 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine); 217 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); 218 219 void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine, 220 struct drm_printer *p); 221 222 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) 223 { 224 memset(batch, 0, 6 * sizeof(u32)); 225 226 batch[0] = GFX_OP_PIPE_CONTROL(6); 227 batch[1] = flags; 228 batch[2] = offset; 229 230 return batch + 6; 231 } 232 233 static inline u32 * 234 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 235 { 236 /* We're using qword write, offset should be aligned to 8 bytes. */ 237 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 238 239 /* w/a for post sync ops following a GPGPU operation we 240 * need a prior CS_STALL, which is emitted by the flush 241 * following the batch. 242 */ 243 *cs++ = GFX_OP_PIPE_CONTROL(6); 244 *cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB; 245 *cs++ = gtt_offset; 246 *cs++ = 0; 247 *cs++ = value; 248 /* We're thrashing one dword of HWS. */ 249 *cs++ = 0; 250 251 return cs; 252 } 253 254 static inline u32 * 255 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 256 { 257 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ 258 GEM_BUG_ON(gtt_offset & (1 << 5)); 259 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */ 260 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 261 262 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags; 263 *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT; 264 *cs++ = 0; 265 *cs++ = value; 266 267 return cs; 268 } 269 270 static inline void __intel_engine_reset(struct intel_engine_cs *engine, 271 bool stalled) 272 { 273 if (engine->reset.reset) 274 engine->reset.reset(engine, stalled); 275 engine->serial++; /* contexts lost */ 276 } 277 278 bool intel_engines_are_idle(struct intel_gt *gt); 279 bool intel_engine_is_idle(struct intel_engine_cs *engine); 280 void intel_engine_flush_submission(struct intel_engine_cs *engine); 281 282 void intel_engines_reset_default_submission(struct intel_gt *gt); 283 284 bool intel_engine_can_store_dword(struct intel_engine_cs *engine); 285 286 __printf(3, 4) 287 void intel_engine_dump(struct intel_engine_cs *engine, 288 struct drm_printer *m, 289 const char *header, ...); 290 291 int intel_enable_engine_stats(struct intel_engine_cs *engine); 292 void intel_disable_engine_stats(struct intel_engine_cs *engine); 293 294 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine); 295 296 struct i915_request * 297 intel_engine_find_active_request(struct intel_engine_cs *engine); 298 299 u32 intel_engine_context_size(struct drm_i915_private *i915, u8 class); 300 301 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 302 303 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists) 304 { 305 if (!execlists->preempt_hang.inject_hang) 306 return false; 307 308 complete(&execlists->preempt_hang.completion); 309 return true; 310 } 311 312 #else 313 314 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists) 315 { 316 return false; 317 } 318 319 #endif 320 321 void intel_engine_init_active(struct intel_engine_cs *engine, 322 unsigned int subclass); 323 #define ENGINE_PHYSICAL 0 324 #define ENGINE_MOCK 1 325 #define ENGINE_VIRTUAL 2 326 327 static inline bool 328 intel_engine_has_preempt_reset(const struct intel_engine_cs *engine) 329 { 330 if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT)) 331 return false; 332 333 return intel_engine_has_preemption(engine); 334 } 335 336 static inline bool 337 intel_engine_has_timeslices(const struct intel_engine_cs *engine) 338 { 339 if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) 340 return false; 341 342 return intel_engine_has_semaphores(engine); 343 } 344 345 #endif /* _INTEL_RINGBUFFER_H_ */ 346