1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014 Intel Corporation 4 */ 5 6 #ifndef __GEN8_ENGINE_CS_H__ 7 #define __GEN8_ENGINE_CS_H__ 8 9 #include <linux/string.h> 10 #include <linux/types.h> 11 12 #include "i915_gem.h" /* GEM_BUG_ON */ 13 #include "intel_gt_regs.h" 14 #include "intel_gpu_commands.h" 15 16 struct intel_engine_cs; 17 struct intel_gt; 18 struct i915_request; 19 20 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode); 21 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode); 22 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode); 23 24 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode); 25 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode); 26 27 int gen8_emit_init_breadcrumb(struct i915_request *rq); 28 29 int gen8_emit_bb_start_noarb(struct i915_request *rq, 30 u64 offset, u32 len, 31 const unsigned int flags); 32 int gen8_emit_bb_start(struct i915_request *rq, 33 u64 offset, u32 len, 34 const unsigned int flags); 35 36 int xehp_emit_bb_start_noarb(struct i915_request *rq, 37 u64 offset, u32 len, 38 const unsigned int flags); 39 int xehp_emit_bb_start(struct i915_request *rq, 40 u64 offset, u32 len, 41 const unsigned int flags); 42 43 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs); 44 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs); 45 46 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 47 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 48 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 49 50 u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs); 51 52 static inline u32 * 53 __gen8_emit_pipe_control(u32 *batch, u32 bit_group_0, 54 u32 bit_group_1, u32 offset) 55 { 56 memset(batch, 0, 6 * sizeof(u32)); 57 58 batch[0] = GFX_OP_PIPE_CONTROL(6) | bit_group_0; 59 batch[1] = bit_group_1; 60 batch[2] = offset; 61 62 return batch + 6; 63 } 64 65 static inline u32 *gen8_emit_pipe_control(u32 *batch, 66 u32 bit_group_1, u32 offset) 67 { 68 return __gen8_emit_pipe_control(batch, 0, bit_group_1, offset); 69 } 70 71 static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 bit_group_0, 72 u32 bit_group_1, u32 offset) 73 { 74 return __gen8_emit_pipe_control(batch, bit_group_0, 75 bit_group_1, offset); 76 } 77 78 static inline u32 * 79 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1) 80 { 81 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; 82 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE; 83 *cs++ = offset; 84 *cs++ = 0; 85 *cs++ = value; 86 *cs++ = 0; /* We're thrashing one extra dword. */ 87 88 return cs; 89 } 90 91 static inline u32* 92 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 93 { 94 /* We're using qword write, offset should be aligned to 8 bytes. */ 95 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 96 97 return __gen8_emit_write_rcs(cs, 98 value, 99 gtt_offset, 100 0, 101 flags | PIPE_CONTROL_GLOBAL_GTT_IVB); 102 } 103 104 static inline u32* 105 gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1) 106 { 107 /* We're using qword write, offset should be aligned to 8 bytes. */ 108 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 109 110 return __gen8_emit_write_rcs(cs, 111 value, 112 gtt_offset, 113 flags0, 114 flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB); 115 } 116 117 static inline u32 * 118 __gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 119 { 120 *cs++ = (MI_FLUSH_DW + 1) | flags; 121 *cs++ = gtt_offset; 122 *cs++ = 0; 123 *cs++ = value; 124 125 return cs; 126 } 127 128 static inline u32 * 129 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 130 { 131 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ 132 GEM_BUG_ON(gtt_offset & (1 << 5)); 133 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */ 134 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); 135 136 return __gen8_emit_flush_dw(cs, 137 value, 138 gtt_offset | MI_FLUSH_DW_USE_GTT, 139 flags | MI_FLUSH_DW_OP_STOREDW); 140 } 141 142 #endif /* __GEN8_ENGINE_CS_H__ */ 143