1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #ifndef __GEN6_ENGINE_CS_H__ 7 #define __GEN6_ENGINE_CS_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_gpu_commands.h" 12 13 struct i915_request; 14 struct intel_engine_cs; 15 16 int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode); 17 int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode); 18 int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode); 19 u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 20 u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); 21 22 int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode); 23 u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); 24 u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); 25 26 int gen6_emit_bb_start(struct i915_request *rq, 27 u64 offset, u32 len, 28 unsigned int dispatch_flags); 29 int hsw_emit_bb_start(struct i915_request *rq, 30 u64 offset, u32 len, 31 unsigned int dispatch_flags); 32 33 void gen6_irq_enable(struct intel_engine_cs *engine); 34 void gen6_irq_disable(struct intel_engine_cs *engine); 35 36 void hsw_irq_enable_vecs(struct intel_engine_cs *engine); 37 void hsw_irq_disable_vecs(struct intel_engine_cs *engine); 38 39 #endif /* __GEN6_ENGINE_CS_H__ */ 40