1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2008,2010 Intel Corporation 5 */ 6 7 #include <linux/dma-resv.h> 8 #include <linux/highmem.h> 9 #include <linux/sync_file.h> 10 #include <linux/uaccess.h> 11 12 #include <drm/drm_syncobj.h> 13 14 #include "display/intel_frontbuffer.h" 15 16 #include "gem/i915_gem_ioctls.h" 17 #include "gt/intel_context.h" 18 #include "gt/intel_gpu_commands.h" 19 #include "gt/intel_gt.h" 20 #include "gt/intel_gt_buffer_pool.h" 21 #include "gt/intel_gt_pm.h" 22 #include "gt/intel_ring.h" 23 24 #include "pxp/intel_pxp.h" 25 26 #include "i915_cmd_parser.h" 27 #include "i915_drv.h" 28 #include "i915_file_private.h" 29 #include "i915_gem_clflush.h" 30 #include "i915_gem_context.h" 31 #include "i915_gem_evict.h" 32 #include "i915_gem_ioctls.h" 33 #include "i915_reg.h" 34 #include "i915_trace.h" 35 #include "i915_user_extensions.h" 36 37 struct eb_vma { 38 struct i915_vma *vma; 39 unsigned int flags; 40 41 /** This vma's place in the execbuf reservation list */ 42 struct drm_i915_gem_exec_object2 *exec; 43 struct list_head bind_link; 44 struct list_head reloc_link; 45 46 struct hlist_node node; 47 u32 handle; 48 }; 49 50 enum { 51 FORCE_CPU_RELOC = 1, 52 FORCE_GTT_RELOC, 53 FORCE_GPU_RELOC, 54 #define DBG_FORCE_RELOC 0 /* choose one of the above! */ 55 }; 56 57 /* __EXEC_OBJECT_ flags > BIT(29) defined in i915_vma.h */ 58 #define __EXEC_OBJECT_HAS_PIN BIT(29) 59 #define __EXEC_OBJECT_HAS_FENCE BIT(28) 60 #define __EXEC_OBJECT_USERPTR_INIT BIT(27) 61 #define __EXEC_OBJECT_NEEDS_MAP BIT(26) 62 #define __EXEC_OBJECT_NEEDS_BIAS BIT(25) 63 #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 25) /* all of the above + */ 64 #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) 65 66 #define __EXEC_HAS_RELOC BIT(31) 67 #define __EXEC_ENGINE_PINNED BIT(30) 68 #define __EXEC_USERPTR_USED BIT(29) 69 #define __EXEC_INTERNAL_FLAGS (~0u << 29) 70 #define UPDATE PIN_OFFSET_FIXED 71 72 #define BATCH_OFFSET_BIAS (256*1024) 73 74 #define __I915_EXEC_ILLEGAL_FLAGS \ 75 (__I915_EXEC_UNKNOWN_FLAGS | \ 76 I915_EXEC_CONSTANTS_MASK | \ 77 I915_EXEC_RESOURCE_STREAMER) 78 79 /* Catch emission of unexpected errors for CI! */ 80 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) 81 #undef EINVAL 82 #define EINVAL ({ \ 83 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \ 84 22; \ 85 }) 86 #endif 87 88 /** 89 * DOC: User command execution 90 * 91 * Userspace submits commands to be executed on the GPU as an instruction 92 * stream within a GEM object we call a batchbuffer. This instructions may 93 * refer to other GEM objects containing auxiliary state such as kernels, 94 * samplers, render targets and even secondary batchbuffers. Userspace does 95 * not know where in the GPU memory these objects reside and so before the 96 * batchbuffer is passed to the GPU for execution, those addresses in the 97 * batchbuffer and auxiliary objects are updated. This is known as relocation, 98 * or patching. To try and avoid having to relocate each object on the next 99 * execution, userspace is told the location of those objects in this pass, 100 * but this remains just a hint as the kernel may choose a new location for 101 * any object in the future. 102 * 103 * At the level of talking to the hardware, submitting a batchbuffer for the 104 * GPU to execute is to add content to a buffer from which the HW 105 * command streamer is reading. 106 * 107 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e. 108 * Execlists, this command is not placed on the same buffer as the 109 * remaining items. 110 * 111 * 2. Add a command to invalidate caches to the buffer. 112 * 113 * 3. Add a batchbuffer start command to the buffer; the start command is 114 * essentially a token together with the GPU address of the batchbuffer 115 * to be executed. 116 * 117 * 4. Add a pipeline flush to the buffer. 118 * 119 * 5. Add a memory write command to the buffer to record when the GPU 120 * is done executing the batchbuffer. The memory write writes the 121 * global sequence number of the request, ``i915_request::global_seqno``; 122 * the i915 driver uses the current value in the register to determine 123 * if the GPU has completed the batchbuffer. 124 * 125 * 6. Add a user interrupt command to the buffer. This command instructs 126 * the GPU to issue an interrupt when the command, pipeline flush and 127 * memory write are completed. 128 * 129 * 7. Inform the hardware of the additional commands added to the buffer 130 * (by updating the tail pointer). 131 * 132 * Processing an execbuf ioctl is conceptually split up into a few phases. 133 * 134 * 1. Validation - Ensure all the pointers, handles and flags are valid. 135 * 2. Reservation - Assign GPU address space for every object 136 * 3. Relocation - Update any addresses to point to the final locations 137 * 4. Serialisation - Order the request with respect to its dependencies 138 * 5. Construction - Construct a request to execute the batchbuffer 139 * 6. Submission (at some point in the future execution) 140 * 141 * Reserving resources for the execbuf is the most complicated phase. We 142 * neither want to have to migrate the object in the address space, nor do 143 * we want to have to update any relocations pointing to this object. Ideally, 144 * we want to leave the object where it is and for all the existing relocations 145 * to match. If the object is given a new address, or if userspace thinks the 146 * object is elsewhere, we have to parse all the relocation entries and update 147 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that 148 * all the target addresses in all of its objects match the value in the 149 * relocation entries and that they all match the presumed offsets given by the 150 * list of execbuffer objects. Using this knowledge, we know that if we haven't 151 * moved any buffers, all the relocation entries are valid and we can skip 152 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU 153 * hang.) The requirement for using I915_EXEC_NO_RELOC are: 154 * 155 * The addresses written in the objects must match the corresponding 156 * reloc.presumed_offset which in turn must match the corresponding 157 * execobject.offset. 158 * 159 * Any render targets written to in the batch must be flagged with 160 * EXEC_OBJECT_WRITE. 161 * 162 * To avoid stalling, execobject.offset should match the current 163 * address of that object within the active context. 164 * 165 * The reservation is done is multiple phases. First we try and keep any 166 * object already bound in its current location - so as long as meets the 167 * constraints imposed by the new execbuffer. Any object left unbound after the 168 * first pass is then fitted into any available idle space. If an object does 169 * not fit, all objects are removed from the reservation and the process rerun 170 * after sorting the objects into a priority order (more difficult to fit 171 * objects are tried first). Failing that, the entire VM is cleared and we try 172 * to fit the execbuf once last time before concluding that it simply will not 173 * fit. 174 * 175 * A small complication to all of this is that we allow userspace not only to 176 * specify an alignment and a size for the object in the address space, but 177 * we also allow userspace to specify the exact offset. This objects are 178 * simpler to place (the location is known a priori) all we have to do is make 179 * sure the space is available. 180 * 181 * Once all the objects are in place, patching up the buried pointers to point 182 * to the final locations is a fairly simple job of walking over the relocation 183 * entry arrays, looking up the right address and rewriting the value into 184 * the object. Simple! ... The relocation entries are stored in user memory 185 * and so to access them we have to copy them into a local buffer. That copy 186 * has to avoid taking any pagefaults as they may lead back to a GEM object 187 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split 188 * the relocation into multiple passes. First we try to do everything within an 189 * atomic context (avoid the pagefaults) which requires that we never wait. If 190 * we detect that we may wait, or if we need to fault, then we have to fallback 191 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm 192 * bells yet?) Dropping the mutex means that we lose all the state we have 193 * built up so far for the execbuf and we must reset any global data. However, 194 * we do leave the objects pinned in their final locations - which is a 195 * potential issue for concurrent execbufs. Once we have left the mutex, we can 196 * allocate and copy all the relocation entries into a large array at our 197 * leisure, reacquire the mutex, reclaim all the objects and other state and 198 * then proceed to update any incorrect addresses with the objects. 199 * 200 * As we process the relocation entries, we maintain a record of whether the 201 * object is being written to. Using NORELOC, we expect userspace to provide 202 * this information instead. We also check whether we can skip the relocation 203 * by comparing the expected value inside the relocation entry with the target's 204 * final address. If they differ, we have to map the current object and rewrite 205 * the 4 or 8 byte pointer within. 206 * 207 * Serialising an execbuf is quite simple according to the rules of the GEM 208 * ABI. Execution within each context is ordered by the order of submission. 209 * Writes to any GEM object are in order of submission and are exclusive. Reads 210 * from a GEM object are unordered with respect to other reads, but ordered by 211 * writes. A write submitted after a read cannot occur before the read, and 212 * similarly any read submitted after a write cannot occur before the write. 213 * Writes are ordered between engines such that only one write occurs at any 214 * time (completing any reads beforehand) - using semaphores where available 215 * and CPU serialisation otherwise. Other GEM access obey the same rules, any 216 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU 217 * reads before starting, and any read (either using set-domain or pread) must 218 * flush all GPU writes before starting. (Note we only employ a barrier before, 219 * we currently rely on userspace not concurrently starting a new execution 220 * whilst reading or writing to an object. This may be an advantage or not 221 * depending on how much you trust userspace not to shoot themselves in the 222 * foot.) Serialisation may just result in the request being inserted into 223 * a DAG awaiting its turn, but most simple is to wait on the CPU until 224 * all dependencies are resolved. 225 * 226 * After all of that, is just a matter of closing the request and handing it to 227 * the hardware (well, leaving it in a queue to be executed). However, we also 228 * offer the ability for batchbuffers to be run with elevated privileges so 229 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.) 230 * Before any batch is given extra privileges we first must check that it 231 * contains no nefarious instructions, we check that each instruction is from 232 * our whitelist and all registers are also from an allowed list. We first 233 * copy the user's batchbuffer to a shadow (so that the user doesn't have 234 * access to it, either by the CPU or GPU as we scan it) and then parse each 235 * instruction. If everything is ok, we set a flag telling the hardware to run 236 * the batchbuffer in trusted mode, otherwise the ioctl is rejected. 237 */ 238 239 struct eb_fence { 240 struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */ 241 struct dma_fence *dma_fence; 242 u64 value; 243 struct dma_fence_chain *chain_fence; 244 }; 245 246 struct i915_execbuffer { 247 struct drm_i915_private *i915; /** i915 backpointer */ 248 struct drm_file *file; /** per-file lookup tables and limits */ 249 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */ 250 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */ 251 struct eb_vma *vma; 252 253 struct intel_gt *gt; /* gt for the execbuf */ 254 struct intel_context *context; /* logical state for the request */ 255 struct i915_gem_context *gem_context; /** caller's context */ 256 257 /** our requests to build */ 258 struct i915_request *requests[MAX_ENGINE_INSTANCE + 1]; 259 /** identity of the batch obj/vma */ 260 struct eb_vma *batches[MAX_ENGINE_INSTANCE + 1]; 261 struct i915_vma *trampoline; /** trampoline used for chaining */ 262 263 /** used for excl fence in dma_resv objects when > 1 BB submitted */ 264 struct dma_fence *composite_fence; 265 266 /** actual size of execobj[] as we may extend it for the cmdparser */ 267 unsigned int buffer_count; 268 269 /* number of batches in execbuf IOCTL */ 270 unsigned int num_batches; 271 272 /** list of vma not yet bound during reservation phase */ 273 struct list_head unbound; 274 275 /** list of vma that have execobj.relocation_count */ 276 struct list_head relocs; 277 278 struct i915_gem_ww_ctx ww; 279 280 /** 281 * Track the most recently used object for relocations, as we 282 * frequently have to perform multiple relocations within the same 283 * obj/page 284 */ 285 struct reloc_cache { 286 struct drm_mm_node node; /** temporary GTT binding */ 287 unsigned long vaddr; /** Current kmap address */ 288 unsigned long page; /** Currently mapped page index */ 289 unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */ 290 bool use_64bit_reloc : 1; 291 bool has_llc : 1; 292 bool has_fence : 1; 293 bool needs_unfenced : 1; 294 } reloc_cache; 295 296 u64 invalid_flags; /** Set of execobj.flags that are invalid */ 297 298 /** Length of batch within object */ 299 u64 batch_len[MAX_ENGINE_INSTANCE + 1]; 300 u32 batch_start_offset; /** Location within object of batch */ 301 u32 batch_flags; /** Flags composed for emit_bb_start() */ 302 struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */ 303 304 /** 305 * Indicate either the size of the hastable used to resolve 306 * relocation handles, or if negative that we are using a direct 307 * index into the execobj[]. 308 */ 309 int lut_size; 310 struct hlist_head *buckets; /** ht for relocation handles */ 311 312 struct eb_fence *fences; 313 unsigned long num_fences; 314 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 315 struct i915_capture_list *capture_lists[MAX_ENGINE_INSTANCE + 1]; 316 #endif 317 }; 318 319 static int eb_parse(struct i915_execbuffer *eb); 320 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle); 321 static void eb_unpin_engine(struct i915_execbuffer *eb); 322 static void eb_capture_release(struct i915_execbuffer *eb); 323 324 static bool eb_use_cmdparser(const struct i915_execbuffer *eb) 325 { 326 return intel_engine_requires_cmd_parser(eb->context->engine) || 327 (intel_engine_using_cmd_parser(eb->context->engine) && 328 eb->args->batch_len); 329 } 330 331 static int eb_create(struct i915_execbuffer *eb) 332 { 333 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { 334 unsigned int size = 1 + ilog2(eb->buffer_count); 335 336 /* 337 * Without a 1:1 association between relocation handles and 338 * the execobject[] index, we instead create a hashtable. 339 * We size it dynamically based on available memory, starting 340 * first with 1:1 assocative hash and scaling back until 341 * the allocation succeeds. 342 * 343 * Later on we use a positive lut_size to indicate we are 344 * using this hashtable, and a negative value to indicate a 345 * direct lookup. 346 */ 347 do { 348 gfp_t flags; 349 350 /* While we can still reduce the allocation size, don't 351 * raise a warning and allow the allocation to fail. 352 * On the last pass though, we want to try as hard 353 * as possible to perform the allocation and warn 354 * if it fails. 355 */ 356 flags = GFP_KERNEL; 357 if (size > 1) 358 flags |= __GFP_NORETRY | __GFP_NOWARN; 359 360 eb->buckets = kzalloc(sizeof(struct hlist_head) << size, 361 flags); 362 if (eb->buckets) 363 break; 364 } while (--size); 365 366 if (unlikely(!size)) 367 return -ENOMEM; 368 369 eb->lut_size = size; 370 } else { 371 eb->lut_size = -eb->buffer_count; 372 } 373 374 return 0; 375 } 376 377 static bool 378 eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, 379 const struct i915_vma *vma, 380 unsigned int flags) 381 { 382 const u64 start = i915_vma_offset(vma); 383 const u64 size = i915_vma_size(vma); 384 385 if (size < entry->pad_to_size) 386 return true; 387 388 if (entry->alignment && !IS_ALIGNED(start, entry->alignment)) 389 return true; 390 391 if (flags & EXEC_OBJECT_PINNED && 392 start != entry->offset) 393 return true; 394 395 if (flags & __EXEC_OBJECT_NEEDS_BIAS && 396 start < BATCH_OFFSET_BIAS) 397 return true; 398 399 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) && 400 (start + size + 4095) >> 32) 401 return true; 402 403 if (flags & __EXEC_OBJECT_NEEDS_MAP && 404 !i915_vma_is_map_and_fenceable(vma)) 405 return true; 406 407 return false; 408 } 409 410 static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry, 411 unsigned int exec_flags) 412 { 413 u64 pin_flags = 0; 414 415 if (exec_flags & EXEC_OBJECT_NEEDS_GTT) 416 pin_flags |= PIN_GLOBAL; 417 418 /* 419 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, 420 * limit address to the first 4GBs for unflagged objects. 421 */ 422 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) 423 pin_flags |= PIN_ZONE_4G; 424 425 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP) 426 pin_flags |= PIN_MAPPABLE; 427 428 if (exec_flags & EXEC_OBJECT_PINNED) 429 pin_flags |= entry->offset | PIN_OFFSET_FIXED; 430 else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) 431 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; 432 433 return pin_flags; 434 } 435 436 static int 437 eb_pin_vma(struct i915_execbuffer *eb, 438 const struct drm_i915_gem_exec_object2 *entry, 439 struct eb_vma *ev) 440 { 441 struct i915_vma *vma = ev->vma; 442 u64 pin_flags; 443 int err; 444 445 if (vma->node.size) 446 pin_flags = __i915_vma_offset(vma); 447 else 448 pin_flags = entry->offset & PIN_OFFSET_MASK; 449 450 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED | PIN_VALIDATE; 451 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT)) 452 pin_flags |= PIN_GLOBAL; 453 454 /* Attempt to reuse the current location if available */ 455 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags); 456 if (err == -EDEADLK) 457 return err; 458 459 if (unlikely(err)) { 460 if (entry->flags & EXEC_OBJECT_PINNED) 461 return err; 462 463 /* Failing that pick any _free_ space if suitable */ 464 err = i915_vma_pin_ww(vma, &eb->ww, 465 entry->pad_to_size, 466 entry->alignment, 467 eb_pin_flags(entry, ev->flags) | 468 PIN_USER | PIN_NOEVICT | PIN_VALIDATE); 469 if (unlikely(err)) 470 return err; 471 } 472 473 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) { 474 err = i915_vma_pin_fence(vma); 475 if (unlikely(err)) 476 return err; 477 478 if (vma->fence) 479 ev->flags |= __EXEC_OBJECT_HAS_FENCE; 480 } 481 482 ev->flags |= __EXEC_OBJECT_HAS_PIN; 483 if (eb_vma_misplaced(entry, vma, ev->flags)) 484 return -EBADSLT; 485 486 return 0; 487 } 488 489 static void 490 eb_unreserve_vma(struct eb_vma *ev) 491 { 492 if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE)) 493 __i915_vma_unpin_fence(ev->vma); 494 495 ev->flags &= ~__EXEC_OBJECT_RESERVED; 496 } 497 498 static int 499 eb_validate_vma(struct i915_execbuffer *eb, 500 struct drm_i915_gem_exec_object2 *entry, 501 struct i915_vma *vma) 502 { 503 /* Relocations are disallowed for all platforms after TGL-LP. This 504 * also covers all platforms with local memory. 505 */ 506 if (entry->relocation_count && 507 GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915)) 508 return -EINVAL; 509 510 if (unlikely(entry->flags & eb->invalid_flags)) 511 return -EINVAL; 512 513 if (unlikely(entry->alignment && 514 !is_power_of_2_u64(entry->alignment))) 515 return -EINVAL; 516 517 /* 518 * Offset can be used as input (EXEC_OBJECT_PINNED), reject 519 * any non-page-aligned or non-canonical addresses. 520 */ 521 if (unlikely(entry->flags & EXEC_OBJECT_PINNED && 522 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK))) 523 return -EINVAL; 524 525 /* pad_to_size was once a reserved field, so sanitize it */ 526 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) { 527 if (unlikely(offset_in_page(entry->pad_to_size))) 528 return -EINVAL; 529 } else { 530 entry->pad_to_size = 0; 531 } 532 /* 533 * From drm_mm perspective address space is continuous, 534 * so from this point we're always using non-canonical 535 * form internally. 536 */ 537 entry->offset = gen8_noncanonical_addr(entry->offset); 538 539 if (!eb->reloc_cache.has_fence) { 540 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; 541 } else { 542 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE || 543 eb->reloc_cache.needs_unfenced) && 544 i915_gem_object_is_tiled(vma->obj)) 545 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP; 546 } 547 548 return 0; 549 } 550 551 static bool 552 is_batch_buffer(struct i915_execbuffer *eb, unsigned int buffer_idx) 553 { 554 return eb->args->flags & I915_EXEC_BATCH_FIRST ? 555 buffer_idx < eb->num_batches : 556 buffer_idx >= eb->args->buffer_count - eb->num_batches; 557 } 558 559 static int 560 eb_add_vma(struct i915_execbuffer *eb, 561 unsigned int *current_batch, 562 unsigned int i, 563 struct i915_vma *vma) 564 { 565 struct drm_i915_private *i915 = eb->i915; 566 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; 567 struct eb_vma *ev = &eb->vma[i]; 568 569 ev->vma = vma; 570 ev->exec = entry; 571 ev->flags = entry->flags; 572 573 if (eb->lut_size > 0) { 574 ev->handle = entry->handle; 575 hlist_add_head(&ev->node, 576 &eb->buckets[hash_32(entry->handle, 577 eb->lut_size)]); 578 } 579 580 if (entry->relocation_count) 581 list_add_tail(&ev->reloc_link, &eb->relocs); 582 583 /* 584 * SNA is doing fancy tricks with compressing batch buffers, which leads 585 * to negative relocation deltas. Usually that works out ok since the 586 * relocate address is still positive, except when the batch is placed 587 * very low in the GTT. Ensure this doesn't happen. 588 * 589 * Note that actual hangs have only been observed on gen7, but for 590 * paranoia do it everywhere. 591 */ 592 if (is_batch_buffer(eb, i)) { 593 if (entry->relocation_count && 594 !(ev->flags & EXEC_OBJECT_PINNED)) 595 ev->flags |= __EXEC_OBJECT_NEEDS_BIAS; 596 if (eb->reloc_cache.has_fence) 597 ev->flags |= EXEC_OBJECT_NEEDS_FENCE; 598 599 eb->batches[*current_batch] = ev; 600 601 if (unlikely(ev->flags & EXEC_OBJECT_WRITE)) { 602 drm_dbg(&i915->drm, 603 "Attempting to use self-modifying batch buffer\n"); 604 return -EINVAL; 605 } 606 607 if (range_overflows_t(u64, 608 eb->batch_start_offset, 609 eb->args->batch_len, 610 ev->vma->size)) { 611 drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); 612 return -EINVAL; 613 } 614 615 if (eb->args->batch_len == 0) 616 eb->batch_len[*current_batch] = ev->vma->size - 617 eb->batch_start_offset; 618 else 619 eb->batch_len[*current_batch] = eb->args->batch_len; 620 if (unlikely(eb->batch_len[*current_batch] == 0)) { /* impossible! */ 621 drm_dbg(&i915->drm, "Invalid batch length\n"); 622 return -EINVAL; 623 } 624 625 ++*current_batch; 626 } 627 628 return 0; 629 } 630 631 static int use_cpu_reloc(const struct reloc_cache *cache, 632 const struct drm_i915_gem_object *obj) 633 { 634 if (!i915_gem_object_has_struct_page(obj)) 635 return false; 636 637 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) 638 return true; 639 640 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) 641 return false; 642 643 /* 644 * For objects created by userspace through GEM_CREATE with pat_index 645 * set by set_pat extension, i915_gem_object_has_cache_level() always 646 * return true, otherwise the call would fall back to checking whether 647 * the object is un-cached. 648 */ 649 return (cache->has_llc || 650 obj->cache_dirty || 651 !i915_gem_object_has_cache_level(obj, I915_CACHE_NONE)); 652 } 653 654 static int eb_reserve_vma(struct i915_execbuffer *eb, 655 struct eb_vma *ev, 656 u64 pin_flags) 657 { 658 struct drm_i915_gem_exec_object2 *entry = ev->exec; 659 struct i915_vma *vma = ev->vma; 660 int err; 661 662 if (drm_mm_node_allocated(&vma->node) && 663 eb_vma_misplaced(entry, vma, ev->flags)) { 664 err = i915_vma_unbind(vma); 665 if (err) 666 return err; 667 } 668 669 err = i915_vma_pin_ww(vma, &eb->ww, 670 entry->pad_to_size, entry->alignment, 671 eb_pin_flags(entry, ev->flags) | pin_flags); 672 if (err) 673 return err; 674 675 if (entry->offset != i915_vma_offset(vma)) { 676 entry->offset = i915_vma_offset(vma) | UPDATE; 677 eb->args->flags |= __EXEC_HAS_RELOC; 678 } 679 680 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) { 681 err = i915_vma_pin_fence(vma); 682 if (unlikely(err)) 683 return err; 684 685 if (vma->fence) 686 ev->flags |= __EXEC_OBJECT_HAS_FENCE; 687 } 688 689 ev->flags |= __EXEC_OBJECT_HAS_PIN; 690 GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags)); 691 692 return 0; 693 } 694 695 static bool eb_unbind(struct i915_execbuffer *eb, bool force) 696 { 697 const unsigned int count = eb->buffer_count; 698 unsigned int i; 699 struct list_head last; 700 bool unpinned = false; 701 702 /* Resort *all* the objects into priority order */ 703 INIT_LIST_HEAD(&eb->unbound); 704 INIT_LIST_HEAD(&last); 705 706 for (i = 0; i < count; i++) { 707 struct eb_vma *ev = &eb->vma[i]; 708 unsigned int flags = ev->flags; 709 710 if (!force && flags & EXEC_OBJECT_PINNED && 711 flags & __EXEC_OBJECT_HAS_PIN) 712 continue; 713 714 unpinned = true; 715 eb_unreserve_vma(ev); 716 717 if (flags & EXEC_OBJECT_PINNED) 718 /* Pinned must have their slot */ 719 list_add(&ev->bind_link, &eb->unbound); 720 else if (flags & __EXEC_OBJECT_NEEDS_MAP) 721 /* Map require the lowest 256MiB (aperture) */ 722 list_add_tail(&ev->bind_link, &eb->unbound); 723 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) 724 /* Prioritise 4GiB region for restricted bo */ 725 list_add(&ev->bind_link, &last); 726 else 727 list_add_tail(&ev->bind_link, &last); 728 } 729 730 list_splice_tail(&last, &eb->unbound); 731 return unpinned; 732 } 733 734 static int eb_reserve(struct i915_execbuffer *eb) 735 { 736 struct eb_vma *ev; 737 unsigned int pass; 738 int err = 0; 739 740 /* 741 * We have one more buffers that we couldn't bind, which could be due to 742 * various reasons. To resolve this we have 4 passes, with every next 743 * level turning the screws tighter: 744 * 745 * 0. Unbind all objects that do not match the GTT constraints for the 746 * execbuffer (fenceable, mappable, alignment etc). Bind all new 747 * objects. This avoids unnecessary unbinding of later objects in order 748 * to make room for the earlier objects *unless* we need to defragment. 749 * 750 * 1. Reorder the buffers, where objects with the most restrictive 751 * placement requirements go first (ignoring fixed location buffers for 752 * now). For example, objects needing the mappable aperture (the first 753 * 256M of GTT), should go first vs objects that can be placed just 754 * about anywhere. Repeat the previous pass. 755 * 756 * 2. Consider buffers that are pinned at a fixed location. Also try to 757 * evict the entire VM this time, leaving only objects that we were 758 * unable to lock. Try again to bind the buffers. (still using the new 759 * buffer order). 760 * 761 * 3. We likely have object lock contention for one or more stubborn 762 * objects in the VM, for which we need to evict to make forward 763 * progress (perhaps we are fighting the shrinker?). When evicting the 764 * VM this time around, anything that we can't lock we now track using 765 * the busy_bo, using the full lock (after dropping the vm->mutex to 766 * prevent deadlocks), instead of trylock. We then continue to evict the 767 * VM, this time with the stubborn object locked, which we can now 768 * hopefully unbind (if still bound in the VM). Repeat until the VM is 769 * evicted. Finally we should be able bind everything. 770 */ 771 for (pass = 0; pass <= 3; pass++) { 772 int pin_flags = PIN_USER | PIN_VALIDATE; 773 774 if (pass == 0) 775 pin_flags |= PIN_NONBLOCK; 776 777 if (pass >= 1) 778 eb_unbind(eb, pass >= 2); 779 780 if (pass == 2) { 781 err = mutex_lock_interruptible(&eb->context->vm->mutex); 782 if (!err) { 783 err = i915_gem_evict_vm(eb->context->vm, &eb->ww, NULL); 784 mutex_unlock(&eb->context->vm->mutex); 785 } 786 if (err) 787 return err; 788 } 789 790 if (pass == 3) { 791 retry: 792 err = mutex_lock_interruptible(&eb->context->vm->mutex); 793 if (!err) { 794 struct drm_i915_gem_object *busy_bo = NULL; 795 796 err = i915_gem_evict_vm(eb->context->vm, &eb->ww, &busy_bo); 797 mutex_unlock(&eb->context->vm->mutex); 798 if (err && busy_bo) { 799 err = i915_gem_object_lock(busy_bo, &eb->ww); 800 i915_gem_object_put(busy_bo); 801 if (!err) 802 goto retry; 803 } 804 } 805 if (err) 806 return err; 807 } 808 809 list_for_each_entry(ev, &eb->unbound, bind_link) { 810 err = eb_reserve_vma(eb, ev, pin_flags); 811 if (err) 812 break; 813 } 814 815 if (err != -ENOSPC) 816 break; 817 } 818 819 return err; 820 } 821 822 static int eb_select_context(struct i915_execbuffer *eb) 823 { 824 struct i915_gem_context *ctx; 825 826 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1); 827 if (unlikely(IS_ERR(ctx))) 828 return PTR_ERR(ctx); 829 830 eb->gem_context = ctx; 831 if (i915_gem_context_has_full_ppgtt(ctx)) 832 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT; 833 834 return 0; 835 } 836 837 static int __eb_add_lut(struct i915_execbuffer *eb, 838 u32 handle, struct i915_vma *vma) 839 { 840 struct i915_gem_context *ctx = eb->gem_context; 841 struct i915_lut_handle *lut; 842 int err; 843 844 lut = i915_lut_handle_alloc(); 845 if (unlikely(!lut)) 846 return -ENOMEM; 847 848 i915_vma_get(vma); 849 if (!atomic_fetch_inc(&vma->open_count)) 850 i915_vma_reopen(vma); 851 lut->handle = handle; 852 lut->ctx = ctx; 853 854 /* Check that the context hasn't been closed in the meantime */ 855 err = -EINTR; 856 if (!mutex_lock_interruptible(&ctx->lut_mutex)) { 857 if (likely(!i915_gem_context_is_closed(ctx))) 858 err = radix_tree_insert(&ctx->handles_vma, handle, vma); 859 else 860 err = -ENOENT; 861 if (err == 0) { /* And nor has this handle */ 862 struct drm_i915_gem_object *obj = vma->obj; 863 864 spin_lock(&obj->lut_lock); 865 if (idr_find(&eb->file->object_idr, handle) == obj) { 866 list_add(&lut->obj_link, &obj->lut_list); 867 } else { 868 radix_tree_delete(&ctx->handles_vma, handle); 869 err = -ENOENT; 870 } 871 spin_unlock(&obj->lut_lock); 872 } 873 mutex_unlock(&ctx->lut_mutex); 874 } 875 if (unlikely(err)) 876 goto err; 877 878 return 0; 879 880 err: 881 i915_vma_close(vma); 882 i915_vma_put(vma); 883 i915_lut_handle_free(lut); 884 return err; 885 } 886 887 static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) 888 { 889 struct i915_address_space *vm = eb->context->vm; 890 891 do { 892 struct drm_i915_gem_object *obj; 893 struct i915_vma *vma; 894 int err; 895 896 rcu_read_lock(); 897 vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle); 898 if (likely(vma && vma->vm == vm)) 899 vma = i915_vma_tryget(vma); 900 rcu_read_unlock(); 901 if (likely(vma)) 902 return vma; 903 904 obj = i915_gem_object_lookup(eb->file, handle); 905 if (unlikely(!obj)) 906 return ERR_PTR(-ENOENT); 907 908 /* 909 * If the user has opted-in for protected-object tracking, make 910 * sure the object encryption can be used. 911 * We only need to do this when the object is first used with 912 * this context, because the context itself will be banned when 913 * the protected objects become invalid. 914 */ 915 if (i915_gem_context_uses_protected_content(eb->gem_context) && 916 i915_gem_object_is_protected(obj)) { 917 err = intel_pxp_key_check(eb->i915->pxp, obj, true); 918 if (err) { 919 i915_gem_object_put(obj); 920 return ERR_PTR(err); 921 } 922 } 923 924 vma = i915_vma_instance(obj, vm, NULL); 925 if (IS_ERR(vma)) { 926 i915_gem_object_put(obj); 927 return vma; 928 } 929 930 err = __eb_add_lut(eb, handle, vma); 931 if (likely(!err)) 932 return vma; 933 934 i915_gem_object_put(obj); 935 if (err != -EEXIST) 936 return ERR_PTR(err); 937 } while (1); 938 } 939 940 static int eb_lookup_vmas(struct i915_execbuffer *eb) 941 { 942 unsigned int i, current_batch = 0; 943 int err = 0; 944 945 INIT_LIST_HEAD(&eb->relocs); 946 947 for (i = 0; i < eb->buffer_count; i++) { 948 struct i915_vma *vma; 949 950 vma = eb_lookup_vma(eb, eb->exec[i].handle); 951 if (IS_ERR(vma)) { 952 err = PTR_ERR(vma); 953 goto err; 954 } 955 956 err = eb_validate_vma(eb, &eb->exec[i], vma); 957 if (unlikely(err)) { 958 i915_vma_put(vma); 959 goto err; 960 } 961 962 err = eb_add_vma(eb, ¤t_batch, i, vma); 963 if (err) 964 return err; 965 966 if (i915_gem_object_is_userptr(vma->obj)) { 967 err = i915_gem_object_userptr_submit_init(vma->obj); 968 if (err) { 969 if (i + 1 < eb->buffer_count) { 970 /* 971 * Execbuffer code expects last vma entry to be NULL, 972 * since we already initialized this entry, 973 * set the next value to NULL or we mess up 974 * cleanup handling. 975 */ 976 eb->vma[i + 1].vma = NULL; 977 } 978 979 return err; 980 } 981 982 eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT; 983 eb->args->flags |= __EXEC_USERPTR_USED; 984 } 985 } 986 987 return 0; 988 989 err: 990 eb->vma[i].vma = NULL; 991 return err; 992 } 993 994 static int eb_lock_vmas(struct i915_execbuffer *eb) 995 { 996 unsigned int i; 997 int err; 998 999 for (i = 0; i < eb->buffer_count; i++) { 1000 struct eb_vma *ev = &eb->vma[i]; 1001 struct i915_vma *vma = ev->vma; 1002 1003 err = i915_gem_object_lock(vma->obj, &eb->ww); 1004 if (err) 1005 return err; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int eb_validate_vmas(struct i915_execbuffer *eb) 1012 { 1013 unsigned int i; 1014 int err; 1015 1016 INIT_LIST_HEAD(&eb->unbound); 1017 1018 err = eb_lock_vmas(eb); 1019 if (err) 1020 return err; 1021 1022 for (i = 0; i < eb->buffer_count; i++) { 1023 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; 1024 struct eb_vma *ev = &eb->vma[i]; 1025 struct i915_vma *vma = ev->vma; 1026 1027 err = eb_pin_vma(eb, entry, ev); 1028 if (err == -EDEADLK) 1029 return err; 1030 1031 if (!err) { 1032 if (entry->offset != i915_vma_offset(vma)) { 1033 entry->offset = i915_vma_offset(vma) | UPDATE; 1034 eb->args->flags |= __EXEC_HAS_RELOC; 1035 } 1036 } else { 1037 eb_unreserve_vma(ev); 1038 1039 list_add_tail(&ev->bind_link, &eb->unbound); 1040 if (drm_mm_node_allocated(&vma->node)) { 1041 err = i915_vma_unbind(vma); 1042 if (err) 1043 return err; 1044 } 1045 } 1046 1047 /* Reserve enough slots to accommodate composite fences */ 1048 err = dma_resv_reserve_fences(vma->obj->base.resv, eb->num_batches); 1049 if (err) 1050 return err; 1051 1052 GEM_BUG_ON(drm_mm_node_allocated(&vma->node) && 1053 eb_vma_misplaced(&eb->exec[i], vma, ev->flags)); 1054 } 1055 1056 if (!list_empty(&eb->unbound)) 1057 return eb_reserve(eb); 1058 1059 return 0; 1060 } 1061 1062 static struct eb_vma * 1063 eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) 1064 { 1065 if (eb->lut_size < 0) { 1066 if (handle >= -eb->lut_size) 1067 return NULL; 1068 return &eb->vma[handle]; 1069 } else { 1070 struct hlist_head *head; 1071 struct eb_vma *ev; 1072 1073 head = &eb->buckets[hash_32(handle, eb->lut_size)]; 1074 hlist_for_each_entry(ev, head, node) { 1075 if (ev->handle == handle) 1076 return ev; 1077 } 1078 return NULL; 1079 } 1080 } 1081 1082 static void eb_release_vmas(struct i915_execbuffer *eb, bool final) 1083 { 1084 const unsigned int count = eb->buffer_count; 1085 unsigned int i; 1086 1087 for (i = 0; i < count; i++) { 1088 struct eb_vma *ev = &eb->vma[i]; 1089 struct i915_vma *vma = ev->vma; 1090 1091 if (!vma) 1092 break; 1093 1094 eb_unreserve_vma(ev); 1095 1096 if (final) 1097 i915_vma_put(vma); 1098 } 1099 1100 eb_capture_release(eb); 1101 eb_unpin_engine(eb); 1102 } 1103 1104 static void eb_destroy(const struct i915_execbuffer *eb) 1105 { 1106 if (eb->lut_size > 0) 1107 kfree(eb->buckets); 1108 } 1109 1110 static u64 1111 relocation_target(const struct drm_i915_gem_relocation_entry *reloc, 1112 const struct i915_vma *target) 1113 { 1114 return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target)); 1115 } 1116 1117 static void reloc_cache_init(struct reloc_cache *cache, 1118 struct drm_i915_private *i915) 1119 { 1120 cache->page = -1; 1121 cache->vaddr = 0; 1122 /* Must be a variable in the struct to allow GCC to unroll. */ 1123 cache->graphics_ver = GRAPHICS_VER(i915); 1124 cache->has_llc = HAS_LLC(i915); 1125 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); 1126 cache->has_fence = cache->graphics_ver < 4; 1127 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; 1128 cache->node.flags = 0; 1129 } 1130 1131 static void *unmask_page(unsigned long p) 1132 { 1133 return (void *)(uintptr_t)(p & PAGE_MASK); 1134 } 1135 1136 static unsigned int unmask_flags(unsigned long p) 1137 { 1138 return p & ~PAGE_MASK; 1139 } 1140 1141 #define KMAP 0x4 /* after CLFLUSH_FLAGS */ 1142 1143 static struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) 1144 { 1145 struct drm_i915_private *i915 = 1146 container_of(cache, struct i915_execbuffer, reloc_cache)->i915; 1147 return to_gt(i915)->ggtt; 1148 } 1149 1150 static void reloc_cache_unmap(struct reloc_cache *cache) 1151 { 1152 void *vaddr; 1153 1154 if (!cache->vaddr) 1155 return; 1156 1157 vaddr = unmask_page(cache->vaddr); 1158 if (cache->vaddr & KMAP) 1159 kunmap_atomic(vaddr); 1160 else 1161 io_mapping_unmap_atomic((void __iomem *)vaddr); 1162 } 1163 1164 static void reloc_cache_remap(struct reloc_cache *cache, 1165 struct drm_i915_gem_object *obj) 1166 { 1167 void *vaddr; 1168 1169 if (!cache->vaddr) 1170 return; 1171 1172 if (cache->vaddr & KMAP) { 1173 struct page *page = i915_gem_object_get_page(obj, cache->page); 1174 1175 vaddr = kmap_atomic(page); 1176 cache->vaddr = unmask_flags(cache->vaddr) | 1177 (unsigned long)vaddr; 1178 } else { 1179 struct i915_ggtt *ggtt = cache_to_ggtt(cache); 1180 unsigned long offset; 1181 1182 offset = cache->node.start; 1183 if (!drm_mm_node_allocated(&cache->node)) 1184 offset += cache->page << PAGE_SHIFT; 1185 1186 cache->vaddr = (unsigned long) 1187 io_mapping_map_atomic_wc(&ggtt->iomap, offset); 1188 } 1189 } 1190 1191 static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb) 1192 { 1193 void *vaddr; 1194 1195 if (!cache->vaddr) 1196 return; 1197 1198 vaddr = unmask_page(cache->vaddr); 1199 if (cache->vaddr & KMAP) { 1200 struct drm_i915_gem_object *obj = 1201 (struct drm_i915_gem_object *)cache->node.mm; 1202 if (cache->vaddr & CLFLUSH_AFTER) 1203 mb(); 1204 1205 kunmap_atomic(vaddr); 1206 i915_gem_object_finish_access(obj); 1207 } else { 1208 struct i915_ggtt *ggtt = cache_to_ggtt(cache); 1209 1210 intel_gt_flush_ggtt_writes(ggtt->vm.gt); 1211 io_mapping_unmap_atomic((void __iomem *)vaddr); 1212 1213 if (drm_mm_node_allocated(&cache->node)) { 1214 ggtt->vm.clear_range(&ggtt->vm, 1215 cache->node.start, 1216 cache->node.size); 1217 mutex_lock(&ggtt->vm.mutex); 1218 drm_mm_remove_node(&cache->node); 1219 mutex_unlock(&ggtt->vm.mutex); 1220 } else { 1221 i915_vma_unpin((struct i915_vma *)cache->node.mm); 1222 } 1223 } 1224 1225 cache->vaddr = 0; 1226 cache->page = -1; 1227 } 1228 1229 static void *reloc_kmap(struct drm_i915_gem_object *obj, 1230 struct reloc_cache *cache, 1231 unsigned long pageno) 1232 { 1233 void *vaddr; 1234 struct page *page; 1235 1236 if (cache->vaddr) { 1237 kunmap_atomic(unmask_page(cache->vaddr)); 1238 } else { 1239 unsigned int flushes; 1240 int err; 1241 1242 err = i915_gem_object_prepare_write(obj, &flushes); 1243 if (err) 1244 return ERR_PTR(err); 1245 1246 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); 1247 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); 1248 1249 cache->vaddr = flushes | KMAP; 1250 cache->node.mm = (void *)obj; 1251 if (flushes) 1252 mb(); 1253 } 1254 1255 page = i915_gem_object_get_page(obj, pageno); 1256 if (!obj->mm.dirty) 1257 set_page_dirty(page); 1258 1259 vaddr = kmap_atomic(page); 1260 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; 1261 cache->page = pageno; 1262 1263 return vaddr; 1264 } 1265 1266 static void *reloc_iomap(struct i915_vma *batch, 1267 struct i915_execbuffer *eb, 1268 unsigned long page) 1269 { 1270 struct drm_i915_gem_object *obj = batch->obj; 1271 struct reloc_cache *cache = &eb->reloc_cache; 1272 struct i915_ggtt *ggtt = cache_to_ggtt(cache); 1273 unsigned long offset; 1274 void *vaddr; 1275 1276 if (cache->vaddr) { 1277 intel_gt_flush_ggtt_writes(ggtt->vm.gt); 1278 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); 1279 } else { 1280 struct i915_vma *vma = ERR_PTR(-ENODEV); 1281 int err; 1282 1283 if (i915_gem_object_is_tiled(obj)) 1284 return ERR_PTR(-EINVAL); 1285 1286 if (use_cpu_reloc(cache, obj)) 1287 return NULL; 1288 1289 err = i915_gem_object_set_to_gtt_domain(obj, true); 1290 if (err) 1291 return ERR_PTR(err); 1292 1293 /* 1294 * i915_gem_object_ggtt_pin_ww may attempt to remove the batch 1295 * VMA from the object list because we no longer pin. 1296 * 1297 * Only attempt to pin the batch buffer to ggtt if the current batch 1298 * is not inside ggtt, or the batch buffer is not misplaced. 1299 */ 1300 if (!i915_is_ggtt(batch->vm) || 1301 !i915_vma_misplaced(batch, 0, 0, PIN_MAPPABLE)) { 1302 vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0, 1303 PIN_MAPPABLE | 1304 PIN_NONBLOCK /* NOWARN */ | 1305 PIN_NOEVICT); 1306 } 1307 1308 if (vma == ERR_PTR(-EDEADLK)) 1309 return vma; 1310 1311 if (IS_ERR(vma)) { 1312 memset(&cache->node, 0, sizeof(cache->node)); 1313 mutex_lock(&ggtt->vm.mutex); 1314 err = drm_mm_insert_node_in_range 1315 (&ggtt->vm.mm, &cache->node, 1316 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, 1317 0, ggtt->mappable_end, 1318 DRM_MM_INSERT_LOW); 1319 mutex_unlock(&ggtt->vm.mutex); 1320 if (err) /* no inactive aperture space, use cpu reloc */ 1321 return NULL; 1322 } else { 1323 cache->node.start = i915_ggtt_offset(vma); 1324 cache->node.mm = (void *)vma; 1325 } 1326 } 1327 1328 offset = cache->node.start; 1329 if (drm_mm_node_allocated(&cache->node)) { 1330 ggtt->vm.insert_page(&ggtt->vm, 1331 i915_gem_object_get_dma_address(obj, page), 1332 offset, 1333 i915_gem_get_pat_index(ggtt->vm.i915, 1334 I915_CACHE_NONE), 1335 0); 1336 } else { 1337 offset += page << PAGE_SHIFT; 1338 } 1339 1340 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, 1341 offset); 1342 cache->page = page; 1343 cache->vaddr = (unsigned long)vaddr; 1344 1345 return vaddr; 1346 } 1347 1348 static void *reloc_vaddr(struct i915_vma *vma, 1349 struct i915_execbuffer *eb, 1350 unsigned long page) 1351 { 1352 struct reloc_cache *cache = &eb->reloc_cache; 1353 void *vaddr; 1354 1355 if (cache->page == page) { 1356 vaddr = unmask_page(cache->vaddr); 1357 } else { 1358 vaddr = NULL; 1359 if ((cache->vaddr & KMAP) == 0) 1360 vaddr = reloc_iomap(vma, eb, page); 1361 if (!vaddr) 1362 vaddr = reloc_kmap(vma->obj, cache, page); 1363 } 1364 1365 return vaddr; 1366 } 1367 1368 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) 1369 { 1370 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { 1371 if (flushes & CLFLUSH_BEFORE) 1372 drm_clflush_virt_range(addr, sizeof(*addr)); 1373 1374 *addr = value; 1375 1376 /* 1377 * Writes to the same cacheline are serialised by the CPU 1378 * (including clflush). On the write path, we only require 1379 * that it hits memory in an orderly fashion and place 1380 * mb barriers at the start and end of the relocation phase 1381 * to ensure ordering of clflush wrt to the system. 1382 */ 1383 if (flushes & CLFLUSH_AFTER) 1384 drm_clflush_virt_range(addr, sizeof(*addr)); 1385 } else 1386 *addr = value; 1387 } 1388 1389 static u64 1390 relocate_entry(struct i915_vma *vma, 1391 const struct drm_i915_gem_relocation_entry *reloc, 1392 struct i915_execbuffer *eb, 1393 const struct i915_vma *target) 1394 { 1395 u64 target_addr = relocation_target(reloc, target); 1396 u64 offset = reloc->offset; 1397 bool wide = eb->reloc_cache.use_64bit_reloc; 1398 void *vaddr; 1399 1400 repeat: 1401 vaddr = reloc_vaddr(vma, eb, 1402 offset >> PAGE_SHIFT); 1403 if (IS_ERR(vaddr)) 1404 return PTR_ERR(vaddr); 1405 1406 GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32))); 1407 clflush_write32(vaddr + offset_in_page(offset), 1408 lower_32_bits(target_addr), 1409 eb->reloc_cache.vaddr); 1410 1411 if (wide) { 1412 offset += sizeof(u32); 1413 target_addr >>= 32; 1414 wide = false; 1415 goto repeat; 1416 } 1417 1418 return target->node.start | UPDATE; 1419 } 1420 1421 static u64 1422 eb_relocate_entry(struct i915_execbuffer *eb, 1423 struct eb_vma *ev, 1424 const struct drm_i915_gem_relocation_entry *reloc) 1425 { 1426 struct drm_i915_private *i915 = eb->i915; 1427 struct eb_vma *target; 1428 int err; 1429 1430 /* we've already hold a reference to all valid objects */ 1431 target = eb_get_vma(eb, reloc->target_handle); 1432 if (unlikely(!target)) 1433 return -ENOENT; 1434 1435 /* Validate that the target is in a valid r/w GPU domain */ 1436 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { 1437 drm_dbg(&i915->drm, "reloc with multiple write domains: " 1438 "target %d offset %d " 1439 "read %08x write %08x\n", 1440 reloc->target_handle, 1441 (int) reloc->offset, 1442 reloc->read_domains, 1443 reloc->write_domain); 1444 return -EINVAL; 1445 } 1446 if (unlikely((reloc->write_domain | reloc->read_domains) 1447 & ~I915_GEM_GPU_DOMAINS)) { 1448 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: " 1449 "target %d offset %d " 1450 "read %08x write %08x\n", 1451 reloc->target_handle, 1452 (int) reloc->offset, 1453 reloc->read_domains, 1454 reloc->write_domain); 1455 return -EINVAL; 1456 } 1457 1458 if (reloc->write_domain) { 1459 target->flags |= EXEC_OBJECT_WRITE; 1460 1461 /* 1462 * Sandybridge PPGTT errata: We need a global gtt mapping 1463 * for MI and pipe_control writes because the gpu doesn't 1464 * properly redirect them through the ppgtt for non_secure 1465 * batchbuffers. 1466 */ 1467 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && 1468 GRAPHICS_VER(eb->i915) == 6 && 1469 !i915_vma_is_bound(target->vma, I915_VMA_GLOBAL_BIND)) { 1470 struct i915_vma *vma = target->vma; 1471 1472 reloc_cache_unmap(&eb->reloc_cache); 1473 mutex_lock(&vma->vm->mutex); 1474 err = i915_vma_bind(target->vma, 1475 target->vma->obj->pat_index, 1476 PIN_GLOBAL, NULL, NULL); 1477 mutex_unlock(&vma->vm->mutex); 1478 reloc_cache_remap(&eb->reloc_cache, ev->vma->obj); 1479 if (err) 1480 return err; 1481 } 1482 } 1483 1484 /* 1485 * If the relocation already has the right value in it, no 1486 * more work needs to be done. 1487 */ 1488 if (!DBG_FORCE_RELOC && 1489 gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset) 1490 return 0; 1491 1492 /* Check that the relocation address is valid... */ 1493 if (unlikely(reloc->offset > 1494 ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) { 1495 drm_dbg(&i915->drm, "Relocation beyond object bounds: " 1496 "target %d offset %d size %d.\n", 1497 reloc->target_handle, 1498 (int)reloc->offset, 1499 (int)ev->vma->size); 1500 return -EINVAL; 1501 } 1502 if (unlikely(reloc->offset & 3)) { 1503 drm_dbg(&i915->drm, "Relocation not 4-byte aligned: " 1504 "target %d offset %d.\n", 1505 reloc->target_handle, 1506 (int)reloc->offset); 1507 return -EINVAL; 1508 } 1509 1510 /* 1511 * If we write into the object, we need to force the synchronisation 1512 * barrier, either with an asynchronous clflush or if we executed the 1513 * patching using the GPU (though that should be serialised by the 1514 * timeline). To be completely sure, and since we are required to 1515 * do relocations we are already stalling, disable the user's opt 1516 * out of our synchronisation. 1517 */ 1518 ev->flags &= ~EXEC_OBJECT_ASYNC; 1519 1520 /* and update the user's relocation entry */ 1521 return relocate_entry(ev->vma, reloc, eb, target->vma); 1522 } 1523 1524 static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) 1525 { 1526 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) 1527 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; 1528 const struct drm_i915_gem_exec_object2 *entry = ev->exec; 1529 struct drm_i915_gem_relocation_entry __user *urelocs = 1530 u64_to_user_ptr(entry->relocs_ptr); 1531 unsigned long remain = entry->relocation_count; 1532 1533 if (unlikely(remain > N_RELOC(ULONG_MAX))) 1534 return -EINVAL; 1535 1536 /* 1537 * We must check that the entire relocation array is safe 1538 * to read. However, if the array is not writable the user loses 1539 * the updated relocation values. 1540 */ 1541 if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs)))) 1542 return -EFAULT; 1543 1544 do { 1545 struct drm_i915_gem_relocation_entry *r = stack; 1546 unsigned int count = 1547 min_t(unsigned long, remain, ARRAY_SIZE(stack)); 1548 unsigned int copied; 1549 1550 /* 1551 * This is the fast path and we cannot handle a pagefault 1552 * whilst holding the struct mutex lest the user pass in the 1553 * relocations contained within a mmaped bo. For in such a case 1554 * we, the page fault handler would call i915_gem_fault() and 1555 * we would try to acquire the struct mutex again. Obviously 1556 * this is bad and so lockdep complains vehemently. 1557 */ 1558 pagefault_disable(); 1559 copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0])); 1560 pagefault_enable(); 1561 if (unlikely(copied)) { 1562 remain = -EFAULT; 1563 goto out; 1564 } 1565 1566 remain -= count; 1567 do { 1568 u64 offset = eb_relocate_entry(eb, ev, r); 1569 1570 if (likely(offset == 0)) { 1571 } else if ((s64)offset < 0) { 1572 remain = (int)offset; 1573 goto out; 1574 } else { 1575 /* 1576 * Note that reporting an error now 1577 * leaves everything in an inconsistent 1578 * state as we have *already* changed 1579 * the relocation value inside the 1580 * object. As we have not changed the 1581 * reloc.presumed_offset or will not 1582 * change the execobject.offset, on the 1583 * call we may not rewrite the value 1584 * inside the object, leaving it 1585 * dangling and causing a GPU hang. Unless 1586 * userspace dynamically rebuilds the 1587 * relocations on each execbuf rather than 1588 * presume a static tree. 1589 * 1590 * We did previously check if the relocations 1591 * were writable (access_ok), an error now 1592 * would be a strange race with mprotect, 1593 * having already demonstrated that we 1594 * can read from this userspace address. 1595 */ 1596 offset = gen8_canonical_addr(offset & ~UPDATE); 1597 __put_user(offset, 1598 &urelocs[r - stack].presumed_offset); 1599 } 1600 } while (r++, --count); 1601 urelocs += ARRAY_SIZE(stack); 1602 } while (remain); 1603 out: 1604 reloc_cache_reset(&eb->reloc_cache, eb); 1605 return remain; 1606 } 1607 1608 static int 1609 eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev) 1610 { 1611 const struct drm_i915_gem_exec_object2 *entry = ev->exec; 1612 struct drm_i915_gem_relocation_entry *relocs = 1613 u64_to_ptr(typeof(*relocs), entry->relocs_ptr); 1614 unsigned int i; 1615 int err; 1616 1617 for (i = 0; i < entry->relocation_count; i++) { 1618 u64 offset = eb_relocate_entry(eb, ev, &relocs[i]); 1619 1620 if ((s64)offset < 0) { 1621 err = (int)offset; 1622 goto err; 1623 } 1624 } 1625 err = 0; 1626 err: 1627 reloc_cache_reset(&eb->reloc_cache, eb); 1628 return err; 1629 } 1630 1631 static int check_relocations(const struct drm_i915_gem_exec_object2 *entry) 1632 { 1633 const char __user *addr, *end; 1634 unsigned long size; 1635 char __maybe_unused c; 1636 1637 size = entry->relocation_count; 1638 if (size == 0) 1639 return 0; 1640 1641 if (size > N_RELOC(ULONG_MAX)) 1642 return -EINVAL; 1643 1644 addr = u64_to_user_ptr(entry->relocs_ptr); 1645 size *= sizeof(struct drm_i915_gem_relocation_entry); 1646 if (!access_ok(addr, size)) 1647 return -EFAULT; 1648 1649 end = addr + size; 1650 for (; addr < end; addr += PAGE_SIZE) { 1651 int err = __get_user(c, addr); 1652 if (err) 1653 return err; 1654 } 1655 return __get_user(c, end - 1); 1656 } 1657 1658 static int eb_copy_relocations(const struct i915_execbuffer *eb) 1659 { 1660 struct drm_i915_gem_relocation_entry *relocs; 1661 const unsigned int count = eb->buffer_count; 1662 unsigned int i; 1663 int err; 1664 1665 for (i = 0; i < count; i++) { 1666 const unsigned int nreloc = eb->exec[i].relocation_count; 1667 struct drm_i915_gem_relocation_entry __user *urelocs; 1668 unsigned long size; 1669 unsigned long copied; 1670 1671 if (nreloc == 0) 1672 continue; 1673 1674 err = check_relocations(&eb->exec[i]); 1675 if (err) 1676 goto err; 1677 1678 urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr); 1679 size = nreloc * sizeof(*relocs); 1680 1681 relocs = kvmalloc_array(size, 1, GFP_KERNEL); 1682 if (!relocs) { 1683 err = -ENOMEM; 1684 goto err; 1685 } 1686 1687 /* copy_from_user is limited to < 4GiB */ 1688 copied = 0; 1689 do { 1690 unsigned int len = 1691 min_t(u64, BIT_ULL(31), size - copied); 1692 1693 if (__copy_from_user((char *)relocs + copied, 1694 (char __user *)urelocs + copied, 1695 len)) 1696 goto end; 1697 1698 copied += len; 1699 } while (copied < size); 1700 1701 /* 1702 * As we do not update the known relocation offsets after 1703 * relocating (due to the complexities in lock handling), 1704 * we need to mark them as invalid now so that we force the 1705 * relocation processing next time. Just in case the target 1706 * object is evicted and then rebound into its old 1707 * presumed_offset before the next execbuffer - if that 1708 * happened we would make the mistake of assuming that the 1709 * relocations were valid. 1710 */ 1711 if (!user_access_begin(urelocs, size)) 1712 goto end; 1713 1714 for (copied = 0; copied < nreloc; copied++) 1715 unsafe_put_user(-1, 1716 &urelocs[copied].presumed_offset, 1717 end_user); 1718 user_access_end(); 1719 1720 eb->exec[i].relocs_ptr = (uintptr_t)relocs; 1721 } 1722 1723 return 0; 1724 1725 end_user: 1726 user_access_end(); 1727 end: 1728 kvfree(relocs); 1729 err = -EFAULT; 1730 err: 1731 while (i--) { 1732 relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr); 1733 if (eb->exec[i].relocation_count) 1734 kvfree(relocs); 1735 } 1736 return err; 1737 } 1738 1739 static int eb_prefault_relocations(const struct i915_execbuffer *eb) 1740 { 1741 const unsigned int count = eb->buffer_count; 1742 unsigned int i; 1743 1744 for (i = 0; i < count; i++) { 1745 int err; 1746 1747 err = check_relocations(&eb->exec[i]); 1748 if (err) 1749 return err; 1750 } 1751 1752 return 0; 1753 } 1754 1755 static int eb_reinit_userptr(struct i915_execbuffer *eb) 1756 { 1757 const unsigned int count = eb->buffer_count; 1758 unsigned int i; 1759 int ret; 1760 1761 if (likely(!(eb->args->flags & __EXEC_USERPTR_USED))) 1762 return 0; 1763 1764 for (i = 0; i < count; i++) { 1765 struct eb_vma *ev = &eb->vma[i]; 1766 1767 if (!i915_gem_object_is_userptr(ev->vma->obj)) 1768 continue; 1769 1770 ret = i915_gem_object_userptr_submit_init(ev->vma->obj); 1771 if (ret) 1772 return ret; 1773 1774 ev->flags |= __EXEC_OBJECT_USERPTR_INIT; 1775 } 1776 1777 return 0; 1778 } 1779 1780 static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) 1781 { 1782 bool have_copy = false; 1783 struct eb_vma *ev; 1784 int err = 0; 1785 1786 repeat: 1787 if (signal_pending(current)) { 1788 err = -ERESTARTSYS; 1789 goto out; 1790 } 1791 1792 /* We may process another execbuffer during the unlock... */ 1793 eb_release_vmas(eb, false); 1794 i915_gem_ww_ctx_fini(&eb->ww); 1795 1796 /* 1797 * We take 3 passes through the slowpatch. 1798 * 1799 * 1 - we try to just prefault all the user relocation entries and 1800 * then attempt to reuse the atomic pagefault disabled fast path again. 1801 * 1802 * 2 - we copy the user entries to a local buffer here outside of the 1803 * local and allow ourselves to wait upon any rendering before 1804 * relocations 1805 * 1806 * 3 - we already have a local copy of the relocation entries, but 1807 * were interrupted (EAGAIN) whilst waiting for the objects, try again. 1808 */ 1809 if (!err) { 1810 err = eb_prefault_relocations(eb); 1811 } else if (!have_copy) { 1812 err = eb_copy_relocations(eb); 1813 have_copy = err == 0; 1814 } else { 1815 cond_resched(); 1816 err = 0; 1817 } 1818 1819 if (!err) 1820 err = eb_reinit_userptr(eb); 1821 1822 i915_gem_ww_ctx_init(&eb->ww, true); 1823 if (err) 1824 goto out; 1825 1826 /* reacquire the objects */ 1827 repeat_validate: 1828 err = eb_pin_engine(eb, false); 1829 if (err) 1830 goto err; 1831 1832 err = eb_validate_vmas(eb); 1833 if (err) 1834 goto err; 1835 1836 GEM_BUG_ON(!eb->batches[0]); 1837 1838 list_for_each_entry(ev, &eb->relocs, reloc_link) { 1839 if (!have_copy) { 1840 err = eb_relocate_vma(eb, ev); 1841 if (err) 1842 break; 1843 } else { 1844 err = eb_relocate_vma_slow(eb, ev); 1845 if (err) 1846 break; 1847 } 1848 } 1849 1850 if (err == -EDEADLK) 1851 goto err; 1852 1853 if (err && !have_copy) 1854 goto repeat; 1855 1856 if (err) 1857 goto err; 1858 1859 /* as last step, parse the command buffer */ 1860 err = eb_parse(eb); 1861 if (err) 1862 goto err; 1863 1864 /* 1865 * Leave the user relocations as are, this is the painfully slow path, 1866 * and we want to avoid the complication of dropping the lock whilst 1867 * having buffers reserved in the aperture and so causing spurious 1868 * ENOSPC for random operations. 1869 */ 1870 1871 err: 1872 if (err == -EDEADLK) { 1873 eb_release_vmas(eb, false); 1874 err = i915_gem_ww_ctx_backoff(&eb->ww); 1875 if (!err) 1876 goto repeat_validate; 1877 } 1878 1879 if (err == -EAGAIN) 1880 goto repeat; 1881 1882 out: 1883 if (have_copy) { 1884 const unsigned int count = eb->buffer_count; 1885 unsigned int i; 1886 1887 for (i = 0; i < count; i++) { 1888 const struct drm_i915_gem_exec_object2 *entry = 1889 &eb->exec[i]; 1890 struct drm_i915_gem_relocation_entry *relocs; 1891 1892 if (!entry->relocation_count) 1893 continue; 1894 1895 relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); 1896 kvfree(relocs); 1897 } 1898 } 1899 1900 return err; 1901 } 1902 1903 static int eb_relocate_parse(struct i915_execbuffer *eb) 1904 { 1905 int err; 1906 bool throttle = true; 1907 1908 retry: 1909 err = eb_pin_engine(eb, throttle); 1910 if (err) { 1911 if (err != -EDEADLK) 1912 return err; 1913 1914 goto err; 1915 } 1916 1917 /* only throttle once, even if we didn't need to throttle */ 1918 throttle = false; 1919 1920 err = eb_validate_vmas(eb); 1921 if (err == -EAGAIN) 1922 goto slow; 1923 else if (err) 1924 goto err; 1925 1926 /* The objects are in their final locations, apply the relocations. */ 1927 if (eb->args->flags & __EXEC_HAS_RELOC) { 1928 struct eb_vma *ev; 1929 1930 list_for_each_entry(ev, &eb->relocs, reloc_link) { 1931 err = eb_relocate_vma(eb, ev); 1932 if (err) 1933 break; 1934 } 1935 1936 if (err == -EDEADLK) 1937 goto err; 1938 else if (err) 1939 goto slow; 1940 } 1941 1942 if (!err) 1943 err = eb_parse(eb); 1944 1945 err: 1946 if (err == -EDEADLK) { 1947 eb_release_vmas(eb, false); 1948 err = i915_gem_ww_ctx_backoff(&eb->ww); 1949 if (!err) 1950 goto retry; 1951 } 1952 1953 return err; 1954 1955 slow: 1956 err = eb_relocate_parse_slow(eb); 1957 if (err) 1958 /* 1959 * If the user expects the execobject.offset and 1960 * reloc.presumed_offset to be an exact match, 1961 * as for using NO_RELOC, then we cannot update 1962 * the execobject.offset until we have completed 1963 * relocation. 1964 */ 1965 eb->args->flags &= ~__EXEC_HAS_RELOC; 1966 1967 return err; 1968 } 1969 1970 /* 1971 * Using two helper loops for the order of which requests / batches are created 1972 * and added the to backend. Requests are created in order from the parent to 1973 * the last child. Requests are added in the reverse order, from the last child 1974 * to parent. This is done for locking reasons as the timeline lock is acquired 1975 * during request creation and released when the request is added to the 1976 * backend. To make lockdep happy (see intel_context_timeline_lock) this must be 1977 * the ordering. 1978 */ 1979 #define for_each_batch_create_order(_eb, _i) \ 1980 for ((_i) = 0; (_i) < (_eb)->num_batches; ++(_i)) 1981 #define for_each_batch_add_order(_eb, _i) \ 1982 BUILD_BUG_ON(!typecheck(int, _i)); \ 1983 for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i)) 1984 1985 static struct i915_request * 1986 eb_find_first_request_added(struct i915_execbuffer *eb) 1987 { 1988 int i; 1989 1990 for_each_batch_add_order(eb, i) 1991 if (eb->requests[i]) 1992 return eb->requests[i]; 1993 1994 GEM_BUG_ON("Request not found"); 1995 1996 return NULL; 1997 } 1998 1999 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 2000 2001 /* Stage with GFP_KERNEL allocations before we enter the signaling critical path */ 2002 static int eb_capture_stage(struct i915_execbuffer *eb) 2003 { 2004 const unsigned int count = eb->buffer_count; 2005 unsigned int i = count, j; 2006 2007 while (i--) { 2008 struct eb_vma *ev = &eb->vma[i]; 2009 struct i915_vma *vma = ev->vma; 2010 unsigned int flags = ev->flags; 2011 2012 if (!(flags & EXEC_OBJECT_CAPTURE)) 2013 continue; 2014 2015 if (i915_gem_context_is_recoverable(eb->gem_context) && 2016 (IS_DGFX(eb->i915) || GRAPHICS_VER_FULL(eb->i915) > IP_VER(12, 0))) 2017 return -EINVAL; 2018 2019 for_each_batch_create_order(eb, j) { 2020 struct i915_capture_list *capture; 2021 2022 capture = kmalloc(sizeof(*capture), GFP_KERNEL); 2023 if (!capture) 2024 continue; 2025 2026 capture->next = eb->capture_lists[j]; 2027 capture->vma_res = i915_vma_resource_get(vma->resource); 2028 eb->capture_lists[j] = capture; 2029 } 2030 } 2031 2032 return 0; 2033 } 2034 2035 /* Commit once we're in the critical path */ 2036 static void eb_capture_commit(struct i915_execbuffer *eb) 2037 { 2038 unsigned int j; 2039 2040 for_each_batch_create_order(eb, j) { 2041 struct i915_request *rq = eb->requests[j]; 2042 2043 if (!rq) 2044 break; 2045 2046 rq->capture_list = eb->capture_lists[j]; 2047 eb->capture_lists[j] = NULL; 2048 } 2049 } 2050 2051 /* 2052 * Release anything that didn't get committed due to errors. 2053 * The capture_list will otherwise be freed at request retire. 2054 */ 2055 static void eb_capture_release(struct i915_execbuffer *eb) 2056 { 2057 unsigned int j; 2058 2059 for_each_batch_create_order(eb, j) { 2060 if (eb->capture_lists[j]) { 2061 i915_request_free_capture_list(eb->capture_lists[j]); 2062 eb->capture_lists[j] = NULL; 2063 } 2064 } 2065 } 2066 2067 static void eb_capture_list_clear(struct i915_execbuffer *eb) 2068 { 2069 memset(eb->capture_lists, 0, sizeof(eb->capture_lists)); 2070 } 2071 2072 #else 2073 2074 static int eb_capture_stage(struct i915_execbuffer *eb) 2075 { 2076 return 0; 2077 } 2078 2079 static void eb_capture_commit(struct i915_execbuffer *eb) 2080 { 2081 } 2082 2083 static void eb_capture_release(struct i915_execbuffer *eb) 2084 { 2085 } 2086 2087 static void eb_capture_list_clear(struct i915_execbuffer *eb) 2088 { 2089 } 2090 2091 #endif 2092 2093 static int eb_move_to_gpu(struct i915_execbuffer *eb) 2094 { 2095 const unsigned int count = eb->buffer_count; 2096 unsigned int i = count; 2097 int err = 0, j; 2098 2099 while (i--) { 2100 struct eb_vma *ev = &eb->vma[i]; 2101 struct i915_vma *vma = ev->vma; 2102 unsigned int flags = ev->flags; 2103 struct drm_i915_gem_object *obj = vma->obj; 2104 2105 assert_vma_held(vma); 2106 2107 /* 2108 * If the GPU is not _reading_ through the CPU cache, we need 2109 * to make sure that any writes (both previous GPU writes from 2110 * before a change in snooping levels and normal CPU writes) 2111 * caught in that cache are flushed to main memory. 2112 * 2113 * We want to say 2114 * obj->cache_dirty && 2115 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) 2116 * but gcc's optimiser doesn't handle that as well and emits 2117 * two jumps instead of one. Maybe one day... 2118 * 2119 * FIXME: There is also sync flushing in set_pages(), which 2120 * serves a different purpose(some of the time at least). 2121 * 2122 * We should consider: 2123 * 2124 * 1. Rip out the async flush code. 2125 * 2126 * 2. Or make the sync flushing use the async clflush path 2127 * using mandatory fences underneath. Currently the below 2128 * async flush happens after we bind the object. 2129 */ 2130 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) { 2131 if (i915_gem_clflush_object(obj, 0)) 2132 flags &= ~EXEC_OBJECT_ASYNC; 2133 } 2134 2135 /* We only need to await on the first request */ 2136 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) { 2137 err = i915_request_await_object 2138 (eb_find_first_request_added(eb), obj, 2139 flags & EXEC_OBJECT_WRITE); 2140 } 2141 2142 for_each_batch_add_order(eb, j) { 2143 if (err) 2144 break; 2145 if (!eb->requests[j]) 2146 continue; 2147 2148 err = _i915_vma_move_to_active(vma, eb->requests[j], 2149 j ? NULL : 2150 eb->composite_fence ? 2151 eb->composite_fence : 2152 &eb->requests[j]->fence, 2153 flags | __EXEC_OBJECT_NO_RESERVE | 2154 __EXEC_OBJECT_NO_REQUEST_AWAIT); 2155 } 2156 } 2157 2158 #ifdef CONFIG_MMU_NOTIFIER 2159 if (!err && (eb->args->flags & __EXEC_USERPTR_USED)) { 2160 read_lock(&eb->i915->mm.notifier_lock); 2161 2162 /* 2163 * count is always at least 1, otherwise __EXEC_USERPTR_USED 2164 * could not have been set 2165 */ 2166 for (i = 0; i < count; i++) { 2167 struct eb_vma *ev = &eb->vma[i]; 2168 struct drm_i915_gem_object *obj = ev->vma->obj; 2169 2170 if (!i915_gem_object_is_userptr(obj)) 2171 continue; 2172 2173 err = i915_gem_object_userptr_submit_done(obj); 2174 if (err) 2175 break; 2176 } 2177 2178 read_unlock(&eb->i915->mm.notifier_lock); 2179 } 2180 #endif 2181 2182 if (unlikely(err)) 2183 goto err_skip; 2184 2185 /* Unconditionally flush any chipset caches (for streaming writes). */ 2186 intel_gt_chipset_flush(eb->gt); 2187 eb_capture_commit(eb); 2188 2189 return 0; 2190 2191 err_skip: 2192 for_each_batch_create_order(eb, j) { 2193 if (!eb->requests[j]) 2194 break; 2195 2196 i915_request_set_error_once(eb->requests[j], err); 2197 } 2198 return err; 2199 } 2200 2201 static int i915_gem_check_execbuffer(struct drm_i915_private *i915, 2202 struct drm_i915_gem_execbuffer2 *exec) 2203 { 2204 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS) 2205 return -EINVAL; 2206 2207 /* Kernel clipping was a DRI1 misfeature */ 2208 if (!(exec->flags & (I915_EXEC_FENCE_ARRAY | 2209 I915_EXEC_USE_EXTENSIONS))) { 2210 if (exec->num_cliprects || exec->cliprects_ptr) 2211 return -EINVAL; 2212 } 2213 2214 if (exec->DR4 == 0xffffffff) { 2215 drm_dbg(&i915->drm, "UXA submitting garbage DR4, fixing up\n"); 2216 exec->DR4 = 0; 2217 } 2218 if (exec->DR1 || exec->DR4) 2219 return -EINVAL; 2220 2221 if ((exec->batch_start_offset | exec->batch_len) & 0x7) 2222 return -EINVAL; 2223 2224 return 0; 2225 } 2226 2227 static int i915_reset_gen7_sol_offsets(struct i915_request *rq) 2228 { 2229 u32 *cs; 2230 int i; 2231 2232 if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) { 2233 drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n"); 2234 return -EINVAL; 2235 } 2236 2237 cs = intel_ring_begin(rq, 4 * 2 + 2); 2238 if (IS_ERR(cs)) 2239 return PTR_ERR(cs); 2240 2241 *cs++ = MI_LOAD_REGISTER_IMM(4); 2242 for (i = 0; i < 4; i++) { 2243 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i)); 2244 *cs++ = 0; 2245 } 2246 *cs++ = MI_NOOP; 2247 intel_ring_advance(rq, cs); 2248 2249 return 0; 2250 } 2251 2252 static struct i915_vma * 2253 shadow_batch_pin(struct i915_execbuffer *eb, 2254 struct drm_i915_gem_object *obj, 2255 struct i915_address_space *vm, 2256 unsigned int flags) 2257 { 2258 struct i915_vma *vma; 2259 int err; 2260 2261 vma = i915_vma_instance(obj, vm, NULL); 2262 if (IS_ERR(vma)) 2263 return vma; 2264 2265 err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags | PIN_VALIDATE); 2266 if (err) 2267 return ERR_PTR(err); 2268 2269 return vma; 2270 } 2271 2272 static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma) 2273 { 2274 /* 2275 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure 2276 * batch" bit. Hence we need to pin secure batches into the global gtt. 2277 * hsw should have this fixed, but bdw mucks it up again. */ 2278 if (eb->batch_flags & I915_DISPATCH_SECURE) 2279 return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, PIN_VALIDATE); 2280 2281 return NULL; 2282 } 2283 2284 static int eb_parse(struct i915_execbuffer *eb) 2285 { 2286 struct drm_i915_private *i915 = eb->i915; 2287 struct intel_gt_buffer_pool_node *pool = eb->batch_pool; 2288 struct i915_vma *shadow, *trampoline, *batch; 2289 unsigned long len; 2290 int err; 2291 2292 if (!eb_use_cmdparser(eb)) { 2293 batch = eb_dispatch_secure(eb, eb->batches[0]->vma); 2294 if (IS_ERR(batch)) 2295 return PTR_ERR(batch); 2296 2297 goto secure_batch; 2298 } 2299 2300 if (intel_context_is_parallel(eb->context)) 2301 return -EINVAL; 2302 2303 len = eb->batch_len[0]; 2304 if (!CMDPARSER_USES_GGTT(eb->i915)) { 2305 /* 2306 * ppGTT backed shadow buffers must be mapped RO, to prevent 2307 * post-scan tampering 2308 */ 2309 if (!eb->context->vm->has_read_only) { 2310 drm_dbg(&i915->drm, 2311 "Cannot prevent post-scan tampering without RO capable vm\n"); 2312 return -EINVAL; 2313 } 2314 } else { 2315 len += I915_CMD_PARSER_TRAMPOLINE_SIZE; 2316 } 2317 if (unlikely(len < eb->batch_len[0])) /* last paranoid check of overflow */ 2318 return -EINVAL; 2319 2320 if (!pool) { 2321 pool = intel_gt_get_buffer_pool(eb->gt, len, 2322 I915_MAP_WB); 2323 if (IS_ERR(pool)) 2324 return PTR_ERR(pool); 2325 eb->batch_pool = pool; 2326 } 2327 2328 err = i915_gem_object_lock(pool->obj, &eb->ww); 2329 if (err) 2330 return err; 2331 2332 shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER); 2333 if (IS_ERR(shadow)) 2334 return PTR_ERR(shadow); 2335 2336 intel_gt_buffer_pool_mark_used(pool); 2337 i915_gem_object_set_readonly(shadow->obj); 2338 shadow->private = pool; 2339 2340 trampoline = NULL; 2341 if (CMDPARSER_USES_GGTT(eb->i915)) { 2342 trampoline = shadow; 2343 2344 shadow = shadow_batch_pin(eb, pool->obj, 2345 &eb->gt->ggtt->vm, 2346 PIN_GLOBAL); 2347 if (IS_ERR(shadow)) 2348 return PTR_ERR(shadow); 2349 2350 shadow->private = pool; 2351 2352 eb->batch_flags |= I915_DISPATCH_SECURE; 2353 } 2354 2355 batch = eb_dispatch_secure(eb, shadow); 2356 if (IS_ERR(batch)) 2357 return PTR_ERR(batch); 2358 2359 err = dma_resv_reserve_fences(shadow->obj->base.resv, 1); 2360 if (err) 2361 return err; 2362 2363 err = intel_engine_cmd_parser(eb->context->engine, 2364 eb->batches[0]->vma, 2365 eb->batch_start_offset, 2366 eb->batch_len[0], 2367 shadow, trampoline); 2368 if (err) 2369 return err; 2370 2371 eb->batches[0] = &eb->vma[eb->buffer_count++]; 2372 eb->batches[0]->vma = i915_vma_get(shadow); 2373 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN; 2374 2375 eb->trampoline = trampoline; 2376 eb->batch_start_offset = 0; 2377 2378 secure_batch: 2379 if (batch) { 2380 if (intel_context_is_parallel(eb->context)) 2381 return -EINVAL; 2382 2383 eb->batches[0] = &eb->vma[eb->buffer_count++]; 2384 eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN; 2385 eb->batches[0]->vma = i915_vma_get(batch); 2386 } 2387 return 0; 2388 } 2389 2390 static int eb_request_submit(struct i915_execbuffer *eb, 2391 struct i915_request *rq, 2392 struct i915_vma *batch, 2393 u64 batch_len) 2394 { 2395 int err; 2396 2397 if (intel_context_nopreempt(rq->context)) 2398 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags); 2399 2400 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) { 2401 err = i915_reset_gen7_sol_offsets(rq); 2402 if (err) 2403 return err; 2404 } 2405 2406 /* 2407 * After we completed waiting for other engines (using HW semaphores) 2408 * then we can signal that this request/batch is ready to run. This 2409 * allows us to determine if the batch is still waiting on the GPU 2410 * or actually running by checking the breadcrumb. 2411 */ 2412 if (rq->context->engine->emit_init_breadcrumb) { 2413 err = rq->context->engine->emit_init_breadcrumb(rq); 2414 if (err) 2415 return err; 2416 } 2417 2418 err = rq->context->engine->emit_bb_start(rq, 2419 i915_vma_offset(batch) + 2420 eb->batch_start_offset, 2421 batch_len, 2422 eb->batch_flags); 2423 if (err) 2424 return err; 2425 2426 if (eb->trampoline) { 2427 GEM_BUG_ON(intel_context_is_parallel(rq->context)); 2428 GEM_BUG_ON(eb->batch_start_offset); 2429 err = rq->context->engine->emit_bb_start(rq, 2430 i915_vma_offset(eb->trampoline) + 2431 batch_len, 0, 0); 2432 if (err) 2433 return err; 2434 } 2435 2436 return 0; 2437 } 2438 2439 static int eb_submit(struct i915_execbuffer *eb) 2440 { 2441 unsigned int i; 2442 int err; 2443 2444 err = eb_move_to_gpu(eb); 2445 2446 for_each_batch_create_order(eb, i) { 2447 if (!eb->requests[i]) 2448 break; 2449 2450 trace_i915_request_queue(eb->requests[i], eb->batch_flags); 2451 if (!err) 2452 err = eb_request_submit(eb, eb->requests[i], 2453 eb->batches[i]->vma, 2454 eb->batch_len[i]); 2455 } 2456 2457 return err; 2458 } 2459 2460 /* 2461 * Find one BSD ring to dispatch the corresponding BSD command. 2462 * The engine index is returned. 2463 */ 2464 static unsigned int 2465 gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, 2466 struct drm_file *file) 2467 { 2468 struct drm_i915_file_private *file_priv = file->driver_priv; 2469 2470 /* Check whether the file_priv has already selected one ring. */ 2471 if ((int)file_priv->bsd_engine < 0) 2472 file_priv->bsd_engine = 2473 get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); 2474 2475 return file_priv->bsd_engine; 2476 } 2477 2478 static const enum intel_engine_id user_ring_map[] = { 2479 [I915_EXEC_DEFAULT] = RCS0, 2480 [I915_EXEC_RENDER] = RCS0, 2481 [I915_EXEC_BLT] = BCS0, 2482 [I915_EXEC_BSD] = VCS0, 2483 [I915_EXEC_VEBOX] = VECS0 2484 }; 2485 2486 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce) 2487 { 2488 struct intel_ring *ring = ce->ring; 2489 struct intel_timeline *tl = ce->timeline; 2490 struct i915_request *rq; 2491 2492 /* 2493 * Completely unscientific finger-in-the-air estimates for suitable 2494 * maximum user request size (to avoid blocking) and then backoff. 2495 */ 2496 if (intel_ring_update_space(ring) >= PAGE_SIZE) 2497 return NULL; 2498 2499 /* 2500 * Find a request that after waiting upon, there will be at least half 2501 * the ring available. The hysteresis allows us to compete for the 2502 * shared ring and should mean that we sleep less often prior to 2503 * claiming our resources, but not so long that the ring completely 2504 * drains before we can submit our next request. 2505 */ 2506 list_for_each_entry(rq, &tl->requests, link) { 2507 if (rq->ring != ring) 2508 continue; 2509 2510 if (__intel_ring_space(rq->postfix, 2511 ring->emit, ring->size) > ring->size / 2) 2512 break; 2513 } 2514 if (&rq->link == &tl->requests) 2515 return NULL; /* weird, we will check again later for real */ 2516 2517 return i915_request_get(rq); 2518 } 2519 2520 static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce, 2521 bool throttle) 2522 { 2523 struct intel_timeline *tl; 2524 struct i915_request *rq = NULL; 2525 2526 /* 2527 * Take a local wakeref for preparing to dispatch the execbuf as 2528 * we expect to access the hardware fairly frequently in the 2529 * process, and require the engine to be kept awake between accesses. 2530 * Upon dispatch, we acquire another prolonged wakeref that we hold 2531 * until the timeline is idle, which in turn releases the wakeref 2532 * taken on the engine, and the parent device. 2533 */ 2534 tl = intel_context_timeline_lock(ce); 2535 if (IS_ERR(tl)) 2536 return PTR_ERR(tl); 2537 2538 intel_context_enter(ce); 2539 if (throttle) 2540 rq = eb_throttle(eb, ce); 2541 intel_context_timeline_unlock(tl); 2542 2543 if (rq) { 2544 bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; 2545 long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT; 2546 2547 if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, 2548 timeout) < 0) { 2549 i915_request_put(rq); 2550 2551 /* 2552 * Error path, cannot use intel_context_timeline_lock as 2553 * that is user interruptable and this clean up step 2554 * must be done. 2555 */ 2556 mutex_lock(&ce->timeline->mutex); 2557 intel_context_exit(ce); 2558 mutex_unlock(&ce->timeline->mutex); 2559 2560 if (nonblock) 2561 return -EWOULDBLOCK; 2562 else 2563 return -EINTR; 2564 } 2565 i915_request_put(rq); 2566 } 2567 2568 return 0; 2569 } 2570 2571 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle) 2572 { 2573 struct intel_context *ce = eb->context, *child; 2574 int err; 2575 int i = 0, j = 0; 2576 2577 GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED); 2578 2579 if (unlikely(intel_context_is_banned(ce))) 2580 return -EIO; 2581 2582 /* 2583 * Pinning the contexts may generate requests in order to acquire 2584 * GGTT space, so do this first before we reserve a seqno for 2585 * ourselves. 2586 */ 2587 err = intel_context_pin_ww(ce, &eb->ww); 2588 if (err) 2589 return err; 2590 for_each_child(ce, child) { 2591 err = intel_context_pin_ww(child, &eb->ww); 2592 GEM_BUG_ON(err); /* perma-pinned should incr a counter */ 2593 } 2594 2595 for_each_child(ce, child) { 2596 err = eb_pin_timeline(eb, child, throttle); 2597 if (err) 2598 goto unwind; 2599 ++i; 2600 } 2601 err = eb_pin_timeline(eb, ce, throttle); 2602 if (err) 2603 goto unwind; 2604 2605 eb->args->flags |= __EXEC_ENGINE_PINNED; 2606 return 0; 2607 2608 unwind: 2609 for_each_child(ce, child) { 2610 if (j++ < i) { 2611 mutex_lock(&child->timeline->mutex); 2612 intel_context_exit(child); 2613 mutex_unlock(&child->timeline->mutex); 2614 } 2615 } 2616 for_each_child(ce, child) 2617 intel_context_unpin(child); 2618 intel_context_unpin(ce); 2619 return err; 2620 } 2621 2622 static void eb_unpin_engine(struct i915_execbuffer *eb) 2623 { 2624 struct intel_context *ce = eb->context, *child; 2625 2626 if (!(eb->args->flags & __EXEC_ENGINE_PINNED)) 2627 return; 2628 2629 eb->args->flags &= ~__EXEC_ENGINE_PINNED; 2630 2631 for_each_child(ce, child) { 2632 mutex_lock(&child->timeline->mutex); 2633 intel_context_exit(child); 2634 mutex_unlock(&child->timeline->mutex); 2635 2636 intel_context_unpin(child); 2637 } 2638 2639 mutex_lock(&ce->timeline->mutex); 2640 intel_context_exit(ce); 2641 mutex_unlock(&ce->timeline->mutex); 2642 2643 intel_context_unpin(ce); 2644 } 2645 2646 static unsigned int 2647 eb_select_legacy_ring(struct i915_execbuffer *eb) 2648 { 2649 struct drm_i915_private *i915 = eb->i915; 2650 struct drm_i915_gem_execbuffer2 *args = eb->args; 2651 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; 2652 2653 if (user_ring_id != I915_EXEC_BSD && 2654 (args->flags & I915_EXEC_BSD_MASK)) { 2655 drm_dbg(&i915->drm, 2656 "execbuf with non bsd ring but with invalid " 2657 "bsd dispatch flags: %d\n", (int)(args->flags)); 2658 return -1; 2659 } 2660 2661 if (user_ring_id == I915_EXEC_BSD && 2662 i915->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO] > 1) { 2663 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; 2664 2665 if (bsd_idx == I915_EXEC_BSD_DEFAULT) { 2666 bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file); 2667 } else if (bsd_idx >= I915_EXEC_BSD_RING1 && 2668 bsd_idx <= I915_EXEC_BSD_RING2) { 2669 bsd_idx >>= I915_EXEC_BSD_SHIFT; 2670 bsd_idx--; 2671 } else { 2672 drm_dbg(&i915->drm, 2673 "execbuf with unknown bsd ring: %u\n", 2674 bsd_idx); 2675 return -1; 2676 } 2677 2678 return _VCS(bsd_idx); 2679 } 2680 2681 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) { 2682 drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n", 2683 user_ring_id); 2684 return -1; 2685 } 2686 2687 return user_ring_map[user_ring_id]; 2688 } 2689 2690 static int 2691 eb_select_engine(struct i915_execbuffer *eb) 2692 { 2693 struct intel_context *ce, *child; 2694 struct intel_gt *gt; 2695 unsigned int idx; 2696 int err; 2697 2698 if (i915_gem_context_user_engines(eb->gem_context)) 2699 idx = eb->args->flags & I915_EXEC_RING_MASK; 2700 else 2701 idx = eb_select_legacy_ring(eb); 2702 2703 ce = i915_gem_context_get_engine(eb->gem_context, idx); 2704 if (IS_ERR(ce)) 2705 return PTR_ERR(ce); 2706 2707 if (intel_context_is_parallel(ce)) { 2708 if (eb->buffer_count < ce->parallel.number_children + 1) { 2709 intel_context_put(ce); 2710 return -EINVAL; 2711 } 2712 if (eb->batch_start_offset || eb->args->batch_len) { 2713 intel_context_put(ce); 2714 return -EINVAL; 2715 } 2716 } 2717 eb->num_batches = ce->parallel.number_children + 1; 2718 gt = ce->engine->gt; 2719 2720 for_each_child(ce, child) 2721 intel_context_get(child); 2722 intel_gt_pm_get(gt); 2723 /* 2724 * Keep GT0 active on MTL so that i915_vma_parked() doesn't 2725 * free VMAs while execbuf ioctl is validating VMAs. 2726 */ 2727 if (gt->info.id) 2728 intel_gt_pm_get(to_gt(gt->i915)); 2729 2730 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { 2731 err = intel_context_alloc_state(ce); 2732 if (err) 2733 goto err; 2734 } 2735 for_each_child(ce, child) { 2736 if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) { 2737 err = intel_context_alloc_state(child); 2738 if (err) 2739 goto err; 2740 } 2741 } 2742 2743 /* 2744 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report 2745 * EIO if the GPU is already wedged. 2746 */ 2747 err = intel_gt_terminally_wedged(ce->engine->gt); 2748 if (err) 2749 goto err; 2750 2751 if (!i915_vm_tryget(ce->vm)) { 2752 err = -ENOENT; 2753 goto err; 2754 } 2755 2756 eb->context = ce; 2757 eb->gt = ce->engine->gt; 2758 2759 /* 2760 * Make sure engine pool stays alive even if we call intel_context_put 2761 * during ww handling. The pool is destroyed when last pm reference 2762 * is dropped, which breaks our -EDEADLK handling. 2763 */ 2764 return err; 2765 2766 err: 2767 if (gt->info.id) 2768 intel_gt_pm_put(to_gt(gt->i915)); 2769 2770 intel_gt_pm_put(gt); 2771 for_each_child(ce, child) 2772 intel_context_put(child); 2773 intel_context_put(ce); 2774 return err; 2775 } 2776 2777 static void 2778 eb_put_engine(struct i915_execbuffer *eb) 2779 { 2780 struct intel_context *child; 2781 2782 i915_vm_put(eb->context->vm); 2783 /* 2784 * This works in conjunction with eb_select_engine() to prevent 2785 * i915_vma_parked() from interfering while execbuf validates vmas. 2786 */ 2787 if (eb->gt->info.id) 2788 intel_gt_pm_put(to_gt(eb->gt->i915)); 2789 intel_gt_pm_put(eb->gt); 2790 for_each_child(eb->context, child) 2791 intel_context_put(child); 2792 intel_context_put(eb->context); 2793 } 2794 2795 static void 2796 __free_fence_array(struct eb_fence *fences, unsigned int n) 2797 { 2798 while (n--) { 2799 drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2)); 2800 dma_fence_put(fences[n].dma_fence); 2801 dma_fence_chain_free(fences[n].chain_fence); 2802 } 2803 kvfree(fences); 2804 } 2805 2806 static int 2807 add_timeline_fence_array(struct i915_execbuffer *eb, 2808 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences) 2809 { 2810 struct drm_i915_gem_exec_fence __user *user_fences; 2811 u64 __user *user_values; 2812 struct eb_fence *f; 2813 u64 nfences; 2814 int err = 0; 2815 2816 nfences = timeline_fences->fence_count; 2817 if (!nfences) 2818 return 0; 2819 2820 /* Check multiplication overflow for access_ok() and kvmalloc_array() */ 2821 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long)); 2822 if (nfences > min_t(unsigned long, 2823 ULONG_MAX / sizeof(*user_fences), 2824 SIZE_MAX / sizeof(*f)) - eb->num_fences) 2825 return -EINVAL; 2826 2827 user_fences = u64_to_user_ptr(timeline_fences->handles_ptr); 2828 if (!access_ok(user_fences, nfences * sizeof(*user_fences))) 2829 return -EFAULT; 2830 2831 user_values = u64_to_user_ptr(timeline_fences->values_ptr); 2832 if (!access_ok(user_values, nfences * sizeof(*user_values))) 2833 return -EFAULT; 2834 2835 f = krealloc(eb->fences, 2836 (eb->num_fences + nfences) * sizeof(*f), 2837 __GFP_NOWARN | GFP_KERNEL); 2838 if (!f) 2839 return -ENOMEM; 2840 2841 eb->fences = f; 2842 f += eb->num_fences; 2843 2844 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) & 2845 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS); 2846 2847 while (nfences--) { 2848 struct drm_i915_gem_exec_fence user_fence; 2849 struct drm_syncobj *syncobj; 2850 struct dma_fence *fence = NULL; 2851 u64 point; 2852 2853 if (__copy_from_user(&user_fence, 2854 user_fences++, 2855 sizeof(user_fence))) 2856 return -EFAULT; 2857 2858 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) 2859 return -EINVAL; 2860 2861 if (__get_user(point, user_values++)) 2862 return -EFAULT; 2863 2864 syncobj = drm_syncobj_find(eb->file, user_fence.handle); 2865 if (!syncobj) { 2866 drm_dbg(&eb->i915->drm, 2867 "Invalid syncobj handle provided\n"); 2868 return -ENOENT; 2869 } 2870 2871 fence = drm_syncobj_fence_get(syncobj); 2872 2873 if (!fence && user_fence.flags && 2874 !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { 2875 drm_dbg(&eb->i915->drm, 2876 "Syncobj handle has no fence\n"); 2877 drm_syncobj_put(syncobj); 2878 return -EINVAL; 2879 } 2880 2881 if (fence) 2882 err = dma_fence_chain_find_seqno(&fence, point); 2883 2884 if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { 2885 drm_dbg(&eb->i915->drm, 2886 "Syncobj handle missing requested point %llu\n", 2887 point); 2888 dma_fence_put(fence); 2889 drm_syncobj_put(syncobj); 2890 return err; 2891 } 2892 2893 /* 2894 * A point might have been signaled already and 2895 * garbage collected from the timeline. In this case 2896 * just ignore the point and carry on. 2897 */ 2898 if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) { 2899 drm_syncobj_put(syncobj); 2900 continue; 2901 } 2902 2903 /* 2904 * For timeline syncobjs we need to preallocate chains for 2905 * later signaling. 2906 */ 2907 if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) { 2908 /* 2909 * Waiting and signaling the same point (when point != 2910 * 0) would break the timeline. 2911 */ 2912 if (user_fence.flags & I915_EXEC_FENCE_WAIT) { 2913 drm_dbg(&eb->i915->drm, 2914 "Trying to wait & signal the same timeline point.\n"); 2915 dma_fence_put(fence); 2916 drm_syncobj_put(syncobj); 2917 return -EINVAL; 2918 } 2919 2920 f->chain_fence = dma_fence_chain_alloc(); 2921 if (!f->chain_fence) { 2922 drm_syncobj_put(syncobj); 2923 dma_fence_put(fence); 2924 return -ENOMEM; 2925 } 2926 } else { 2927 f->chain_fence = NULL; 2928 } 2929 2930 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2); 2931 f->dma_fence = fence; 2932 f->value = point; 2933 f++; 2934 eb->num_fences++; 2935 } 2936 2937 return 0; 2938 } 2939 2940 static int add_fence_array(struct i915_execbuffer *eb) 2941 { 2942 struct drm_i915_gem_execbuffer2 *args = eb->args; 2943 struct drm_i915_gem_exec_fence __user *user; 2944 unsigned long num_fences = args->num_cliprects; 2945 struct eb_fence *f; 2946 2947 if (!(args->flags & I915_EXEC_FENCE_ARRAY)) 2948 return 0; 2949 2950 if (!num_fences) 2951 return 0; 2952 2953 /* Check multiplication overflow for access_ok() and kvmalloc_array() */ 2954 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long)); 2955 if (num_fences > min_t(unsigned long, 2956 ULONG_MAX / sizeof(*user), 2957 SIZE_MAX / sizeof(*f) - eb->num_fences)) 2958 return -EINVAL; 2959 2960 user = u64_to_user_ptr(args->cliprects_ptr); 2961 if (!access_ok(user, num_fences * sizeof(*user))) 2962 return -EFAULT; 2963 2964 f = krealloc(eb->fences, 2965 (eb->num_fences + num_fences) * sizeof(*f), 2966 __GFP_NOWARN | GFP_KERNEL); 2967 if (!f) 2968 return -ENOMEM; 2969 2970 eb->fences = f; 2971 f += eb->num_fences; 2972 while (num_fences--) { 2973 struct drm_i915_gem_exec_fence user_fence; 2974 struct drm_syncobj *syncobj; 2975 struct dma_fence *fence = NULL; 2976 2977 if (__copy_from_user(&user_fence, user++, sizeof(user_fence))) 2978 return -EFAULT; 2979 2980 if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) 2981 return -EINVAL; 2982 2983 syncobj = drm_syncobj_find(eb->file, user_fence.handle); 2984 if (!syncobj) { 2985 drm_dbg(&eb->i915->drm, 2986 "Invalid syncobj handle provided\n"); 2987 return -ENOENT; 2988 } 2989 2990 if (user_fence.flags & I915_EXEC_FENCE_WAIT) { 2991 fence = drm_syncobj_fence_get(syncobj); 2992 if (!fence) { 2993 drm_dbg(&eb->i915->drm, 2994 "Syncobj handle has no fence\n"); 2995 drm_syncobj_put(syncobj); 2996 return -EINVAL; 2997 } 2998 } 2999 3000 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) & 3001 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS); 3002 3003 f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2); 3004 f->dma_fence = fence; 3005 f->value = 0; 3006 f->chain_fence = NULL; 3007 f++; 3008 eb->num_fences++; 3009 } 3010 3011 return 0; 3012 } 3013 3014 static void put_fence_array(struct eb_fence *fences, int num_fences) 3015 { 3016 if (fences) 3017 __free_fence_array(fences, num_fences); 3018 } 3019 3020 static int 3021 await_fence_array(struct i915_execbuffer *eb, 3022 struct i915_request *rq) 3023 { 3024 unsigned int n; 3025 int err; 3026 3027 for (n = 0; n < eb->num_fences; n++) { 3028 if (!eb->fences[n].dma_fence) 3029 continue; 3030 3031 err = i915_request_await_dma_fence(rq, eb->fences[n].dma_fence); 3032 if (err < 0) 3033 return err; 3034 } 3035 3036 return 0; 3037 } 3038 3039 static void signal_fence_array(const struct i915_execbuffer *eb, 3040 struct dma_fence * const fence) 3041 { 3042 unsigned int n; 3043 3044 for (n = 0; n < eb->num_fences; n++) { 3045 struct drm_syncobj *syncobj; 3046 unsigned int flags; 3047 3048 syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2); 3049 if (!(flags & I915_EXEC_FENCE_SIGNAL)) 3050 continue; 3051 3052 if (eb->fences[n].chain_fence) { 3053 drm_syncobj_add_point(syncobj, 3054 eb->fences[n].chain_fence, 3055 fence, 3056 eb->fences[n].value); 3057 /* 3058 * The chain's ownership is transferred to the 3059 * timeline. 3060 */ 3061 eb->fences[n].chain_fence = NULL; 3062 } else { 3063 drm_syncobj_replace_fence(syncobj, fence); 3064 } 3065 } 3066 } 3067 3068 static int 3069 parse_timeline_fences(struct i915_user_extension __user *ext, void *data) 3070 { 3071 struct i915_execbuffer *eb = data; 3072 struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences; 3073 3074 if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences))) 3075 return -EFAULT; 3076 3077 return add_timeline_fence_array(eb, &timeline_fences); 3078 } 3079 3080 static void retire_requests(struct intel_timeline *tl, struct i915_request *end) 3081 { 3082 struct i915_request *rq, *rn; 3083 3084 list_for_each_entry_safe(rq, rn, &tl->requests, link) 3085 if (rq == end || !i915_request_retire(rq)) 3086 break; 3087 } 3088 3089 static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq, 3090 int err, bool last_parallel) 3091 { 3092 struct intel_timeline * const tl = i915_request_timeline(rq); 3093 struct i915_sched_attr attr = {}; 3094 struct i915_request *prev; 3095 3096 lockdep_assert_held(&tl->mutex); 3097 lockdep_unpin_lock(&tl->mutex, rq->cookie); 3098 3099 trace_i915_request_add(rq); 3100 3101 prev = __i915_request_commit(rq); 3102 3103 /* Check that the context wasn't destroyed before submission */ 3104 if (likely(!intel_context_is_closed(eb->context))) { 3105 attr = eb->gem_context->sched; 3106 } else { 3107 /* Serialise with context_close via the add_to_timeline */ 3108 i915_request_set_error_once(rq, -ENOENT); 3109 __i915_request_skip(rq); 3110 err = -ENOENT; /* override any transient errors */ 3111 } 3112 3113 if (intel_context_is_parallel(eb->context)) { 3114 if (err) { 3115 __i915_request_skip(rq); 3116 set_bit(I915_FENCE_FLAG_SKIP_PARALLEL, 3117 &rq->fence.flags); 3118 } 3119 if (last_parallel) 3120 set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL, 3121 &rq->fence.flags); 3122 } 3123 3124 __i915_request_queue(rq, &attr); 3125 3126 /* Try to clean up the client's timeline after submitting the request */ 3127 if (prev) 3128 retire_requests(tl, prev); 3129 3130 mutex_unlock(&tl->mutex); 3131 3132 return err; 3133 } 3134 3135 static int eb_requests_add(struct i915_execbuffer *eb, int err) 3136 { 3137 int i; 3138 3139 /* 3140 * We iterate in reverse order of creation to release timeline mutexes in 3141 * same order. 3142 */ 3143 for_each_batch_add_order(eb, i) { 3144 struct i915_request *rq = eb->requests[i]; 3145 3146 if (!rq) 3147 continue; 3148 err |= eb_request_add(eb, rq, err, i == 0); 3149 } 3150 3151 return err; 3152 } 3153 3154 static const i915_user_extension_fn execbuf_extensions[] = { 3155 [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences, 3156 }; 3157 3158 static int 3159 parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args, 3160 struct i915_execbuffer *eb) 3161 { 3162 if (!(args->flags & I915_EXEC_USE_EXTENSIONS)) 3163 return 0; 3164 3165 /* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot 3166 * have another flag also using it at the same time. 3167 */ 3168 if (eb->args->flags & I915_EXEC_FENCE_ARRAY) 3169 return -EINVAL; 3170 3171 if (args->num_cliprects != 0) 3172 return -EINVAL; 3173 3174 return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr), 3175 execbuf_extensions, 3176 ARRAY_SIZE(execbuf_extensions), 3177 eb); 3178 } 3179 3180 static void eb_requests_get(struct i915_execbuffer *eb) 3181 { 3182 unsigned int i; 3183 3184 for_each_batch_create_order(eb, i) { 3185 if (!eb->requests[i]) 3186 break; 3187 3188 i915_request_get(eb->requests[i]); 3189 } 3190 } 3191 3192 static void eb_requests_put(struct i915_execbuffer *eb) 3193 { 3194 unsigned int i; 3195 3196 for_each_batch_create_order(eb, i) { 3197 if (!eb->requests[i]) 3198 break; 3199 3200 i915_request_put(eb->requests[i]); 3201 } 3202 } 3203 3204 static struct sync_file * 3205 eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd) 3206 { 3207 struct sync_file *out_fence = NULL; 3208 struct dma_fence_array *fence_array; 3209 struct dma_fence **fences; 3210 unsigned int i; 3211 3212 GEM_BUG_ON(!intel_context_is_parent(eb->context)); 3213 3214 fences = kmalloc_array(eb->num_batches, sizeof(*fences), GFP_KERNEL); 3215 if (!fences) 3216 return ERR_PTR(-ENOMEM); 3217 3218 for_each_batch_create_order(eb, i) { 3219 fences[i] = &eb->requests[i]->fence; 3220 __set_bit(I915_FENCE_FLAG_COMPOSITE, 3221 &eb->requests[i]->fence.flags); 3222 } 3223 3224 fence_array = dma_fence_array_create(eb->num_batches, 3225 fences, 3226 eb->context->parallel.fence_context, 3227 eb->context->parallel.seqno++, 3228 false); 3229 if (!fence_array) { 3230 kfree(fences); 3231 return ERR_PTR(-ENOMEM); 3232 } 3233 3234 /* Move ownership to the dma_fence_array created above */ 3235 for_each_batch_create_order(eb, i) 3236 dma_fence_get(fences[i]); 3237 3238 if (out_fence_fd != -1) { 3239 out_fence = sync_file_create(&fence_array->base); 3240 /* sync_file now owns fence_arry, drop creation ref */ 3241 dma_fence_put(&fence_array->base); 3242 if (!out_fence) 3243 return ERR_PTR(-ENOMEM); 3244 } 3245 3246 eb->composite_fence = &fence_array->base; 3247 3248 return out_fence; 3249 } 3250 3251 static struct sync_file * 3252 eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq, 3253 struct dma_fence *in_fence, int out_fence_fd) 3254 { 3255 struct sync_file *out_fence = NULL; 3256 int err; 3257 3258 if (unlikely(eb->gem_context->syncobj)) { 3259 struct dma_fence *fence; 3260 3261 fence = drm_syncobj_fence_get(eb->gem_context->syncobj); 3262 err = i915_request_await_dma_fence(rq, fence); 3263 dma_fence_put(fence); 3264 if (err) 3265 return ERR_PTR(err); 3266 } 3267 3268 if (in_fence) { 3269 if (eb->args->flags & I915_EXEC_FENCE_SUBMIT) 3270 err = i915_request_await_execution(rq, in_fence); 3271 else 3272 err = i915_request_await_dma_fence(rq, in_fence); 3273 if (err < 0) 3274 return ERR_PTR(err); 3275 } 3276 3277 if (eb->fences) { 3278 err = await_fence_array(eb, rq); 3279 if (err) 3280 return ERR_PTR(err); 3281 } 3282 3283 if (intel_context_is_parallel(eb->context)) { 3284 out_fence = eb_composite_fence_create(eb, out_fence_fd); 3285 if (IS_ERR(out_fence)) 3286 return ERR_PTR(-ENOMEM); 3287 } else if (out_fence_fd != -1) { 3288 out_fence = sync_file_create(&rq->fence); 3289 if (!out_fence) 3290 return ERR_PTR(-ENOMEM); 3291 } 3292 3293 return out_fence; 3294 } 3295 3296 static struct intel_context * 3297 eb_find_context(struct i915_execbuffer *eb, unsigned int context_number) 3298 { 3299 struct intel_context *child; 3300 3301 if (likely(context_number == 0)) 3302 return eb->context; 3303 3304 for_each_child(eb->context, child) 3305 if (!--context_number) 3306 return child; 3307 3308 GEM_BUG_ON("Context not found"); 3309 3310 return NULL; 3311 } 3312 3313 static struct sync_file * 3314 eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence, 3315 int out_fence_fd) 3316 { 3317 struct sync_file *out_fence = NULL; 3318 unsigned int i; 3319 3320 for_each_batch_create_order(eb, i) { 3321 /* Allocate a request for this batch buffer nice and early. */ 3322 eb->requests[i] = i915_request_create(eb_find_context(eb, i)); 3323 if (IS_ERR(eb->requests[i])) { 3324 out_fence = ERR_CAST(eb->requests[i]); 3325 eb->requests[i] = NULL; 3326 return out_fence; 3327 } 3328 3329 /* 3330 * Only the first request added (committed to backend) has to 3331 * take the in fences into account as all subsequent requests 3332 * will have fences inserted inbetween them. 3333 */ 3334 if (i + 1 == eb->num_batches) { 3335 out_fence = eb_fences_add(eb, eb->requests[i], 3336 in_fence, out_fence_fd); 3337 if (IS_ERR(out_fence)) 3338 return out_fence; 3339 } 3340 3341 /* 3342 * Not really on stack, but we don't want to call 3343 * kfree on the batch_snapshot when we put it, so use the 3344 * _onstack interface. 3345 */ 3346 if (eb->batches[i]->vma) 3347 eb->requests[i]->batch_res = 3348 i915_vma_resource_get(eb->batches[i]->vma->resource); 3349 if (eb->batch_pool) { 3350 GEM_BUG_ON(intel_context_is_parallel(eb->context)); 3351 intel_gt_buffer_pool_mark_active(eb->batch_pool, 3352 eb->requests[i]); 3353 } 3354 } 3355 3356 return out_fence; 3357 } 3358 3359 static int 3360 i915_gem_do_execbuffer(struct drm_device *dev, 3361 struct drm_file *file, 3362 struct drm_i915_gem_execbuffer2 *args, 3363 struct drm_i915_gem_exec_object2 *exec) 3364 { 3365 struct drm_i915_private *i915 = to_i915(dev); 3366 struct i915_execbuffer eb; 3367 struct dma_fence *in_fence = NULL; 3368 struct sync_file *out_fence = NULL; 3369 int out_fence_fd = -1; 3370 int err; 3371 3372 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS); 3373 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS & 3374 ~__EXEC_OBJECT_UNKNOWN_FLAGS); 3375 3376 eb.i915 = i915; 3377 eb.file = file; 3378 eb.args = args; 3379 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) 3380 args->flags |= __EXEC_HAS_RELOC; 3381 3382 eb.exec = exec; 3383 eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); 3384 eb.vma[0].vma = NULL; 3385 eb.batch_pool = NULL; 3386 3387 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; 3388 reloc_cache_init(&eb.reloc_cache, eb.i915); 3389 3390 eb.buffer_count = args->buffer_count; 3391 eb.batch_start_offset = args->batch_start_offset; 3392 eb.trampoline = NULL; 3393 3394 eb.fences = NULL; 3395 eb.num_fences = 0; 3396 3397 eb_capture_list_clear(&eb); 3398 3399 memset(eb.requests, 0, sizeof(struct i915_request *) * 3400 ARRAY_SIZE(eb.requests)); 3401 eb.composite_fence = NULL; 3402 3403 eb.batch_flags = 0; 3404 if (args->flags & I915_EXEC_SECURE) { 3405 if (GRAPHICS_VER(i915) >= 11) 3406 return -ENODEV; 3407 3408 /* Return -EPERM to trigger fallback code on old binaries. */ 3409 if (!HAS_SECURE_BATCHES(i915)) 3410 return -EPERM; 3411 3412 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN)) 3413 return -EPERM; 3414 3415 eb.batch_flags |= I915_DISPATCH_SECURE; 3416 } 3417 if (args->flags & I915_EXEC_IS_PINNED) 3418 eb.batch_flags |= I915_DISPATCH_PINNED; 3419 3420 err = parse_execbuf2_extensions(args, &eb); 3421 if (err) 3422 goto err_ext; 3423 3424 err = add_fence_array(&eb); 3425 if (err) 3426 goto err_ext; 3427 3428 #define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT) 3429 if (args->flags & IN_FENCES) { 3430 if ((args->flags & IN_FENCES) == IN_FENCES) 3431 return -EINVAL; 3432 3433 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); 3434 if (!in_fence) { 3435 err = -EINVAL; 3436 goto err_ext; 3437 } 3438 } 3439 #undef IN_FENCES 3440 3441 if (args->flags & I915_EXEC_FENCE_OUT) { 3442 out_fence_fd = get_unused_fd_flags(O_CLOEXEC); 3443 if (out_fence_fd < 0) { 3444 err = out_fence_fd; 3445 goto err_in_fence; 3446 } 3447 } 3448 3449 err = eb_create(&eb); 3450 if (err) 3451 goto err_out_fence; 3452 3453 GEM_BUG_ON(!eb.lut_size); 3454 3455 err = eb_select_context(&eb); 3456 if (unlikely(err)) 3457 goto err_destroy; 3458 3459 err = eb_select_engine(&eb); 3460 if (unlikely(err)) 3461 goto err_context; 3462 3463 err = eb_lookup_vmas(&eb); 3464 if (err) { 3465 eb_release_vmas(&eb, true); 3466 goto err_engine; 3467 } 3468 3469 i915_gem_ww_ctx_init(&eb.ww, true); 3470 3471 err = eb_relocate_parse(&eb); 3472 if (err) { 3473 /* 3474 * If the user expects the execobject.offset and 3475 * reloc.presumed_offset to be an exact match, 3476 * as for using NO_RELOC, then we cannot update 3477 * the execobject.offset until we have completed 3478 * relocation. 3479 */ 3480 args->flags &= ~__EXEC_HAS_RELOC; 3481 goto err_vma; 3482 } 3483 3484 ww_acquire_done(&eb.ww.ctx); 3485 err = eb_capture_stage(&eb); 3486 if (err) 3487 goto err_vma; 3488 3489 out_fence = eb_requests_create(&eb, in_fence, out_fence_fd); 3490 if (IS_ERR(out_fence)) { 3491 err = PTR_ERR(out_fence); 3492 out_fence = NULL; 3493 if (eb.requests[0]) 3494 goto err_request; 3495 else 3496 goto err_vma; 3497 } 3498 3499 err = eb_submit(&eb); 3500 3501 err_request: 3502 eb_requests_get(&eb); 3503 err = eb_requests_add(&eb, err); 3504 3505 if (eb.fences) 3506 signal_fence_array(&eb, eb.composite_fence ? 3507 eb.composite_fence : 3508 &eb.requests[0]->fence); 3509 3510 if (unlikely(eb.gem_context->syncobj)) { 3511 drm_syncobj_replace_fence(eb.gem_context->syncobj, 3512 eb.composite_fence ? 3513 eb.composite_fence : 3514 &eb.requests[0]->fence); 3515 } 3516 3517 if (out_fence) { 3518 if (err == 0) { 3519 fd_install(out_fence_fd, out_fence->file); 3520 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */ 3521 args->rsvd2 |= (u64)out_fence_fd << 32; 3522 out_fence_fd = -1; 3523 } else { 3524 fput(out_fence->file); 3525 } 3526 } 3527 3528 if (!out_fence && eb.composite_fence) 3529 dma_fence_put(eb.composite_fence); 3530 3531 eb_requests_put(&eb); 3532 3533 err_vma: 3534 eb_release_vmas(&eb, true); 3535 WARN_ON(err == -EDEADLK); 3536 i915_gem_ww_ctx_fini(&eb.ww); 3537 3538 if (eb.batch_pool) 3539 intel_gt_buffer_pool_put(eb.batch_pool); 3540 err_engine: 3541 eb_put_engine(&eb); 3542 err_context: 3543 i915_gem_context_put(eb.gem_context); 3544 err_destroy: 3545 eb_destroy(&eb); 3546 err_out_fence: 3547 if (out_fence_fd != -1) 3548 put_unused_fd(out_fence_fd); 3549 err_in_fence: 3550 dma_fence_put(in_fence); 3551 err_ext: 3552 put_fence_array(eb.fences, eb.num_fences); 3553 return err; 3554 } 3555 3556 static size_t eb_element_size(void) 3557 { 3558 return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma); 3559 } 3560 3561 static bool check_buffer_count(size_t count) 3562 { 3563 const size_t sz = eb_element_size(); 3564 3565 /* 3566 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup 3567 * array size (see eb_create()). Otherwise, we can accept an array as 3568 * large as can be addressed (though use large arrays at your peril)! 3569 */ 3570 3571 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1); 3572 } 3573 3574 int 3575 i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, 3576 struct drm_file *file) 3577 { 3578 struct drm_i915_private *i915 = to_i915(dev); 3579 struct drm_i915_gem_execbuffer2 *args = data; 3580 struct drm_i915_gem_exec_object2 *exec2_list; 3581 const size_t count = args->buffer_count; 3582 int err; 3583 3584 if (!check_buffer_count(count)) { 3585 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count); 3586 return -EINVAL; 3587 } 3588 3589 err = i915_gem_check_execbuffer(i915, args); 3590 if (err) 3591 return err; 3592 3593 /* Allocate extra slots for use by the command parser */ 3594 exec2_list = kvmalloc_array(count + 2, eb_element_size(), 3595 __GFP_NOWARN | GFP_KERNEL); 3596 if (exec2_list == NULL) { 3597 drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", 3598 count); 3599 return -ENOMEM; 3600 } 3601 if (copy_from_user(exec2_list, 3602 u64_to_user_ptr(args->buffers_ptr), 3603 sizeof(*exec2_list) * count)) { 3604 drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count); 3605 kvfree(exec2_list); 3606 return -EFAULT; 3607 } 3608 3609 err = i915_gem_do_execbuffer(dev, file, args, exec2_list); 3610 3611 /* 3612 * Now that we have begun execution of the batchbuffer, we ignore 3613 * any new error after this point. Also given that we have already 3614 * updated the associated relocations, we try to write out the current 3615 * object locations irrespective of any error. 3616 */ 3617 if (args->flags & __EXEC_HAS_RELOC) { 3618 struct drm_i915_gem_exec_object2 __user *user_exec_list = 3619 u64_to_user_ptr(args->buffers_ptr); 3620 unsigned int i; 3621 3622 /* Copy the new buffer offsets back to the user's exec list. */ 3623 /* 3624 * Note: count * sizeof(*user_exec_list) does not overflow, 3625 * because we checked 'count' in check_buffer_count(). 3626 * 3627 * And this range already got effectively checked earlier 3628 * when we did the "copy_from_user()" above. 3629 */ 3630 if (!user_write_access_begin(user_exec_list, 3631 count * sizeof(*user_exec_list))) 3632 goto end; 3633 3634 for (i = 0; i < args->buffer_count; i++) { 3635 if (!(exec2_list[i].offset & UPDATE)) 3636 continue; 3637 3638 exec2_list[i].offset = 3639 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK); 3640 unsafe_put_user(exec2_list[i].offset, 3641 &user_exec_list[i].offset, 3642 end_user); 3643 } 3644 end_user: 3645 user_write_access_end(); 3646 end:; 3647 } 3648 3649 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS; 3650 kvfree(exec2_list); 3651 return err; 3652 } 3653