1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Shobhit Kumar <shobhit.kumar@intel.com> 25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/string_helpers.h> 30 31 #include "i915_drv.h" 32 #include "intel_de.h" 33 #include "intel_display_types.h" 34 #include "intel_dsi.h" 35 #include "vlv_dsi_pll.h" 36 #include "vlv_dsi_pll_regs.h" 37 #include "vlv_sideband.h" 38 39 static const u16 lfsr_converts[] = { 40 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 41 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 42 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ 43 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ 44 }; 45 46 /* Get DSI clock from pixel clock */ 47 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, 48 int lane_count) 49 { 50 u32 dsi_clk_khz; 51 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt); 52 53 /* DSI data rate = pixel clock * bits per pixel / lane count 54 pixel clock is converted from KHz to Hz */ 55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 56 57 return dsi_clk_khz; 58 } 59 60 static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 61 struct intel_crtc_state *config, 62 int target_dsi_clk) 63 { 64 unsigned int m_min, m_max, p_min = 2, p_max = 6; 65 unsigned int m, n, p; 66 unsigned int calc_m, calc_p; 67 int delta, ref_clk; 68 69 /* target_dsi_clk is expected in kHz */ 70 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { 71 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); 72 return -ECHRNG; 73 } 74 75 if (IS_CHERRYVIEW(dev_priv)) { 76 ref_clk = 100000; 77 n = 4; 78 m_min = 70; 79 m_max = 96; 80 } else { 81 ref_clk = 25000; 82 n = 1; 83 m_min = 62; 84 m_max = 92; 85 } 86 87 calc_p = p_min; 88 calc_m = m_min; 89 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); 90 91 for (m = m_min; m <= m_max && delta; m++) { 92 for (p = p_min; p <= p_max && delta; p++) { 93 /* 94 * Find the optimal m and p divisors with minimal delta 95 * +/- the required clock 96 */ 97 int calc_dsi_clk = (m * ref_clk) / (p * n); 98 int d = abs(target_dsi_clk - calc_dsi_clk); 99 if (d < delta) { 100 delta = d; 101 calc_m = m; 102 calc_p = p; 103 } 104 } 105 } 106 107 /* register has log2(N1), this works fine for powers of two */ 108 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 109 config->dsi_pll.div = 110 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT | 111 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT; 112 113 return 0; 114 } 115 116 /* 117 * XXX: The muxing and gating is hard coded for now. Need to add support for 118 * sharing PLLs with two DSI outputs. 119 */ 120 int vlv_dsi_pll_compute(struct intel_encoder *encoder, 121 struct intel_crtc_state *config) 122 { 123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 124 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 125 int ret; 126 u32 dsi_clk; 127 128 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 129 intel_dsi->lane_count); 130 131 ret = dsi_calc_mnp(dev_priv, config, dsi_clk); 132 if (ret) { 133 drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n"); 134 return ret; 135 } 136 137 if (intel_dsi->ports & (1 << PORT_A)) 138 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 139 140 if (intel_dsi->ports & (1 << PORT_C)) 141 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 142 143 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; 144 145 drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n", 146 config->dsi_pll.div, config->dsi_pll.ctrl); 147 148 return 0; 149 } 150 151 void vlv_dsi_pll_enable(struct intel_encoder *encoder, 152 const struct intel_crtc_state *config) 153 { 154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 155 156 drm_dbg_kms(&dev_priv->drm, "\n"); 157 158 vlv_cck_get(dev_priv); 159 160 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 161 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); 162 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 163 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); 164 165 /* wait at least 0.5 us after ungating before enabling VCO, 166 * allow hrtimer subsystem optimization by relaxing timing 167 */ 168 usleep_range(10, 50); 169 170 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); 171 172 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 173 DSI_PLL_LOCK, 20)) { 174 175 vlv_cck_put(dev_priv); 176 drm_err(&dev_priv->drm, "DSI PLL lock failed\n"); 177 return; 178 } 179 vlv_cck_put(dev_priv); 180 181 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); 182 } 183 184 void vlv_dsi_pll_disable(struct intel_encoder *encoder) 185 { 186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 187 u32 tmp; 188 189 drm_dbg_kms(&dev_priv->drm, "\n"); 190 191 vlv_cck_get(dev_priv); 192 193 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 194 tmp &= ~DSI_PLL_VCO_EN; 195 tmp |= DSI_PLL_LDO_GATE; 196 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 197 198 vlv_cck_put(dev_priv); 199 } 200 201 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) 202 { 203 bool enabled; 204 u32 val; 205 u32 mask; 206 207 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; 208 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 209 enabled = (val & mask) == mask; 210 211 if (!enabled) 212 return false; 213 214 /* 215 * Dividers must be programmed with valid values. As per BSEPC, for 216 * GEMINLAKE only PORT A divider values are checked while for BXT 217 * both divider values are validated. Check this here for 218 * paranoia, since BIOS is known to misconfigure PLLs in this way at 219 * times, and since accessing DSI registers with invalid dividers 220 * causes a system hang. 221 */ 222 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); 223 if (IS_GEMINILAKE(dev_priv)) { 224 if (!(val & BXT_DSIA_16X_MASK)) { 225 drm_dbg(&dev_priv->drm, 226 "Invalid PLL divider (%08x)\n", val); 227 enabled = false; 228 } 229 } else { 230 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { 231 drm_dbg(&dev_priv->drm, 232 "Invalid PLL divider (%08x)\n", val); 233 enabled = false; 234 } 235 } 236 237 return enabled; 238 } 239 240 void bxt_dsi_pll_disable(struct intel_encoder *encoder) 241 { 242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 243 u32 val; 244 245 drm_dbg_kms(&dev_priv->drm, "\n"); 246 247 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 248 val &= ~BXT_DSI_PLL_DO_ENABLE; 249 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); 250 251 /* 252 * PLL lock should deassert within 200us. 253 * Wait up to 1ms before timing out. 254 */ 255 if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE, 256 BXT_DSI_PLL_LOCKED, 1)) 257 drm_err(&dev_priv->drm, 258 "Timeout waiting for PLL lock deassertion\n"); 259 } 260 261 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, 262 struct intel_crtc_state *config) 263 { 264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 265 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 266 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 267 u32 dsi_clock, pclk; 268 u32 pll_ctl, pll_div; 269 u32 m = 0, p = 0, n; 270 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; 271 int i; 272 273 drm_dbg_kms(&dev_priv->drm, "\n"); 274 275 vlv_cck_get(dev_priv); 276 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 277 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 278 vlv_cck_put(dev_priv); 279 280 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; 281 config->dsi_pll.div = pll_div; 282 283 /* mask out other bits and extract the P1 divisor */ 284 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 285 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 286 287 /* N1 divisor */ 288 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; 289 n = 1 << n; /* register has log2(N1) */ 290 291 /* mask out the other bits and extract the M1 divisor */ 292 pll_div &= DSI_PLL_M1_DIV_MASK; 293 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 294 295 while (pll_ctl) { 296 pll_ctl = pll_ctl >> 1; 297 p++; 298 } 299 p--; 300 301 if (!p) { 302 drm_err(&dev_priv->drm, "wrong P1 divisor\n"); 303 return 0; 304 } 305 306 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 307 if (lfsr_converts[i] == pll_div) 308 break; 309 } 310 311 if (i == ARRAY_SIZE(lfsr_converts)) { 312 drm_err(&dev_priv->drm, "wrong m_seed programmed\n"); 313 return 0; 314 } 315 316 m = i + 62; 317 318 dsi_clock = (m * refclk) / (p * n); 319 320 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); 321 322 return pclk; 323 } 324 325 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, 326 struct intel_crtc_state *config) 327 { 328 u32 pclk; 329 u32 dsi_clk; 330 u32 dsi_ratio; 331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 333 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 334 335 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); 336 337 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 338 339 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; 340 341 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); 342 343 drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk); 344 return pclk; 345 } 346 347 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 348 { 349 u32 temp; 350 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 351 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 352 353 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); 354 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 355 intel_de_write(dev_priv, MIPI_CTRL(port), 356 temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); 357 } 358 359 static void glk_dsi_program_esc_clock(struct drm_device *dev, 360 const struct intel_crtc_state *config) 361 { 362 struct drm_i915_private *dev_priv = to_i915(dev); 363 u32 dsi_rate = 0; 364 u32 pll_ratio = 0; 365 u32 ddr_clk = 0; 366 u32 div1_value = 0; 367 u32 div2_value = 0; 368 u32 txesc1_div = 0; 369 u32 txesc2_div = 0; 370 371 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 372 373 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 374 375 ddr_clk = dsi_rate / 2; 376 377 /* Variable divider value */ 378 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000); 379 380 /* Calculate TXESC1 divider */ 381 if (div1_value <= 10) 382 txesc1_div = div1_value; 383 else if ((div1_value > 10) && (div1_value <= 20)) 384 txesc1_div = DIV_ROUND_UP(div1_value, 2); 385 else if ((div1_value > 20) && (div1_value <= 30)) 386 txesc1_div = DIV_ROUND_UP(div1_value, 4); 387 else if ((div1_value > 30) && (div1_value <= 40)) 388 txesc1_div = DIV_ROUND_UP(div1_value, 6); 389 else if ((div1_value > 40) && (div1_value <= 50)) 390 txesc1_div = DIV_ROUND_UP(div1_value, 8); 391 else 392 txesc1_div = 10; 393 394 /* Calculate TXESC2 divider */ 395 div2_value = DIV_ROUND_UP(div1_value, txesc1_div); 396 397 txesc2_div = min_t(u32, div2_value, 10); 398 399 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, 400 (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); 401 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, 402 (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); 403 } 404 405 /* Program BXT Mipi clocks and dividers */ 406 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, 407 const struct intel_crtc_state *config) 408 { 409 struct drm_i915_private *dev_priv = to_i915(dev); 410 u32 tmp; 411 u32 dsi_rate = 0; 412 u32 pll_ratio = 0; 413 u32 rx_div; 414 u32 tx_div; 415 u32 rx_div_upper; 416 u32 rx_div_lower; 417 u32 mipi_8by3_divider; 418 419 /* Clear old configurations */ 420 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); 421 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 422 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 423 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 424 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 425 426 /* Get the current DSI rate(actual) */ 427 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 428 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 429 430 /* 431 * tx clock should be <= 20MHz and the div value must be 432 * subtracted by 1 as per bspec 433 */ 434 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; 435 /* 436 * rx clock should be <= 150MHz and the div value must be 437 * subtracted by 1 as per bspec 438 */ 439 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; 440 441 /* 442 * rx divider value needs to be updated in the 443 * two differnt bit fields in the register hence splitting the 444 * rx divider value accordingly 445 */ 446 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; 447 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; 448 449 mipi_8by3_divider = 0x2; 450 451 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); 452 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); 453 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); 454 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); 455 456 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 457 } 458 459 int bxt_dsi_pll_compute(struct intel_encoder *encoder, 460 struct intel_crtc_state *config) 461 { 462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 463 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 464 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max; 465 u32 dsi_clk; 466 467 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 468 intel_dsi->lane_count); 469 470 /* 471 * From clock diagram, to get PLL ratio divider, divide double of DSI 472 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to 473 * round 'up' the result 474 */ 475 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); 476 477 if (IS_BROXTON(dev_priv)) { 478 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN; 479 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX; 480 } else { 481 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN; 482 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX; 483 } 484 485 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) { 486 drm_err(&dev_priv->drm, 487 "Can't get a suitable ratio from DSI PLL ratios\n"); 488 return -ECHRNG; 489 } else 490 drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n"); 491 492 /* 493 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x 494 * Spec says both have to be programmed, even if one is not getting 495 * used. Configure MIPI_CLOCK_CTL dividers in modeset 496 */ 497 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2; 498 499 /* As per recommendation from hardware team, 500 * Prog PVD ratio =1 if dsi ratio <= 50 501 */ 502 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50) 503 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1; 504 505 return 0; 506 } 507 508 void bxt_dsi_pll_enable(struct intel_encoder *encoder, 509 const struct intel_crtc_state *config) 510 { 511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 513 enum port port; 514 u32 val; 515 516 drm_dbg_kms(&dev_priv->drm, "\n"); 517 518 /* Configure PLL vales */ 519 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); 520 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); 521 522 /* Program TX, RX, Dphy clocks */ 523 if (IS_BROXTON(dev_priv)) { 524 for_each_dsi_port(port, intel_dsi->ports) 525 bxt_dsi_program_clocks(encoder->base.dev, port, config); 526 } else { 527 glk_dsi_program_esc_clock(encoder->base.dev, config); 528 } 529 530 /* Enable DSI PLL */ 531 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 532 val |= BXT_DSI_PLL_DO_ENABLE; 533 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); 534 535 /* Timeout and fail if PLL not locked */ 536 if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE, 537 BXT_DSI_PLL_LOCKED, 1)) { 538 drm_err(&dev_priv->drm, 539 "Timed out waiting for DSI PLL to lock\n"); 540 return; 541 } 542 543 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); 544 } 545 546 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 547 { 548 u32 tmp; 549 struct drm_device *dev = encoder->base.dev; 550 struct drm_i915_private *dev_priv = to_i915(dev); 551 552 /* Clear old configurations */ 553 if (IS_BROXTON(dev_priv)) { 554 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); 555 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 556 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 557 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 558 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 559 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 560 } else { 561 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); 562 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK; 563 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp); 564 565 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); 566 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK; 567 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp); 568 } 569 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 570 } 571 572 static void assert_dsi_pll(struct drm_i915_private *i915, bool state) 573 { 574 bool cur_state; 575 576 vlv_cck_get(i915); 577 cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; 578 vlv_cck_put(i915); 579 580 I915_STATE_WARN(cur_state != state, 581 "DSI PLL state assertion failure (expected %s, current %s)\n", 582 str_on_off(state), str_on_off(cur_state)); 583 } 584 585 void assert_dsi_pll_enabled(struct drm_i915_private *i915) 586 { 587 assert_dsi_pll(i915, true); 588 } 589 590 void assert_dsi_pll_disabled(struct drm_i915_private *i915) 591 { 592 assert_dsi_pll(i915, false); 593 } 594