1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Shobhit Kumar <shobhit.kumar@intel.com> 25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> 26 */ 27 28 #include <linux/kernel.h> 29 30 #include "i915_drv.h" 31 #include "intel_de.h" 32 #include "intel_display_types.h" 33 #include "intel_dsi.h" 34 #include "vlv_dsi_pll.h" 35 #include "vlv_dsi_pll_regs.h" 36 #include "vlv_sideband.h" 37 38 static const u16 lfsr_converts[] = { 39 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 40 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 41 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ 42 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ 43 }; 44 45 /* Get DSI clock from pixel clock */ 46 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, 47 int lane_count) 48 { 49 u32 dsi_clk_khz; 50 u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt); 51 52 /* DSI data rate = pixel clock * bits per pixel / lane count 53 pixel clock is converted from KHz to Hz */ 54 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 55 56 return dsi_clk_khz; 57 } 58 59 static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 60 struct intel_crtc_state *config, 61 int target_dsi_clk) 62 { 63 unsigned int m_min, m_max, p_min = 2, p_max = 6; 64 unsigned int m, n, p; 65 unsigned int calc_m, calc_p; 66 int delta, ref_clk; 67 68 /* target_dsi_clk is expected in kHz */ 69 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { 70 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); 71 return -ECHRNG; 72 } 73 74 if (IS_CHERRYVIEW(dev_priv)) { 75 ref_clk = 100000; 76 n = 4; 77 m_min = 70; 78 m_max = 96; 79 } else { 80 ref_clk = 25000; 81 n = 1; 82 m_min = 62; 83 m_max = 92; 84 } 85 86 calc_p = p_min; 87 calc_m = m_min; 88 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); 89 90 for (m = m_min; m <= m_max && delta; m++) { 91 for (p = p_min; p <= p_max && delta; p++) { 92 /* 93 * Find the optimal m and p divisors with minimal delta 94 * +/- the required clock 95 */ 96 int calc_dsi_clk = (m * ref_clk) / (p * n); 97 int d = abs(target_dsi_clk - calc_dsi_clk); 98 if (d < delta) { 99 delta = d; 100 calc_m = m; 101 calc_p = p; 102 } 103 } 104 } 105 106 /* register has log2(N1), this works fine for powers of two */ 107 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 108 config->dsi_pll.div = 109 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT | 110 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT; 111 112 return 0; 113 } 114 115 /* 116 * XXX: The muxing and gating is hard coded for now. Need to add support for 117 * sharing PLLs with two DSI outputs. 118 */ 119 int vlv_dsi_pll_compute(struct intel_encoder *encoder, 120 struct intel_crtc_state *config) 121 { 122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 123 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 124 int ret; 125 u32 dsi_clk; 126 127 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 128 intel_dsi->lane_count); 129 130 ret = dsi_calc_mnp(dev_priv, config, dsi_clk); 131 if (ret) { 132 drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n"); 133 return ret; 134 } 135 136 if (intel_dsi->ports & (1 << PORT_A)) 137 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 138 139 if (intel_dsi->ports & (1 << PORT_C)) 140 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 141 142 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; 143 144 drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n", 145 config->dsi_pll.div, config->dsi_pll.ctrl); 146 147 return 0; 148 } 149 150 void vlv_dsi_pll_enable(struct intel_encoder *encoder, 151 const struct intel_crtc_state *config) 152 { 153 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 154 155 drm_dbg_kms(&dev_priv->drm, "\n"); 156 157 vlv_cck_get(dev_priv); 158 159 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 160 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); 161 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 162 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); 163 164 /* wait at least 0.5 us after ungating before enabling VCO, 165 * allow hrtimer subsystem optimization by relaxing timing 166 */ 167 usleep_range(10, 50); 168 169 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); 170 171 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 172 DSI_PLL_LOCK, 20)) { 173 174 vlv_cck_put(dev_priv); 175 drm_err(&dev_priv->drm, "DSI PLL lock failed\n"); 176 return; 177 } 178 vlv_cck_put(dev_priv); 179 180 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); 181 } 182 183 void vlv_dsi_pll_disable(struct intel_encoder *encoder) 184 { 185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 186 u32 tmp; 187 188 drm_dbg_kms(&dev_priv->drm, "\n"); 189 190 vlv_cck_get(dev_priv); 191 192 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 193 tmp &= ~DSI_PLL_VCO_EN; 194 tmp |= DSI_PLL_LDO_GATE; 195 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 196 197 vlv_cck_put(dev_priv); 198 } 199 200 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) 201 { 202 bool enabled; 203 u32 val; 204 u32 mask; 205 206 mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; 207 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 208 enabled = (val & mask) == mask; 209 210 if (!enabled) 211 return false; 212 213 /* 214 * Dividers must be programmed with valid values. As per BSEPC, for 215 * GEMINLAKE only PORT A divider values are checked while for BXT 216 * both divider values are validated. Check this here for 217 * paranoia, since BIOS is known to misconfigure PLLs in this way at 218 * times, and since accessing DSI registers with invalid dividers 219 * causes a system hang. 220 */ 221 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); 222 if (IS_GEMINILAKE(dev_priv)) { 223 if (!(val & BXT_DSIA_16X_MASK)) { 224 drm_dbg(&dev_priv->drm, 225 "Invalid PLL divider (%08x)\n", val); 226 enabled = false; 227 } 228 } else { 229 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { 230 drm_dbg(&dev_priv->drm, 231 "Invalid PLL divider (%08x)\n", val); 232 enabled = false; 233 } 234 } 235 236 return enabled; 237 } 238 239 void bxt_dsi_pll_disable(struct intel_encoder *encoder) 240 { 241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 242 u32 val; 243 244 drm_dbg_kms(&dev_priv->drm, "\n"); 245 246 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 247 val &= ~BXT_DSI_PLL_DO_ENABLE; 248 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); 249 250 /* 251 * PLL lock should deassert within 200us. 252 * Wait up to 1ms before timing out. 253 */ 254 if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE, 255 BXT_DSI_PLL_LOCKED, 1)) 256 drm_err(&dev_priv->drm, 257 "Timeout waiting for PLL lock deassertion\n"); 258 } 259 260 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, 261 struct intel_crtc_state *config) 262 { 263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 264 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 265 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 266 u32 dsi_clock, pclk; 267 u32 pll_ctl, pll_div; 268 u32 m = 0, p = 0, n; 269 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; 270 int i; 271 272 drm_dbg_kms(&dev_priv->drm, "\n"); 273 274 vlv_cck_get(dev_priv); 275 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 276 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 277 vlv_cck_put(dev_priv); 278 279 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; 280 config->dsi_pll.div = pll_div; 281 282 /* mask out other bits and extract the P1 divisor */ 283 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 284 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 285 286 /* N1 divisor */ 287 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; 288 n = 1 << n; /* register has log2(N1) */ 289 290 /* mask out the other bits and extract the M1 divisor */ 291 pll_div &= DSI_PLL_M1_DIV_MASK; 292 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 293 294 while (pll_ctl) { 295 pll_ctl = pll_ctl >> 1; 296 p++; 297 } 298 p--; 299 300 if (!p) { 301 drm_err(&dev_priv->drm, "wrong P1 divisor\n"); 302 return 0; 303 } 304 305 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 306 if (lfsr_converts[i] == pll_div) 307 break; 308 } 309 310 if (i == ARRAY_SIZE(lfsr_converts)) { 311 drm_err(&dev_priv->drm, "wrong m_seed programmed\n"); 312 return 0; 313 } 314 315 m = i + 62; 316 317 dsi_clock = (m * refclk) / (p * n); 318 319 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); 320 321 return pclk; 322 } 323 324 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, 325 struct intel_crtc_state *config) 326 { 327 u32 pclk; 328 u32 dsi_clk; 329 u32 dsi_ratio; 330 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 331 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 332 int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 333 334 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); 335 336 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 337 338 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; 339 340 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); 341 342 drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk); 343 return pclk; 344 } 345 346 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 347 { 348 u32 temp; 349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 350 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 351 352 temp = intel_de_read(dev_priv, MIPI_CTRL(port)); 353 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 354 intel_de_write(dev_priv, MIPI_CTRL(port), 355 temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); 356 } 357 358 static void glk_dsi_program_esc_clock(struct drm_device *dev, 359 const struct intel_crtc_state *config) 360 { 361 struct drm_i915_private *dev_priv = to_i915(dev); 362 u32 dsi_rate = 0; 363 u32 pll_ratio = 0; 364 u32 ddr_clk = 0; 365 u32 div1_value = 0; 366 u32 div2_value = 0; 367 u32 txesc1_div = 0; 368 u32 txesc2_div = 0; 369 370 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 371 372 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 373 374 ddr_clk = dsi_rate / 2; 375 376 /* Variable divider value */ 377 div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000); 378 379 /* Calculate TXESC1 divider */ 380 if (div1_value <= 10) 381 txesc1_div = div1_value; 382 else if ((div1_value > 10) && (div1_value <= 20)) 383 txesc1_div = DIV_ROUND_UP(div1_value, 2); 384 else if ((div1_value > 20) && (div1_value <= 30)) 385 txesc1_div = DIV_ROUND_UP(div1_value, 4); 386 else if ((div1_value > 30) && (div1_value <= 40)) 387 txesc1_div = DIV_ROUND_UP(div1_value, 6); 388 else if ((div1_value > 40) && (div1_value <= 50)) 389 txesc1_div = DIV_ROUND_UP(div1_value, 8); 390 else 391 txesc1_div = 10; 392 393 /* Calculate TXESC2 divider */ 394 div2_value = DIV_ROUND_UP(div1_value, txesc1_div); 395 396 if (div2_value < 10) 397 txesc2_div = div2_value; 398 else 399 txesc2_div = 10; 400 401 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, 402 (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); 403 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, 404 (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); 405 } 406 407 /* Program BXT Mipi clocks and dividers */ 408 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, 409 const struct intel_crtc_state *config) 410 { 411 struct drm_i915_private *dev_priv = to_i915(dev); 412 u32 tmp; 413 u32 dsi_rate = 0; 414 u32 pll_ratio = 0; 415 u32 rx_div; 416 u32 tx_div; 417 u32 rx_div_upper; 418 u32 rx_div_lower; 419 u32 mipi_8by3_divider; 420 421 /* Clear old configurations */ 422 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); 423 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 424 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 425 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 426 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 427 428 /* Get the current DSI rate(actual) */ 429 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; 430 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 431 432 /* 433 * tx clock should be <= 20MHz and the div value must be 434 * subtracted by 1 as per bspec 435 */ 436 tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; 437 /* 438 * rx clock should be <= 150MHz and the div value must be 439 * subtracted by 1 as per bspec 440 */ 441 rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; 442 443 /* 444 * rx divider value needs to be updated in the 445 * two differnt bit fields in the register hence splitting the 446 * rx divider value accordingly 447 */ 448 rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; 449 rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; 450 451 mipi_8by3_divider = 0x2; 452 453 tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); 454 tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); 455 tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); 456 tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); 457 458 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 459 } 460 461 int bxt_dsi_pll_compute(struct intel_encoder *encoder, 462 struct intel_crtc_state *config) 463 { 464 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 465 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 466 u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max; 467 u32 dsi_clk; 468 469 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 470 intel_dsi->lane_count); 471 472 /* 473 * From clock diagram, to get PLL ratio divider, divide double of DSI 474 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to 475 * round 'up' the result 476 */ 477 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); 478 479 if (IS_BROXTON(dev_priv)) { 480 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN; 481 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX; 482 } else { 483 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN; 484 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX; 485 } 486 487 if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) { 488 drm_err(&dev_priv->drm, 489 "Can't get a suitable ratio from DSI PLL ratios\n"); 490 return -ECHRNG; 491 } else 492 drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n"); 493 494 /* 495 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x 496 * Spec says both have to be programmed, even if one is not getting 497 * used. Configure MIPI_CLOCK_CTL dividers in modeset 498 */ 499 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2; 500 501 /* As per recommendation from hardware team, 502 * Prog PVD ratio =1 if dsi ratio <= 50 503 */ 504 if (IS_BROXTON(dev_priv) && dsi_ratio <= 50) 505 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1; 506 507 return 0; 508 } 509 510 void bxt_dsi_pll_enable(struct intel_encoder *encoder, 511 const struct intel_crtc_state *config) 512 { 513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 514 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 515 enum port port; 516 u32 val; 517 518 drm_dbg_kms(&dev_priv->drm, "\n"); 519 520 /* Configure PLL vales */ 521 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); 522 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); 523 524 /* Program TX, RX, Dphy clocks */ 525 if (IS_BROXTON(dev_priv)) { 526 for_each_dsi_port(port, intel_dsi->ports) 527 bxt_dsi_program_clocks(encoder->base.dev, port, config); 528 } else { 529 glk_dsi_program_esc_clock(encoder->base.dev, config); 530 } 531 532 /* Enable DSI PLL */ 533 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); 534 val |= BXT_DSI_PLL_DO_ENABLE; 535 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); 536 537 /* Timeout and fail if PLL not locked */ 538 if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE, 539 BXT_DSI_PLL_LOCKED, 1)) { 540 drm_err(&dev_priv->drm, 541 "Timed out waiting for DSI PLL to lock\n"); 542 return; 543 } 544 545 drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); 546 } 547 548 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 549 { 550 u32 tmp; 551 struct drm_device *dev = encoder->base.dev; 552 struct drm_i915_private *dev_priv = to_i915(dev); 553 554 /* Clear old configurations */ 555 if (IS_BROXTON(dev_priv)) { 556 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); 557 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 558 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); 559 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); 560 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); 561 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); 562 } else { 563 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); 564 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK; 565 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp); 566 567 tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); 568 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK; 569 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp); 570 } 571 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 572 } 573 574 static void assert_dsi_pll(struct drm_i915_private *i915, bool state) 575 { 576 bool cur_state; 577 578 vlv_cck_get(i915); 579 cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; 580 vlv_cck_put(i915); 581 582 I915_STATE_WARN(cur_state != state, 583 "DSI PLL state assertion failure (expected %s, current %s)\n", 584 onoff(state), onoff(cur_state)); 585 } 586 587 void assert_dsi_pll_enabled(struct drm_i915_private *i915) 588 { 589 assert_dsi_pll(i915, true); 590 } 591 592 void assert_dsi_pll_disabled(struct drm_i915_private *i915) 593 { 594 assert_dsi_pll(i915, false); 595 } 596