1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/slab.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_mipi_dsi.h> 32 33 #include "i915_drv.h" 34 #include "intel_atomic.h" 35 #include "intel_connector.h" 36 #include "intel_display_types.h" 37 #include "intel_dsi.h" 38 #include "intel_fifo_underrun.h" 39 #include "intel_panel.h" 40 #include "intel_sideband.h" 41 42 /* return pixels in terms of txbyteclkhs */ 43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 44 u16 burst_mode_ratio) 45 { 46 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 47 8 * 100), lane_count); 48 } 49 50 /* return pixels equvalent to txbyteclkhs */ 51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 52 u16 burst_mode_ratio) 53 { 54 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 55 (bpp * burst_mode_ratio)); 56 } 57 58 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 59 { 60 /* It just so happens the VBT matches register contents. */ 61 switch (fmt) { 62 case VID_MODE_FORMAT_RGB888: 63 return MIPI_DSI_FMT_RGB888; 64 case VID_MODE_FORMAT_RGB666: 65 return MIPI_DSI_FMT_RGB666; 66 case VID_MODE_FORMAT_RGB666_PACKED: 67 return MIPI_DSI_FMT_RGB666_PACKED; 68 case VID_MODE_FORMAT_RGB565: 69 return MIPI_DSI_FMT_RGB565; 70 default: 71 MISSING_CASE(fmt); 72 return MIPI_DSI_FMT_RGB666; 73 } 74 } 75 76 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 77 { 78 struct drm_encoder *encoder = &intel_dsi->base.base; 79 struct drm_device *dev = encoder->dev; 80 struct drm_i915_private *dev_priv = to_i915(dev); 81 u32 mask; 82 83 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 84 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 85 86 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), 87 mask, 100)) 88 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); 89 } 90 91 static void write_data(struct drm_i915_private *dev_priv, 92 i915_reg_t reg, 93 const u8 *data, u32 len) 94 { 95 u32 i, j; 96 97 for (i = 0; i < len; i += 4) { 98 u32 val = 0; 99 100 for (j = 0; j < min_t(u32, len - i, 4); j++) 101 val |= *data++ << 8 * j; 102 103 intel_de_write(dev_priv, reg, val); 104 } 105 } 106 107 static void read_data(struct drm_i915_private *dev_priv, 108 i915_reg_t reg, 109 u8 *data, u32 len) 110 { 111 u32 i, j; 112 113 for (i = 0; i < len; i += 4) { 114 u32 val = intel_de_read(dev_priv, reg); 115 116 for (j = 0; j < min_t(u32, len - i, 4); j++) 117 *data++ = val >> 8 * j; 118 } 119 } 120 121 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 122 const struct mipi_dsi_msg *msg) 123 { 124 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 125 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; 126 struct drm_i915_private *dev_priv = to_i915(dev); 127 enum port port = intel_dsi_host->port; 128 struct mipi_dsi_packet packet; 129 ssize_t ret; 130 const u8 *header, *data; 131 i915_reg_t data_reg, ctrl_reg; 132 u32 data_mask, ctrl_mask; 133 134 ret = mipi_dsi_create_packet(&packet, msg); 135 if (ret < 0) 136 return ret; 137 138 header = packet.header; 139 data = packet.payload; 140 141 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 142 data_reg = MIPI_LP_GEN_DATA(port); 143 data_mask = LP_DATA_FIFO_FULL; 144 ctrl_reg = MIPI_LP_GEN_CTRL(port); 145 ctrl_mask = LP_CTRL_FIFO_FULL; 146 } else { 147 data_reg = MIPI_HS_GEN_DATA(port); 148 data_mask = HS_DATA_FIFO_FULL; 149 ctrl_reg = MIPI_HS_GEN_CTRL(port); 150 ctrl_mask = HS_CTRL_FIFO_FULL; 151 } 152 153 /* note: this is never true for reads */ 154 if (packet.payload_length) { 155 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 156 data_mask, 50)) 157 drm_err(&dev_priv->drm, 158 "Timeout waiting for HS/LP DATA FIFO !full\n"); 159 160 write_data(dev_priv, data_reg, packet.payload, 161 packet.payload_length); 162 } 163 164 if (msg->rx_len) { 165 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 166 GEN_READ_DATA_AVAIL); 167 } 168 169 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), 170 ctrl_mask, 50)) { 171 drm_err(&dev_priv->drm, 172 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 173 } 174 175 intel_de_write(dev_priv, ctrl_reg, 176 header[2] << 16 | header[1] << 8 | header[0]); 177 178 /* ->rx_len is set only for reads */ 179 if (msg->rx_len) { 180 data_mask = GEN_READ_DATA_AVAIL; 181 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), 182 data_mask, 50)) 183 drm_err(&dev_priv->drm, 184 "Timeout waiting for read data.\n"); 185 186 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); 187 } 188 189 /* XXX: fix for reads and writes */ 190 return 4 + packet.payload_length; 191 } 192 193 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 194 struct mipi_dsi_device *dsi) 195 { 196 return 0; 197 } 198 199 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 200 struct mipi_dsi_device *dsi) 201 { 202 return 0; 203 } 204 205 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 206 .attach = intel_dsi_host_attach, 207 .detach = intel_dsi_host_detach, 208 .transfer = intel_dsi_host_transfer, 209 }; 210 211 /* 212 * send a video mode command 213 * 214 * XXX: commands with data in MIPI_DPI_DATA? 215 */ 216 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 217 enum port port) 218 { 219 struct drm_encoder *encoder = &intel_dsi->base.base; 220 struct drm_device *dev = encoder->dev; 221 struct drm_i915_private *dev_priv = to_i915(dev); 222 u32 mask; 223 224 /* XXX: pipe, hs */ 225 if (hs) 226 cmd &= ~DPI_LP_MODE; 227 else 228 cmd |= DPI_LP_MODE; 229 230 /* clear bit */ 231 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); 232 233 /* XXX: old code skips write if control unchanged */ 234 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) 235 drm_dbg_kms(&dev_priv->drm, 236 "Same special packet %02x twice in a row.\n", cmd); 237 238 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); 239 240 mask = SPL_PKT_SENT_INTERRUPT; 241 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) 242 drm_err(&dev_priv->drm, 243 "Video mode command 0x%08x send failed.\n", cmd); 244 245 return 0; 246 } 247 248 static void band_gap_reset(struct drm_i915_private *dev_priv) 249 { 250 vlv_flisdsi_get(dev_priv); 251 252 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 253 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 254 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 255 udelay(150); 256 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 257 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 258 259 vlv_flisdsi_put(dev_priv); 260 } 261 262 static int intel_dsi_compute_config(struct intel_encoder *encoder, 263 struct intel_crtc_state *pipe_config, 264 struct drm_connector_state *conn_state) 265 { 266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 267 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 268 base); 269 struct intel_connector *intel_connector = intel_dsi->attached_connector; 270 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 271 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 272 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 273 int ret; 274 275 drm_dbg_kms(&dev_priv->drm, "\n"); 276 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 277 278 if (fixed_mode) { 279 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 280 281 if (HAS_GMCH(dev_priv)) 282 intel_gmch_panel_fitting(crtc, pipe_config, 283 conn_state->scaling_mode); 284 else 285 intel_pch_panel_fitting(crtc, pipe_config, 286 conn_state->scaling_mode); 287 } 288 289 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 290 return -EINVAL; 291 292 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 293 adjusted_mode->flags = 0; 294 295 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 296 pipe_config->pipe_bpp = 24; 297 else 298 pipe_config->pipe_bpp = 18; 299 300 if (IS_GEN9_LP(dev_priv)) { 301 /* Enable Frame time stamp based scanline reporting */ 302 adjusted_mode->private_flags |= 303 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 304 305 /* Dual link goes to DSI transcoder A. */ 306 if (intel_dsi->ports == BIT(PORT_C)) 307 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 308 else 309 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 310 311 ret = bxt_dsi_pll_compute(encoder, pipe_config); 312 if (ret) 313 return -EINVAL; 314 } else { 315 ret = vlv_dsi_pll_compute(encoder, pipe_config); 316 if (ret) 317 return -EINVAL; 318 } 319 320 pipe_config->clock_set = true; 321 322 return 0; 323 } 324 325 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 326 { 327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 328 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 329 enum port port; 330 u32 tmp; 331 bool cold_boot = false; 332 333 /* Set the MIPI mode 334 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 335 * Power ON MIPI IO first and then write into IO reset and LP wake bits 336 */ 337 for_each_dsi_port(port, intel_dsi->ports) { 338 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 339 intel_de_write(dev_priv, MIPI_CTRL(port), 340 tmp | GLK_MIPIIO_ENABLE); 341 } 342 343 /* Put the IO into reset */ 344 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 345 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 346 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 347 348 /* Program LP Wake */ 349 for_each_dsi_port(port, intel_dsi->ports) { 350 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 351 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 352 tmp &= ~GLK_LP_WAKE; 353 else 354 tmp |= GLK_LP_WAKE; 355 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 356 } 357 358 /* Wait for Pwr ACK */ 359 for_each_dsi_port(port, intel_dsi->ports) { 360 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 361 GLK_MIPIIO_PORT_POWERED, 20)) 362 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); 363 } 364 365 /* Check for cold boot scenario */ 366 for_each_dsi_port(port, intel_dsi->ports) { 367 cold_boot |= 368 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); 369 } 370 371 return cold_boot; 372 } 373 374 static void glk_dsi_device_ready(struct intel_encoder *encoder) 375 { 376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 377 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 378 enum port port; 379 u32 val; 380 381 /* Wait for MIPI PHY status bit to set */ 382 for_each_dsi_port(port, intel_dsi->ports) { 383 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 384 GLK_PHY_STATUS_PORT_READY, 20)) 385 drm_err(&dev_priv->drm, "PHY is not ON\n"); 386 } 387 388 /* Get IO out of reset */ 389 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 390 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 391 val | GLK_MIPIIO_RESET_RELEASED); 392 393 /* Get IO out of Low power state*/ 394 for_each_dsi_port(port, intel_dsi->ports) { 395 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { 396 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 397 val &= ~ULPS_STATE_MASK; 398 val |= DEVICE_READY; 399 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 400 usleep_range(10, 15); 401 } else { 402 /* Enter ULPS */ 403 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 404 val &= ~ULPS_STATE_MASK; 405 val |= (ULPS_STATE_ENTER | DEVICE_READY); 406 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 407 408 /* Wait for ULPS active */ 409 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 410 GLK_ULPS_NOT_ACTIVE, 20)) 411 drm_err(&dev_priv->drm, "ULPS not active\n"); 412 413 /* Exit ULPS */ 414 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 415 val &= ~ULPS_STATE_MASK; 416 val |= (ULPS_STATE_EXIT | DEVICE_READY); 417 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 418 419 /* Enter Normal Mode */ 420 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 421 val &= ~ULPS_STATE_MASK; 422 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 423 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 424 425 val = intel_de_read(dev_priv, MIPI_CTRL(port)); 426 val &= ~GLK_LP_WAKE; 427 intel_de_write(dev_priv, MIPI_CTRL(port), val); 428 } 429 } 430 431 /* Wait for Stop state */ 432 for_each_dsi_port(port, intel_dsi->ports) { 433 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), 434 GLK_DATA_LANE_STOP_STATE, 20)) 435 drm_err(&dev_priv->drm, 436 "Date lane not in STOP state\n"); 437 } 438 439 /* Wait for AFE LATCH */ 440 for_each_dsi_port(port, intel_dsi->ports) { 441 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), 442 AFE_LATCHOUT, 20)) 443 drm_err(&dev_priv->drm, 444 "D-PHY not entering LP-11 state\n"); 445 } 446 } 447 448 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 449 { 450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 451 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 452 enum port port; 453 u32 val; 454 455 drm_dbg_kms(&dev_priv->drm, "\n"); 456 457 /* Enable MIPI PHY transparent latch */ 458 for_each_dsi_port(port, intel_dsi->ports) { 459 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); 460 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), 461 val | LP_OUTPUT_HOLD); 462 usleep_range(2000, 2500); 463 } 464 465 /* Clear ULPS and set device ready */ 466 for_each_dsi_port(port, intel_dsi->ports) { 467 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 468 val &= ~ULPS_STATE_MASK; 469 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 470 usleep_range(2000, 2500); 471 val |= DEVICE_READY; 472 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 473 } 474 } 475 476 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 477 { 478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 479 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 480 enum port port; 481 u32 val; 482 483 drm_dbg_kms(&dev_priv->drm, "\n"); 484 485 vlv_flisdsi_get(dev_priv); 486 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 487 * needed everytime after power gate */ 488 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 489 vlv_flisdsi_put(dev_priv); 490 491 /* bandgap reset is needed after everytime we do power gate */ 492 band_gap_reset(dev_priv); 493 494 for_each_dsi_port(port, intel_dsi->ports) { 495 496 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 497 ULPS_STATE_ENTER); 498 usleep_range(2500, 3000); 499 500 /* Enable MIPI PHY transparent latch 501 * Common bit for both MIPI Port A & MIPI Port C 502 * No similar bit in MIPI Port C reg 503 */ 504 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); 505 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), 506 val | LP_OUTPUT_HOLD); 507 usleep_range(1000, 1500); 508 509 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 510 ULPS_STATE_EXIT); 511 usleep_range(2500, 3000); 512 513 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 514 DEVICE_READY); 515 usleep_range(2500, 3000); 516 } 517 } 518 519 static void intel_dsi_device_ready(struct intel_encoder *encoder) 520 { 521 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 522 523 if (IS_GEMINILAKE(dev_priv)) 524 glk_dsi_device_ready(encoder); 525 else if (IS_GEN9_LP(dev_priv)) 526 bxt_dsi_device_ready(encoder); 527 else 528 vlv_dsi_device_ready(encoder); 529 } 530 531 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 532 { 533 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 534 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 535 enum port port; 536 u32 val; 537 538 /* Enter ULPS */ 539 for_each_dsi_port(port, intel_dsi->ports) { 540 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); 541 val &= ~ULPS_STATE_MASK; 542 val |= (ULPS_STATE_ENTER | DEVICE_READY); 543 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); 544 } 545 546 /* Wait for MIPI PHY status bit to unset */ 547 for_each_dsi_port(port, intel_dsi->ports) { 548 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 549 GLK_PHY_STATUS_PORT_READY, 20)) 550 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 551 } 552 553 /* Wait for Pwr ACK bit to unset */ 554 for_each_dsi_port(port, intel_dsi->ports) { 555 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 556 GLK_MIPIIO_PORT_POWERED, 20)) 557 drm_err(&dev_priv->drm, 558 "MIPI IO Port is not powergated\n"); 559 } 560 } 561 562 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 563 { 564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 565 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 566 enum port port; 567 u32 tmp; 568 569 /* Put the IO into reset */ 570 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 571 tmp &= ~GLK_MIPIIO_RESET_RELEASED; 572 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); 573 574 /* Wait for MIPI PHY status bit to unset */ 575 for_each_dsi_port(port, intel_dsi->ports) { 576 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), 577 GLK_PHY_STATUS_PORT_READY, 20)) 578 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); 579 } 580 581 /* Clear MIPI mode */ 582 for_each_dsi_port(port, intel_dsi->ports) { 583 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 584 tmp &= ~GLK_MIPIIO_ENABLE; 585 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 586 } 587 } 588 589 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 590 { 591 glk_dsi_enter_low_power_mode(encoder); 592 glk_dsi_disable_mipi_io(encoder); 593 } 594 595 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 596 { 597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 598 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 599 enum port port; 600 601 drm_dbg_kms(&dev_priv->drm, "\n"); 602 for_each_dsi_port(port, intel_dsi->ports) { 603 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 604 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 605 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); 606 u32 val; 607 608 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 609 DEVICE_READY | ULPS_STATE_ENTER); 610 usleep_range(2000, 2500); 611 612 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 613 DEVICE_READY | ULPS_STATE_EXIT); 614 usleep_range(2000, 2500); 615 616 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 617 DEVICE_READY | ULPS_STATE_ENTER); 618 usleep_range(2000, 2500); 619 620 /* 621 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 622 * Port A only. MIPI Port C has no similar bit for checking. 623 */ 624 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && 625 intel_de_wait_for_clear(dev_priv, port_ctrl, 626 AFE_LATCHOUT, 30)) 627 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); 628 629 /* Disable MIPI PHY transparent latch */ 630 val = intel_de_read(dev_priv, port_ctrl); 631 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); 632 usleep_range(1000, 1500); 633 634 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); 635 usleep_range(2000, 2500); 636 } 637 } 638 639 static void intel_dsi_port_enable(struct intel_encoder *encoder, 640 const struct intel_crtc_state *crtc_state) 641 { 642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 644 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 645 enum port port; 646 647 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 648 u32 temp; 649 if (IS_GEN9_LP(dev_priv)) { 650 for_each_dsi_port(port, intel_dsi->ports) { 651 temp = intel_de_read(dev_priv, 652 MIPI_CTRL(port)); 653 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | 654 intel_dsi->pixel_overlap << 655 BXT_PIXEL_OVERLAP_CNT_SHIFT; 656 intel_de_write(dev_priv, MIPI_CTRL(port), 657 temp); 658 } 659 } else { 660 temp = intel_de_read(dev_priv, VLV_CHICKEN_3); 661 temp &= ~PIXEL_OVERLAP_CNT_MASK | 662 intel_dsi->pixel_overlap << 663 PIXEL_OVERLAP_CNT_SHIFT; 664 intel_de_write(dev_priv, VLV_CHICKEN_3, temp); 665 } 666 } 667 668 for_each_dsi_port(port, intel_dsi->ports) { 669 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 670 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 671 u32 temp; 672 673 temp = intel_de_read(dev_priv, port_ctrl); 674 675 temp &= ~LANE_CONFIGURATION_MASK; 676 temp &= ~DUAL_LINK_MODE_MASK; 677 678 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 679 temp |= (intel_dsi->dual_link - 1) 680 << DUAL_LINK_MODE_SHIFT; 681 if (IS_BROXTON(dev_priv)) 682 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 683 else 684 temp |= crtc->pipe ? 685 LANE_CONFIGURATION_DUAL_LINK_B : 686 LANE_CONFIGURATION_DUAL_LINK_A; 687 } 688 689 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 690 temp |= DITHERING_ENABLE; 691 692 /* assert ip_tg_enable signal */ 693 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); 694 intel_de_posting_read(dev_priv, port_ctrl); 695 } 696 } 697 698 static void intel_dsi_port_disable(struct intel_encoder *encoder) 699 { 700 struct drm_device *dev = encoder->base.dev; 701 struct drm_i915_private *dev_priv = to_i915(dev); 702 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 703 enum port port; 704 705 for_each_dsi_port(port, intel_dsi->ports) { 706 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? 707 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 708 u32 temp; 709 710 /* de-assert ip_tg_enable signal */ 711 temp = intel_de_read(dev_priv, port_ctrl); 712 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); 713 intel_de_posting_read(dev_priv, port_ctrl); 714 } 715 } 716 717 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 718 const struct intel_crtc_state *pipe_config); 719 static void intel_dsi_unprepare(struct intel_encoder *encoder); 720 721 /* 722 * Panel enable/disable sequences from the VBT spec. 723 * 724 * Note the spec has AssertReset / DeassertReset swapped from their 725 * usual naming. We use the normal names to avoid confusion (so below 726 * they are swapped compared to the spec). 727 * 728 * Steps starting with MIPI refer to VBT sequences, note that for v2 729 * VBTs several steps which have a VBT in v2 are expected to be handled 730 * directly by the driver, by directly driving gpios for example. 731 * 732 * v2 video mode seq v3 video mode seq command mode seq 733 * - power on - MIPIPanelPowerOn - power on 734 * - wait t1+t2 - wait t1+t2 735 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 736 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 737 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 738 * - MIPITearOn 739 * - MIPIDisplayOn 740 * - turn on DPI - turn on DPI - set pipe to dsr mode 741 * - MIPIDisplayOn - MIPIDisplayOn 742 * - wait t5 - wait t5 743 * - backlight on - MIPIBacklightOn - backlight on 744 * ... ... ... issue mem cmds ... 745 * - backlight off - MIPIBacklightOff - backlight off 746 * - wait t6 - wait t6 747 * - MIPIDisplayOff 748 * - turn off DPI - turn off DPI - disable pipe dsr mode 749 * - MIPITearOff 750 * - MIPIDisplayOff - MIPIDisplayOff 751 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 752 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 753 * - wait t3 - wait t3 754 * - power off - MIPIPanelPowerOff - power off 755 * - wait t4 - wait t4 756 */ 757 758 /* 759 * DSI port enable has to be done before pipe and plane enable, so we do it in 760 * the pre_enable hook instead of the enable hook. 761 */ 762 static void intel_dsi_pre_enable(struct intel_encoder *encoder, 763 const struct intel_crtc_state *pipe_config, 764 const struct drm_connector_state *conn_state) 765 { 766 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 767 struct drm_crtc *crtc = pipe_config->uapi.crtc; 768 struct drm_i915_private *dev_priv = to_i915(crtc->dev); 769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 770 enum pipe pipe = intel_crtc->pipe; 771 enum port port; 772 u32 val; 773 bool glk_cold_boot = false; 774 775 drm_dbg_kms(&dev_priv->drm, "\n"); 776 777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 778 779 /* 780 * The BIOS may leave the PLL in a wonky state where it doesn't 781 * lock. It needs to be fully powered down to fix it. 782 */ 783 if (IS_GEN9_LP(dev_priv)) { 784 bxt_dsi_pll_disable(encoder); 785 bxt_dsi_pll_enable(encoder, pipe_config); 786 } else { 787 vlv_dsi_pll_disable(encoder); 788 vlv_dsi_pll_enable(encoder, pipe_config); 789 } 790 791 if (IS_BROXTON(dev_priv)) { 792 /* Add MIPI IO reset programming for modeset */ 793 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 794 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 795 val | MIPIO_RST_CTRL); 796 797 /* Power up DSI regulator */ 798 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 799 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 800 } 801 802 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 803 u32 val; 804 805 /* Disable DPOunit clock gating, can stall pipe */ 806 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 807 val |= DPOUNIT_CLOCK_GATE_DISABLE; 808 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 809 } 810 811 if (!IS_GEMINILAKE(dev_priv)) 812 intel_dsi_prepare(encoder, pipe_config); 813 814 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 815 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 816 817 /* Deassert reset */ 818 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 819 820 if (IS_GEMINILAKE(dev_priv)) { 821 glk_cold_boot = glk_dsi_enable_io(encoder); 822 823 /* Prepare port in cold boot(s3/s4) scenario */ 824 if (glk_cold_boot) 825 intel_dsi_prepare(encoder, pipe_config); 826 } 827 828 /* Put device in ready state (LP-11) */ 829 intel_dsi_device_ready(encoder); 830 831 /* Prepare port in normal boot scenario */ 832 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 833 intel_dsi_prepare(encoder, pipe_config); 834 835 /* Send initialization commands in LP mode */ 836 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 837 838 /* Enable port in pre-enable phase itself because as per hw team 839 * recommendation, port should be enabled befor plane & pipe */ 840 if (is_cmd_mode(intel_dsi)) { 841 for_each_dsi_port(port, intel_dsi->ports) 842 intel_de_write(dev_priv, 843 MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 844 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 845 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 846 } else { 847 msleep(20); /* XXX */ 848 for_each_dsi_port(port, intel_dsi->ports) 849 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 850 intel_dsi_msleep(intel_dsi, 100); 851 852 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 853 854 intel_dsi_port_enable(encoder, pipe_config); 855 } 856 857 intel_panel_enable_backlight(pipe_config, conn_state); 858 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 859 } 860 861 static void bxt_dsi_enable(struct intel_encoder *encoder, 862 const struct intel_crtc_state *crtc_state, 863 const struct drm_connector_state *conn_state) 864 { 865 WARN_ON(crtc_state->has_pch_encoder); 866 867 intel_crtc_vblank_on(crtc_state); 868 } 869 870 /* 871 * DSI port disable has to be done after pipe and plane disable, so we do it in 872 * the post_disable hook. 873 */ 874 static void intel_dsi_disable(struct intel_encoder *encoder, 875 const struct intel_crtc_state *old_crtc_state, 876 const struct drm_connector_state *old_conn_state) 877 { 878 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 879 enum port port; 880 881 DRM_DEBUG_KMS("\n"); 882 883 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 884 intel_panel_disable_backlight(old_conn_state); 885 886 /* 887 * According to the spec we should send SHUTDOWN before 888 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 889 * has shown that the v3 sequence works for v2 VBTs too 890 */ 891 if (is_vid_mode(intel_dsi)) { 892 /* Send Shutdown command to the panel in LP mode */ 893 for_each_dsi_port(port, intel_dsi->ports) 894 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 895 msleep(10); 896 } 897 } 898 899 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 900 { 901 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 902 903 if (IS_GEMINILAKE(dev_priv)) 904 glk_dsi_clear_device_ready(encoder); 905 else 906 vlv_dsi_clear_device_ready(encoder); 907 } 908 909 static void intel_dsi_post_disable(struct intel_encoder *encoder, 910 const struct intel_crtc_state *old_crtc_state, 911 const struct drm_connector_state *old_conn_state) 912 { 913 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 914 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 915 enum port port; 916 u32 val; 917 918 drm_dbg_kms(&dev_priv->drm, "\n"); 919 920 if (IS_GEN9_LP(dev_priv)) { 921 intel_crtc_vblank_off(old_crtc_state); 922 923 skl_scaler_disable(old_crtc_state); 924 } 925 926 if (is_vid_mode(intel_dsi)) { 927 for_each_dsi_port(port, intel_dsi->ports) 928 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 929 930 intel_dsi_port_disable(encoder); 931 usleep_range(2000, 5000); 932 } 933 934 intel_dsi_unprepare(encoder); 935 936 /* 937 * if disable packets are sent before sending shutdown packet then in 938 * some next enable sequence send turn on packet error is observed 939 */ 940 if (is_cmd_mode(intel_dsi)) 941 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 942 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 943 944 /* Transition to LP-00 */ 945 intel_dsi_clear_device_ready(encoder); 946 947 if (IS_BROXTON(dev_priv)) { 948 /* Power down DSI regulator to save power */ 949 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 950 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 951 HS_IO_CTRL_SELECT); 952 953 /* Add MIPI IO reset programming for modeset */ 954 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 955 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, 956 val & ~MIPIO_RST_CTRL); 957 } 958 959 if (IS_GEN9_LP(dev_priv)) { 960 bxt_dsi_pll_disable(encoder); 961 } else { 962 u32 val; 963 964 vlv_dsi_pll_disable(encoder); 965 966 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 967 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 968 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 969 } 970 971 /* Assert reset */ 972 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 973 974 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); 975 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 976 977 /* 978 * FIXME As we do with eDP, just make a note of the time here 979 * and perform the wait before the next panel power on. 980 */ 981 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); 982 } 983 984 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 985 enum pipe *pipe) 986 { 987 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 988 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 989 intel_wakeref_t wakeref; 990 enum port port; 991 bool active = false; 992 993 drm_dbg_kms(&dev_priv->drm, "\n"); 994 995 wakeref = intel_display_power_get_if_enabled(dev_priv, 996 encoder->power_domain); 997 if (!wakeref) 998 return false; 999 1000 /* 1001 * On Broxton the PLL needs to be enabled with a valid divider 1002 * configuration, otherwise accessing DSI registers will hang the 1003 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 1004 */ 1005 if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) 1006 goto out_put_power; 1007 1008 /* XXX: this only works for one DSI output */ 1009 for_each_dsi_port(port, intel_dsi->ports) { 1010 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? 1011 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); 1012 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; 1013 1014 /* 1015 * Due to some hardware limitations on VLV/CHV, the DPI enable 1016 * bit in port C control register does not get set. As a 1017 * workaround, check pipe B conf instead. 1018 */ 1019 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1020 port == PORT_C) 1021 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; 1022 1023 /* Try command mode if video mode not enabled */ 1024 if (!enabled) { 1025 u32 tmp = intel_de_read(dev_priv, 1026 MIPI_DSI_FUNC_PRG(port)); 1027 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 1028 } 1029 1030 if (!enabled) 1031 continue; 1032 1033 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) 1034 continue; 1035 1036 if (IS_GEN9_LP(dev_priv)) { 1037 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1038 tmp &= BXT_PIPE_SELECT_MASK; 1039 tmp >>= BXT_PIPE_SELECT_SHIFT; 1040 1041 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) 1042 continue; 1043 1044 *pipe = tmp; 1045 } else { 1046 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1047 } 1048 1049 active = true; 1050 break; 1051 } 1052 1053 out_put_power: 1054 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1055 1056 return active; 1057 } 1058 1059 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1060 struct intel_crtc_state *pipe_config) 1061 { 1062 struct drm_device *dev = encoder->base.dev; 1063 struct drm_i915_private *dev_priv = to_i915(dev); 1064 struct drm_display_mode *adjusted_mode = 1065 &pipe_config->hw.adjusted_mode; 1066 struct drm_display_mode *adjusted_mode_sw; 1067 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1068 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1069 unsigned int lane_count = intel_dsi->lane_count; 1070 unsigned int bpp, fmt; 1071 enum port port; 1072 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1073 u16 hfp_sw, hsync_sw, hbp_sw; 1074 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1075 crtc_hblank_start_sw, crtc_hblank_end_sw; 1076 1077 /* FIXME: hw readout should not depend on SW state */ 1078 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1079 1080 /* 1081 * Atleast one port is active as encoder->get_config called only if 1082 * encoder->get_hw_state() returns true. 1083 */ 1084 for_each_dsi_port(port, intel_dsi->ports) { 1085 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1086 break; 1087 } 1088 1089 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; 1090 bpp = mipi_dsi_pixel_format_to_bpp( 1091 pixel_format_from_register_bits(fmt)); 1092 1093 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1094 1095 /* Enable Frame time stamo based scanline reporting */ 1096 adjusted_mode->private_flags |= 1097 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1098 1099 /* In terms of pixels */ 1100 adjusted_mode->crtc_hdisplay = 1101 intel_de_read(dev_priv, 1102 BXT_MIPI_TRANS_HACTIVE(port)); 1103 adjusted_mode->crtc_vdisplay = 1104 intel_de_read(dev_priv, 1105 BXT_MIPI_TRANS_VACTIVE(port)); 1106 adjusted_mode->crtc_vtotal = 1107 intel_de_read(dev_priv, 1108 BXT_MIPI_TRANS_VTOTAL(port)); 1109 1110 hactive = adjusted_mode->crtc_hdisplay; 1111 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); 1112 1113 /* 1114 * Meaningful for video mode non-burst sync pulse mode only, 1115 * can be zero for non-burst sync events and burst modes 1116 */ 1117 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); 1118 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); 1119 1120 /* harizontal values are in terms of high speed byte clock */ 1121 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1122 intel_dsi->burst_mode_ratio); 1123 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1124 intel_dsi->burst_mode_ratio); 1125 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1126 intel_dsi->burst_mode_ratio); 1127 1128 if (intel_dsi->dual_link) { 1129 hfp *= 2; 1130 hsync *= 2; 1131 hbp *= 2; 1132 } 1133 1134 /* vertical values are in terms of lines */ 1135 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); 1136 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); 1137 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); 1138 1139 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1140 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1141 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1142 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1143 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1144 1145 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1146 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1147 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1148 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1149 1150 /* 1151 * In BXT DSI there is no regs programmed with few horizontal timings 1152 * in Pixels but txbyteclkhs.. So retrieval process adds some 1153 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1154 * Actually here for the given adjusted_mode, we are calculating the 1155 * value programmed to the port and then back to the horizontal timing 1156 * param in pixels. This is the expected value, including roundup errors 1157 * And if that is same as retrieved value from port, then 1158 * (HW state) adjusted_mode's horizontal timings are corrected to 1159 * match with SW state to nullify the errors. 1160 */ 1161 /* Calculating the value programmed to the Port register */ 1162 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1163 adjusted_mode_sw->crtc_hdisplay; 1164 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1165 adjusted_mode_sw->crtc_hsync_start; 1166 hbp_sw = adjusted_mode_sw->crtc_htotal - 1167 adjusted_mode_sw->crtc_hsync_end; 1168 1169 if (intel_dsi->dual_link) { 1170 hfp_sw /= 2; 1171 hsync_sw /= 2; 1172 hbp_sw /= 2; 1173 } 1174 1175 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1176 intel_dsi->burst_mode_ratio); 1177 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1178 intel_dsi->burst_mode_ratio); 1179 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1180 intel_dsi->burst_mode_ratio); 1181 1182 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1183 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1184 intel_dsi->burst_mode_ratio); 1185 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1186 intel_dsi->burst_mode_ratio); 1187 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1188 intel_dsi->burst_mode_ratio); 1189 1190 if (intel_dsi->dual_link) { 1191 hfp_sw *= 2; 1192 hsync_sw *= 2; 1193 hbp_sw *= 2; 1194 } 1195 1196 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1197 hsync_sw + hbp_sw; 1198 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1199 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1200 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1201 crtc_hblank_end_sw = crtc_htotal_sw; 1202 1203 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1204 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1205 1206 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1207 adjusted_mode->crtc_hsync_start = 1208 adjusted_mode_sw->crtc_hsync_start; 1209 1210 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1211 adjusted_mode->crtc_hsync_end = 1212 adjusted_mode_sw->crtc_hsync_end; 1213 1214 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1215 adjusted_mode->crtc_hblank_start = 1216 adjusted_mode_sw->crtc_hblank_start; 1217 1218 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1219 adjusted_mode->crtc_hblank_end = 1220 adjusted_mode_sw->crtc_hblank_end; 1221 } 1222 1223 static void intel_dsi_get_config(struct intel_encoder *encoder, 1224 struct intel_crtc_state *pipe_config) 1225 { 1226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1227 u32 pclk; 1228 drm_dbg_kms(&dev_priv->drm, "\n"); 1229 1230 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1231 1232 if (IS_GEN9_LP(dev_priv)) { 1233 bxt_dsi_get_pipe_config(encoder, pipe_config); 1234 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1235 } else { 1236 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1237 } 1238 1239 if (pclk) { 1240 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1241 pipe_config->port_clock = pclk; 1242 } 1243 } 1244 1245 /* return txclkesc cycles in terms of divider and duration in us */ 1246 static u16 txclkesc(u32 divider, unsigned int us) 1247 { 1248 switch (divider) { 1249 case ESCAPE_CLOCK_DIVIDER_1: 1250 default: 1251 return 20 * us; 1252 case ESCAPE_CLOCK_DIVIDER_2: 1253 return 10 * us; 1254 case ESCAPE_CLOCK_DIVIDER_4: 1255 return 5 * us; 1256 } 1257 } 1258 1259 static void set_dsi_timings(struct drm_encoder *encoder, 1260 const struct drm_display_mode *adjusted_mode) 1261 { 1262 struct drm_device *dev = encoder->dev; 1263 struct drm_i915_private *dev_priv = to_i915(dev); 1264 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1265 enum port port; 1266 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1267 unsigned int lane_count = intel_dsi->lane_count; 1268 1269 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1270 1271 hactive = adjusted_mode->crtc_hdisplay; 1272 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1273 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1274 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1275 1276 if (intel_dsi->dual_link) { 1277 hactive /= 2; 1278 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1279 hactive += intel_dsi->pixel_overlap; 1280 hfp /= 2; 1281 hsync /= 2; 1282 hbp /= 2; 1283 } 1284 1285 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1286 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1287 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1288 1289 /* horizontal values are in terms of high speed byte clock */ 1290 hactive = txbyteclkhs(hactive, bpp, lane_count, 1291 intel_dsi->burst_mode_ratio); 1292 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1293 hsync = txbyteclkhs(hsync, bpp, lane_count, 1294 intel_dsi->burst_mode_ratio); 1295 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1296 1297 for_each_dsi_port(port, intel_dsi->ports) { 1298 if (IS_GEN9_LP(dev_priv)) { 1299 /* 1300 * Program hdisplay and vdisplay on MIPI transcoder. 1301 * This is different from calculated hactive and 1302 * vactive, as they are calculated per channel basis, 1303 * whereas these values should be based on resolution. 1304 */ 1305 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), 1306 adjusted_mode->crtc_hdisplay); 1307 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), 1308 adjusted_mode->crtc_vdisplay); 1309 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), 1310 adjusted_mode->crtc_vtotal); 1311 } 1312 1313 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), 1314 hactive); 1315 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); 1316 1317 /* meaningful for video mode non-burst sync pulse mode only, 1318 * can be zero for non-burst sync events and burst modes */ 1319 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), 1320 hsync); 1321 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); 1322 1323 /* vertical values are in terms of lines */ 1324 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); 1325 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), 1326 vsync); 1327 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); 1328 } 1329 } 1330 1331 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1332 { 1333 switch (fmt) { 1334 case MIPI_DSI_FMT_RGB888: 1335 return VID_MODE_FORMAT_RGB888; 1336 case MIPI_DSI_FMT_RGB666: 1337 return VID_MODE_FORMAT_RGB666; 1338 case MIPI_DSI_FMT_RGB666_PACKED: 1339 return VID_MODE_FORMAT_RGB666_PACKED; 1340 case MIPI_DSI_FMT_RGB565: 1341 return VID_MODE_FORMAT_RGB565; 1342 default: 1343 MISSING_CASE(fmt); 1344 return VID_MODE_FORMAT_RGB666; 1345 } 1346 } 1347 1348 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 1349 const struct intel_crtc_state *pipe_config) 1350 { 1351 struct drm_encoder *encoder = &intel_encoder->base; 1352 struct drm_device *dev = encoder->dev; 1353 struct drm_i915_private *dev_priv = to_i915(dev); 1354 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 1355 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1356 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1357 enum port port; 1358 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1359 u32 val, tmp; 1360 u16 mode_hdisplay; 1361 1362 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe)); 1363 1364 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1365 1366 if (intel_dsi->dual_link) { 1367 mode_hdisplay /= 2; 1368 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1369 mode_hdisplay += intel_dsi->pixel_overlap; 1370 } 1371 1372 for_each_dsi_port(port, intel_dsi->ports) { 1373 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1374 /* 1375 * escape clock divider, 20MHz, shared for A and C. 1376 * device ready must be off when doing this! txclkesc? 1377 */ 1378 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); 1379 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1380 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), 1381 tmp | ESCAPE_CLOCK_DIVIDER_1); 1382 1383 /* read request priority is per pipe */ 1384 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1385 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1386 intel_de_write(dev_priv, MIPI_CTRL(port), 1387 tmp | READ_REQUEST_PRIORITY_HIGH); 1388 } else if (IS_GEN9_LP(dev_priv)) { 1389 enum pipe pipe = intel_crtc->pipe; 1390 1391 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); 1392 tmp &= ~BXT_PIPE_SELECT_MASK; 1393 1394 tmp |= BXT_PIPE_SELECT(pipe); 1395 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); 1396 } 1397 1398 /* XXX: why here, why like this? handling in irq handler?! */ 1399 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); 1400 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); 1401 1402 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), 1403 intel_dsi->dphy_reg); 1404 1405 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), 1406 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1407 } 1408 1409 set_dsi_timings(encoder, adjusted_mode); 1410 1411 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1412 if (is_cmd_mode(intel_dsi)) { 1413 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1414 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1415 } else { 1416 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1417 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1418 } 1419 1420 tmp = 0; 1421 if (intel_dsi->eotp_pkt == 0) 1422 tmp |= EOT_DISABLE; 1423 if (intel_dsi->clock_stop) 1424 tmp |= CLOCKSTOP; 1425 1426 if (IS_GEN9_LP(dev_priv)) { 1427 tmp |= BXT_DPHY_DEFEATURE_EN; 1428 if (!is_cmd_mode(intel_dsi)) 1429 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1430 } 1431 1432 for_each_dsi_port(port, intel_dsi->ports) { 1433 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1434 1435 /* timeouts for recovery. one frame IIUC. if counter expires, 1436 * EOT and stop state. */ 1437 1438 /* 1439 * In burst mode, value greater than one DPI line Time in byte 1440 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1441 * said value is recommended. 1442 * 1443 * In non-burst mode, Value greater than one DPI frame time in 1444 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1445 * said value is recommended. 1446 * 1447 * In DBI only mode, value greater than one DBI frame time in 1448 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1449 * said value is recommended. 1450 */ 1451 1452 if (is_vid_mode(intel_dsi) && 1453 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 1454 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1455 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1456 } else { 1457 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), 1458 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1459 } 1460 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), 1461 intel_dsi->lp_rx_timeout); 1462 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), 1463 intel_dsi->turn_arnd_val); 1464 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), 1465 intel_dsi->rst_timer_val); 1466 1467 /* dphy stuff */ 1468 1469 /* in terms of low power clock */ 1470 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1471 txclkesc(intel_dsi->escape_clk_div, 100)); 1472 1473 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { 1474 /* 1475 * BXT spec says write MIPI_INIT_COUNT for 1476 * both the ports, even if only one is 1477 * getting used. So write the other port 1478 * if not in dual link mode. 1479 */ 1480 intel_de_write(dev_priv, 1481 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), 1482 intel_dsi->init_count); 1483 } 1484 1485 /* recovery disables */ 1486 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); 1487 1488 /* in terms of low power clock */ 1489 intel_de_write(dev_priv, MIPI_INIT_COUNT(port), 1490 intel_dsi->init_count); 1491 1492 /* in terms of txbyteclkhs. actual high to low switch + 1493 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1494 * 1495 * XXX: write MIPI_STOP_STATE_STALL? 1496 */ 1497 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), 1498 intel_dsi->hs_to_lp_count); 1499 1500 /* XXX: low power clock equivalence in terms of byte clock. 1501 * the number of byte clocks occupied in one low power clock. 1502 * based on txbyteclkhs and txclkesc. 1503 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1504 * ) / 105.??? 1505 */ 1506 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), 1507 intel_dsi->lp_byte_clk); 1508 1509 if (IS_GEMINILAKE(dev_priv)) { 1510 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), 1511 intel_dsi->lp_byte_clk); 1512 /* Shadow of DPHY reg */ 1513 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), 1514 intel_dsi->dphy_reg); 1515 } 1516 1517 /* the bw essential for transmitting 16 long packets containing 1518 * 252 bytes meant for dcs write memory command is programmed in 1519 * this register in terms of byte clocks. based on dsi transfer 1520 * rate and the number of lanes configured the time taken to 1521 * transmit 16 long packets in a dsi stream varies. */ 1522 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), 1523 intel_dsi->bw_timer); 1524 1525 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), 1526 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1527 1528 if (is_vid_mode(intel_dsi)) 1529 /* Some panels might have resolution which is not a 1530 * multiple of 64 like 1366 x 768. Enable RANDOM 1531 * resolution support for such panels by default */ 1532 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), 1533 intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION); 1534 } 1535 } 1536 1537 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1538 { 1539 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1540 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1541 enum port port; 1542 u32 val; 1543 1544 if (IS_GEMINILAKE(dev_priv)) 1545 return; 1546 1547 for_each_dsi_port(port, intel_dsi->ports) { 1548 /* Panel commands can be sent when clock is in LP11 */ 1549 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); 1550 1551 if (IS_GEN9_LP(dev_priv)) 1552 bxt_dsi_reset_clocks(encoder, port); 1553 else 1554 vlv_dsi_reset_clocks(encoder, port); 1555 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); 1556 1557 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); 1558 val &= ~VID_MODE_FORMAT_MASK; 1559 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); 1560 1561 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); 1562 } 1563 } 1564 1565 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) 1566 { 1567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)); 1568 1569 intel_dsi_vbt_gpio_cleanup(intel_dsi); 1570 intel_encoder_destroy(encoder); 1571 } 1572 1573 static const struct drm_encoder_funcs intel_dsi_funcs = { 1574 .destroy = intel_dsi_encoder_destroy, 1575 }; 1576 1577 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1578 .get_modes = intel_dsi_get_modes, 1579 .mode_valid = intel_dsi_mode_valid, 1580 .atomic_check = intel_digital_connector_atomic_check, 1581 }; 1582 1583 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1584 .late_register = intel_connector_register, 1585 .early_unregister = intel_connector_unregister, 1586 .destroy = intel_connector_destroy, 1587 .fill_modes = drm_helper_probe_single_connector_modes, 1588 .atomic_get_property = intel_digital_connector_atomic_get_property, 1589 .atomic_set_property = intel_digital_connector_atomic_set_property, 1590 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1591 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1592 }; 1593 1594 static void vlv_dsi_add_properties(struct intel_connector *connector) 1595 { 1596 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1597 1598 if (connector->panel.fixed_mode) { 1599 u32 allowed_scalers; 1600 1601 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 1602 if (!HAS_GMCH(dev_priv)) 1603 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 1604 1605 drm_connector_attach_scaling_mode_property(&connector->base, 1606 allowed_scalers); 1607 1608 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1609 1610 drm_connector_set_panel_orientation_with_quirk( 1611 &connector->base, 1612 intel_dsi_get_panel_orientation(connector), 1613 connector->panel.fixed_mode->hdisplay, 1614 connector->panel.fixed_mode->vdisplay); 1615 } 1616 } 1617 1618 #define NS_KHZ_RATIO 1000000 1619 1620 #define PREPARE_CNT_MAX 0x3F 1621 #define EXIT_ZERO_CNT_MAX 0x3F 1622 #define CLK_ZERO_CNT_MAX 0xFF 1623 #define TRAIL_CNT_MAX 0x1F 1624 1625 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1626 { 1627 struct drm_device *dev = intel_dsi->base.base.dev; 1628 struct drm_i915_private *dev_priv = to_i915(dev); 1629 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1630 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1631 u32 ui_num, ui_den; 1632 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1633 u32 ths_prepare_ns, tclk_trail_ns; 1634 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1635 u32 lp_to_hs_switch, hs_to_lp_switch; 1636 u32 mul; 1637 1638 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1639 1640 switch (intel_dsi->lane_count) { 1641 case 1: 1642 case 2: 1643 extra_byte_count = 2; 1644 break; 1645 case 3: 1646 extra_byte_count = 4; 1647 break; 1648 case 4: 1649 default: 1650 extra_byte_count = 3; 1651 break; 1652 } 1653 1654 /* in Kbps */ 1655 ui_num = NS_KHZ_RATIO; 1656 ui_den = intel_dsi_bitrate(intel_dsi); 1657 1658 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1659 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1660 1661 /* 1662 * B060 1663 * LP byte clock = TLPX/ (8UI) 1664 */ 1665 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1666 1667 /* DDR clock period = 2 * UI 1668 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1669 * UI(nsec) = 10^6 / bitrate 1670 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1671 * DDR clock count = ns_value / DDR clock period 1672 * 1673 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1674 * HS byte clock count for other platform in HS ddr clock count 1675 */ 1676 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1677 ths_prepare_ns = max(mipi_config->ths_prepare, 1678 mipi_config->tclk_prepare); 1679 1680 /* prepare count */ 1681 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1682 1683 if (prepare_cnt > PREPARE_CNT_MAX) { 1684 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1685 prepare_cnt); 1686 prepare_cnt = PREPARE_CNT_MAX; 1687 } 1688 1689 /* exit zero count */ 1690 exit_zero_cnt = DIV_ROUND_UP( 1691 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1692 ui_num * mul 1693 ); 1694 1695 /* 1696 * Exit zero is unified val ths_zero and ths_exit 1697 * minimum value for ths_exit = 110ns 1698 * min (exit_zero_cnt * 2) = 110/UI 1699 * exit_zero_cnt = 55/UI 1700 */ 1701 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1702 exit_zero_cnt += 1; 1703 1704 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1705 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1706 exit_zero_cnt); 1707 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1708 } 1709 1710 /* clk zero count */ 1711 clk_zero_cnt = DIV_ROUND_UP( 1712 (tclk_prepare_clkzero - ths_prepare_ns) 1713 * ui_den, ui_num * mul); 1714 1715 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1716 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1717 clk_zero_cnt); 1718 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1719 } 1720 1721 /* trail count */ 1722 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1723 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1724 1725 if (trail_cnt > TRAIL_CNT_MAX) { 1726 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1727 trail_cnt); 1728 trail_cnt = TRAIL_CNT_MAX; 1729 } 1730 1731 /* B080 */ 1732 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1733 clk_zero_cnt << 8 | prepare_cnt; 1734 1735 /* 1736 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1737 * mul + 10UI + Extra Byte Count 1738 * 1739 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1740 * Extra Byte Count is calculated according to number of lanes. 1741 * High Low Switch Count is the Max of LP to HS and 1742 * HS to LP switch count 1743 * 1744 */ 1745 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1746 1747 /* B044 */ 1748 /* FIXME: 1749 * The comment above does not match with the code */ 1750 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1751 exit_zero_cnt * mul + 10, 8); 1752 1753 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1754 1755 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1756 intel_dsi->hs_to_lp_count += extra_byte_count; 1757 1758 /* B088 */ 1759 /* LP -> HS for clock lanes 1760 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1761 * extra byte count 1762 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1763 * 2(in UI) + extra byte count 1764 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1765 * 8 + extra byte count 1766 */ 1767 intel_dsi->clk_lp_to_hs_count = 1768 DIV_ROUND_UP( 1769 4 * tlpx_ui + prepare_cnt * 2 + 1770 clk_zero_cnt * 2, 1771 8); 1772 1773 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1774 1775 /* HS->LP for Clock Lanes 1776 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1777 * Extra byte count 1778 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1779 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1780 * Extra byte count 1781 */ 1782 intel_dsi->clk_hs_to_lp_count = 1783 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1784 8); 1785 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1786 1787 intel_dsi_log_params(intel_dsi); 1788 } 1789 1790 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1791 { 1792 struct drm_device *dev = &dev_priv->drm; 1793 struct intel_dsi *intel_dsi; 1794 struct intel_encoder *intel_encoder; 1795 struct drm_encoder *encoder; 1796 struct intel_connector *intel_connector; 1797 struct drm_connector *connector; 1798 struct drm_display_mode *current_mode, *fixed_mode; 1799 enum port port; 1800 enum pipe pipe; 1801 1802 drm_dbg_kms(&dev_priv->drm, "\n"); 1803 1804 /* There is no detection method for MIPI so rely on VBT */ 1805 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1806 return; 1807 1808 if (IS_GEN9_LP(dev_priv)) 1809 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; 1810 else 1811 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 1812 1813 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1814 if (!intel_dsi) 1815 return; 1816 1817 intel_connector = intel_connector_alloc(); 1818 if (!intel_connector) { 1819 kfree(intel_dsi); 1820 return; 1821 } 1822 1823 intel_encoder = &intel_dsi->base; 1824 encoder = &intel_encoder->base; 1825 intel_dsi->attached_connector = intel_connector; 1826 1827 connector = &intel_connector->base; 1828 1829 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, 1830 "DSI %c", port_name(port)); 1831 1832 intel_encoder->compute_config = intel_dsi_compute_config; 1833 intel_encoder->pre_enable = intel_dsi_pre_enable; 1834 if (IS_GEN9_LP(dev_priv)) 1835 intel_encoder->enable = bxt_dsi_enable; 1836 intel_encoder->disable = intel_dsi_disable; 1837 intel_encoder->post_disable = intel_dsi_post_disable; 1838 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 1839 intel_encoder->get_config = intel_dsi_get_config; 1840 intel_encoder->update_pipe = intel_panel_update_backlight; 1841 1842 intel_connector->get_hw_state = intel_connector_get_hw_state; 1843 1844 intel_encoder->port = port; 1845 intel_encoder->type = INTEL_OUTPUT_DSI; 1846 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1847 intel_encoder->cloneable = 0; 1848 1849 /* 1850 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1851 * port C. BXT isn't limited like this. 1852 */ 1853 if (IS_GEN9_LP(dev_priv)) 1854 intel_encoder->pipe_mask = ~0; 1855 else if (port == PORT_A) 1856 intel_encoder->pipe_mask = BIT(PIPE_A); 1857 else 1858 intel_encoder->pipe_mask = BIT(PIPE_B); 1859 1860 if (dev_priv->vbt.dsi.config->dual_link) 1861 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1862 else 1863 intel_dsi->ports = BIT(port); 1864 1865 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1866 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1867 1868 /* Create a DSI host (and a device) for each port. */ 1869 for_each_dsi_port(port, intel_dsi->ports) { 1870 struct intel_dsi_host *host; 1871 1872 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1873 port); 1874 if (!host) 1875 goto err; 1876 1877 intel_dsi->dsi_hosts[port] = host; 1878 } 1879 1880 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1881 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1882 goto err; 1883 } 1884 1885 /* Use clock read-back from current hw-state for fastboot */ 1886 current_mode = intel_encoder_current_mode(intel_encoder); 1887 if (current_mode) { 1888 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1889 intel_dsi->pclk, current_mode->clock); 1890 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1891 current_mode->clock)) { 1892 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1893 intel_dsi->pclk = current_mode->clock; 1894 } 1895 1896 kfree(current_mode); 1897 } 1898 1899 vlv_dphy_param_init(intel_dsi); 1900 1901 intel_dsi_vbt_gpio_init(intel_dsi, 1902 intel_dsi_get_hw_state(intel_encoder, &pipe)); 1903 1904 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 1905 DRM_MODE_CONNECTOR_DSI); 1906 1907 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 1908 1909 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 1910 connector->interlace_allowed = false; 1911 connector->doublescan_allowed = false; 1912 1913 intel_connector_attach_encoder(intel_connector, intel_encoder); 1914 1915 mutex_lock(&dev->mode_config.mutex); 1916 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1917 mutex_unlock(&dev->mode_config.mutex); 1918 1919 if (!fixed_mode) { 1920 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 1921 goto err_cleanup_connector; 1922 } 1923 1924 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1925 intel_panel_setup_backlight(connector, INVALID_PIPE); 1926 1927 vlv_dsi_add_properties(intel_connector); 1928 1929 return; 1930 1931 err_cleanup_connector: 1932 drm_connector_cleanup(&intel_connector->base); 1933 err: 1934 drm_encoder_cleanup(&intel_encoder->base); 1935 kfree(intel_dsi); 1936 kfree(intel_connector); 1937 } 1938