1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <linux/dmi.h> 27 #include <linux/slab.h> 28 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_crtc.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_mipi_dsi.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include "i915_drv.h" 36 #include "i915_reg.h" 37 #include "intel_atomic.h" 38 #include "intel_backlight.h" 39 #include "intel_connector.h" 40 #include "intel_crtc.h" 41 #include "intel_de.h" 42 #include "intel_display_types.h" 43 #include "intel_dsi.h" 44 #include "intel_dsi_vbt.h" 45 #include "intel_fifo_underrun.h" 46 #include "intel_panel.h" 47 #include "intel_pfit.h" 48 #include "skl_scaler.h" 49 #include "vlv_dsi.h" 50 #include "vlv_dsi_pll.h" 51 #include "vlv_dsi_regs.h" 52 #include "vlv_sideband.h" 53 54 /* return pixels in terms of txbyteclkhs */ 55 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 56 u16 burst_mode_ratio) 57 { 58 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 59 8 * 100), lane_count); 60 } 61 62 /* return pixels equvalent to txbyteclkhs */ 63 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 64 u16 burst_mode_ratio) 65 { 66 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 67 (bpp * burst_mode_ratio)); 68 } 69 70 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 71 { 72 /* It just so happens the VBT matches register contents. */ 73 switch (fmt) { 74 case VID_MODE_FORMAT_RGB888: 75 return MIPI_DSI_FMT_RGB888; 76 case VID_MODE_FORMAT_RGB666: 77 return MIPI_DSI_FMT_RGB666; 78 case VID_MODE_FORMAT_RGB666_PACKED: 79 return MIPI_DSI_FMT_RGB666_PACKED; 80 case VID_MODE_FORMAT_RGB565: 81 return MIPI_DSI_FMT_RGB565; 82 default: 83 MISSING_CASE(fmt); 84 return MIPI_DSI_FMT_RGB666; 85 } 86 } 87 88 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 89 { 90 struct intel_display *display = to_intel_display(&intel_dsi->base); 91 u32 mask; 92 93 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 94 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 95 96 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), 97 mask, 100)) 98 drm_err(display->drm, "DPI FIFOs are not empty\n"); 99 } 100 101 static void write_data(struct intel_display *display, 102 i915_reg_t reg, 103 const u8 *data, u32 len) 104 { 105 u32 i, j; 106 107 for (i = 0; i < len; i += 4) { 108 u32 val = 0; 109 110 for (j = 0; j < min_t(u32, len - i, 4); j++) 111 val |= *data++ << 8 * j; 112 113 intel_de_write(display, reg, val); 114 } 115 } 116 117 static void read_data(struct intel_display *display, 118 i915_reg_t reg, 119 u8 *data, u32 len) 120 { 121 u32 i, j; 122 123 for (i = 0; i < len; i += 4) { 124 u32 val = intel_de_read(display, reg); 125 126 for (j = 0; j < min_t(u32, len - i, 4); j++) 127 *data++ = val >> 8 * j; 128 } 129 } 130 131 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 132 const struct mipi_dsi_msg *msg) 133 { 134 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 135 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; 136 struct intel_display *display = to_intel_display(&intel_dsi->base); 137 enum port port = intel_dsi_host->port; 138 struct mipi_dsi_packet packet; 139 ssize_t ret; 140 const u8 *header; 141 i915_reg_t data_reg, ctrl_reg; 142 u32 data_mask, ctrl_mask; 143 144 ret = mipi_dsi_create_packet(&packet, msg); 145 if (ret < 0) 146 return ret; 147 148 header = packet.header; 149 150 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 151 data_reg = MIPI_LP_GEN_DATA(display, port); 152 data_mask = LP_DATA_FIFO_FULL; 153 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); 154 ctrl_mask = LP_CTRL_FIFO_FULL; 155 } else { 156 data_reg = MIPI_HS_GEN_DATA(display, port); 157 data_mask = HS_DATA_FIFO_FULL; 158 ctrl_reg = MIPI_HS_GEN_CTRL(display, port); 159 ctrl_mask = HS_CTRL_FIFO_FULL; 160 } 161 162 /* note: this is never true for reads */ 163 if (packet.payload_length) { 164 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), 165 data_mask, 50)) 166 drm_err(display->drm, 167 "Timeout waiting for HS/LP DATA FIFO !full\n"); 168 169 write_data(display, data_reg, packet.payload, 170 packet.payload_length); 171 } 172 173 if (msg->rx_len) { 174 intel_de_write(display, MIPI_INTR_STAT(display, port), 175 GEN_READ_DATA_AVAIL); 176 } 177 178 if (intel_de_wait_for_clear(display, MIPI_GEN_FIFO_STAT(display, port), 179 ctrl_mask, 50)) { 180 drm_err(display->drm, 181 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 182 } 183 184 intel_de_write(display, ctrl_reg, 185 header[2] << 16 | header[1] << 8 | header[0]); 186 187 /* ->rx_len is set only for reads */ 188 if (msg->rx_len) { 189 data_mask = GEN_READ_DATA_AVAIL; 190 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), 191 data_mask, 50)) 192 drm_err(display->drm, 193 "Timeout waiting for read data.\n"); 194 195 read_data(display, data_reg, msg->rx_buf, msg->rx_len); 196 } 197 198 /* XXX: fix for reads and writes */ 199 return 4 + packet.payload_length; 200 } 201 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host, 203 struct mipi_dsi_device *dsi) 204 { 205 return 0; 206 } 207 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host, 209 struct mipi_dsi_device *dsi) 210 { 211 return 0; 212 } 213 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 215 .attach = intel_dsi_host_attach, 216 .detach = intel_dsi_host_detach, 217 .transfer = intel_dsi_host_transfer, 218 }; 219 220 /* 221 * send a video mode command 222 * 223 * XXX: commands with data in MIPI_DPI_DATA? 224 */ 225 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 226 enum port port) 227 { 228 struct intel_display *display = to_intel_display(&intel_dsi->base); 229 u32 mask; 230 231 /* XXX: pipe, hs */ 232 if (hs) 233 cmd &= ~DPI_LP_MODE; 234 else 235 cmd |= DPI_LP_MODE; 236 237 /* clear bit */ 238 intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); 239 240 /* XXX: old code skips write if control unchanged */ 241 if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) 242 drm_dbg_kms(display->drm, 243 "Same special packet %02x twice in a row.\n", cmd); 244 245 intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); 246 247 mask = SPL_PKT_SENT_INTERRUPT; 248 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100)) 249 drm_err(display->drm, 250 "Video mode command 0x%08x send failed.\n", cmd); 251 252 return 0; 253 } 254 255 static void band_gap_reset(struct drm_i915_private *dev_priv) 256 { 257 vlv_flisdsi_get(dev_priv); 258 259 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 260 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 261 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 262 udelay(150); 263 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 264 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 265 266 vlv_flisdsi_put(dev_priv); 267 } 268 269 static int intel_dsi_compute_config(struct intel_encoder *encoder, 270 struct intel_crtc_state *pipe_config, 271 struct drm_connector_state *conn_state) 272 { 273 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 274 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 275 struct intel_connector *intel_connector = intel_dsi->attached_connector; 276 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 277 int ret; 278 279 drm_dbg_kms(&dev_priv->drm, "\n"); 280 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 281 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 282 283 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 284 if (ret) 285 return ret; 286 287 ret = intel_panel_fitting(pipe_config, conn_state); 288 if (ret) 289 return ret; 290 291 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 292 return -EINVAL; 293 294 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 295 adjusted_mode->flags = 0; 296 297 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 298 pipe_config->pipe_bpp = 24; 299 else 300 pipe_config->pipe_bpp = 18; 301 302 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 303 /* Enable Frame time stamp based scanline reporting */ 304 pipe_config->mode_flags |= 305 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 306 307 /* Dual link goes to DSI transcoder A. */ 308 if (intel_dsi->ports == BIT(PORT_C)) 309 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 310 else 311 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 312 313 ret = bxt_dsi_pll_compute(encoder, pipe_config); 314 if (ret) 315 return -EINVAL; 316 } else { 317 ret = vlv_dsi_pll_compute(encoder, pipe_config); 318 if (ret) 319 return -EINVAL; 320 } 321 322 pipe_config->clock_set = true; 323 324 return 0; 325 } 326 327 static bool glk_dsi_enable_io(struct intel_encoder *encoder) 328 { 329 struct intel_display *display = to_intel_display(encoder); 330 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 331 enum port port; 332 bool cold_boot = false; 333 334 /* Set the MIPI mode 335 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 336 * Power ON MIPI IO first and then write into IO reset and LP wake bits 337 */ 338 for_each_dsi_port(port, intel_dsi->ports) 339 intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); 340 341 /* Put the IO into reset */ 342 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 343 344 /* Program LP Wake */ 345 for_each_dsi_port(port, intel_dsi->ports) { 346 u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); 347 348 intel_de_rmw(display, MIPI_CTRL(display, port), 349 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); 350 } 351 352 /* Wait for Pwr ACK */ 353 for_each_dsi_port(port, intel_dsi->ports) { 354 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), 355 GLK_MIPIIO_PORT_POWERED, 20)) 356 drm_err(display->drm, "MIPIO port is powergated\n"); 357 } 358 359 /* Check for cold boot scenario */ 360 for_each_dsi_port(port, intel_dsi->ports) { 361 cold_boot |= 362 !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); 363 } 364 365 return cold_boot; 366 } 367 368 static void glk_dsi_device_ready(struct intel_encoder *encoder) 369 { 370 struct intel_display *display = to_intel_display(encoder); 371 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 372 enum port port; 373 374 /* Wait for MIPI PHY status bit to set */ 375 for_each_dsi_port(port, intel_dsi->ports) { 376 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), 377 GLK_PHY_STATUS_PORT_READY, 20)) 378 drm_err(display->drm, "PHY is not ON\n"); 379 } 380 381 /* Get IO out of reset */ 382 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); 383 384 /* Get IO out of Low power state*/ 385 for_each_dsi_port(port, intel_dsi->ports) { 386 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { 387 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 388 ULPS_STATE_MASK, DEVICE_READY); 389 usleep_range(10, 15); 390 } else { 391 /* Enter ULPS */ 392 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 393 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 394 395 /* Wait for ULPS active */ 396 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), 397 GLK_ULPS_NOT_ACTIVE, 20)) 398 drm_err(display->drm, "ULPS not active\n"); 399 400 /* Exit ULPS */ 401 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 402 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); 403 404 /* Enter Normal Mode */ 405 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 406 ULPS_STATE_MASK, 407 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 408 409 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); 410 } 411 } 412 413 /* Wait for Stop state */ 414 for_each_dsi_port(port, intel_dsi->ports) { 415 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), 416 GLK_DATA_LANE_STOP_STATE, 20)) 417 drm_err(display->drm, 418 "Date lane not in STOP state\n"); 419 } 420 421 /* Wait for AFE LATCH */ 422 for_each_dsi_port(port, intel_dsi->ports) { 423 if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port), 424 AFE_LATCHOUT, 20)) 425 drm_err(display->drm, 426 "D-PHY not entering LP-11 state\n"); 427 } 428 } 429 430 static void bxt_dsi_device_ready(struct intel_encoder *encoder) 431 { 432 struct intel_display *display = to_intel_display(encoder); 433 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 434 enum port port; 435 u32 val; 436 437 drm_dbg_kms(display->drm, "\n"); 438 439 /* Enable MIPI PHY transparent latch */ 440 for_each_dsi_port(port, intel_dsi->ports) { 441 intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); 442 usleep_range(2000, 2500); 443 } 444 445 /* Clear ULPS and set device ready */ 446 for_each_dsi_port(port, intel_dsi->ports) { 447 val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); 448 val &= ~ULPS_STATE_MASK; 449 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); 450 usleep_range(2000, 2500); 451 val |= DEVICE_READY; 452 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); 453 } 454 } 455 456 static void vlv_dsi_device_ready(struct intel_encoder *encoder) 457 { 458 struct intel_display *display = to_intel_display(encoder); 459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 460 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 461 enum port port; 462 463 drm_dbg_kms(display->drm, "\n"); 464 465 vlv_flisdsi_get(dev_priv); 466 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 467 * needed everytime after power gate */ 468 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 469 vlv_flisdsi_put(dev_priv); 470 471 /* bandgap reset is needed after everytime we do power gate */ 472 band_gap_reset(dev_priv); 473 474 for_each_dsi_port(port, intel_dsi->ports) { 475 476 intel_de_write(display, MIPI_DEVICE_READY(display, port), 477 ULPS_STATE_ENTER); 478 usleep_range(2500, 3000); 479 480 /* Enable MIPI PHY transparent latch 481 * Common bit for both MIPI Port A & MIPI Port C 482 * No similar bit in MIPI Port C reg 483 */ 484 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); 485 usleep_range(1000, 1500); 486 487 intel_de_write(display, MIPI_DEVICE_READY(display, port), 488 ULPS_STATE_EXIT); 489 usleep_range(2500, 3000); 490 491 intel_de_write(display, MIPI_DEVICE_READY(display, port), 492 DEVICE_READY); 493 usleep_range(2500, 3000); 494 } 495 } 496 497 static void intel_dsi_device_ready(struct intel_encoder *encoder) 498 { 499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 500 501 if (IS_GEMINILAKE(dev_priv)) 502 glk_dsi_device_ready(encoder); 503 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 504 bxt_dsi_device_ready(encoder); 505 else 506 vlv_dsi_device_ready(encoder); 507 } 508 509 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 510 { 511 struct intel_display *display = to_intel_display(encoder); 512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 513 enum port port; 514 515 /* Enter ULPS */ 516 for_each_dsi_port(port, intel_dsi->ports) 517 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 518 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 519 520 /* Wait for MIPI PHY status bit to unset */ 521 for_each_dsi_port(port, intel_dsi->ports) { 522 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), 523 GLK_PHY_STATUS_PORT_READY, 20)) 524 drm_err(display->drm, "PHY is not turning OFF\n"); 525 } 526 527 /* Wait for Pwr ACK bit to unset */ 528 for_each_dsi_port(port, intel_dsi->ports) { 529 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), 530 GLK_MIPIIO_PORT_POWERED, 20)) 531 drm_err(display->drm, 532 "MIPI IO Port is not powergated\n"); 533 } 534 } 535 536 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 537 { 538 struct intel_display *display = to_intel_display(encoder); 539 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 540 enum port port; 541 542 /* Put the IO into reset */ 543 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 544 545 /* Wait for MIPI PHY status bit to unset */ 546 for_each_dsi_port(port, intel_dsi->ports) { 547 if (intel_de_wait_for_clear(display, MIPI_CTRL(display, port), 548 GLK_PHY_STATUS_PORT_READY, 20)) 549 drm_err(display->drm, "PHY is not turning OFF\n"); 550 } 551 552 /* Clear MIPI mode */ 553 for_each_dsi_port(port, intel_dsi->ports) 554 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0); 555 } 556 557 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 558 { 559 glk_dsi_enter_low_power_mode(encoder); 560 glk_dsi_disable_mipi_io(encoder); 561 } 562 563 static i915_reg_t port_ctrl_reg(struct drm_i915_private *i915, enum port port) 564 { 565 return IS_GEMINILAKE(i915) || IS_BROXTON(i915) ? 566 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port); 567 } 568 569 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 570 { 571 struct intel_display *display = to_intel_display(encoder); 572 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 573 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 574 enum port port; 575 576 drm_dbg_kms(display->drm, "\n"); 577 for_each_dsi_port(port, intel_dsi->ports) { 578 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 579 i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? 580 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); 581 582 intel_de_write(display, MIPI_DEVICE_READY(display, port), 583 DEVICE_READY | ULPS_STATE_ENTER); 584 usleep_range(2000, 2500); 585 586 intel_de_write(display, MIPI_DEVICE_READY(display, port), 587 DEVICE_READY | ULPS_STATE_EXIT); 588 usleep_range(2000, 2500); 589 590 intel_de_write(display, MIPI_DEVICE_READY(display, port), 591 DEVICE_READY | ULPS_STATE_ENTER); 592 usleep_range(2000, 2500); 593 594 /* 595 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 596 * Port A only. MIPI Port C has no similar bit for checking. 597 */ 598 if ((IS_BROXTON(dev_priv) || port == PORT_A) && 599 intel_de_wait_for_clear(display, port_ctrl, 600 AFE_LATCHOUT, 30)) 601 drm_err(display->drm, "DSI LP not going Low\n"); 602 603 /* Disable MIPI PHY transparent latch */ 604 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); 605 usleep_range(1000, 1500); 606 607 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00); 608 usleep_range(2000, 2500); 609 } 610 } 611 612 static void intel_dsi_port_enable(struct intel_encoder *encoder, 613 const struct intel_crtc_state *crtc_state) 614 { 615 struct intel_display *display = to_intel_display(encoder); 616 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 617 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 618 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 619 enum port port; 620 621 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 622 u32 temp = intel_dsi->pixel_overlap; 623 624 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 625 for_each_dsi_port(port, intel_dsi->ports) 626 intel_de_rmw(display, MIPI_CTRL(display, port), 627 BXT_PIXEL_OVERLAP_CNT_MASK, 628 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); 629 } else { 630 intel_de_rmw(display, VLV_CHICKEN_3, 631 PIXEL_OVERLAP_CNT_MASK, 632 temp << PIXEL_OVERLAP_CNT_SHIFT); 633 } 634 } 635 636 for_each_dsi_port(port, intel_dsi->ports) { 637 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); 638 u32 temp; 639 640 temp = intel_de_read(display, port_ctrl); 641 642 temp &= ~LANE_CONFIGURATION_MASK; 643 temp &= ~DUAL_LINK_MODE_MASK; 644 645 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 646 temp |= (intel_dsi->dual_link - 1) 647 << DUAL_LINK_MODE_SHIFT; 648 if (IS_BROXTON(dev_priv)) 649 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 650 else 651 temp |= crtc->pipe ? 652 LANE_CONFIGURATION_DUAL_LINK_B : 653 LANE_CONFIGURATION_DUAL_LINK_A; 654 } 655 656 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 657 temp |= DITHERING_ENABLE; 658 659 /* assert ip_tg_enable signal */ 660 intel_de_write(display, port_ctrl, temp | DPI_ENABLE); 661 intel_de_posting_read(display, port_ctrl); 662 } 663 } 664 665 static void intel_dsi_port_disable(struct intel_encoder *encoder) 666 { 667 struct intel_display *display = to_intel_display(encoder); 668 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 669 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 670 enum port port; 671 672 for_each_dsi_port(port, intel_dsi->ports) { 673 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); 674 675 /* de-assert ip_tg_enable signal */ 676 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); 677 intel_de_posting_read(display, port_ctrl); 678 } 679 } 680 681 static void intel_dsi_prepare(struct intel_encoder *encoder, 682 const struct intel_crtc_state *pipe_config); 683 static void intel_dsi_unprepare(struct intel_encoder *encoder); 684 685 /* 686 * Panel enable/disable sequences from the VBT spec. 687 * 688 * Note the spec has AssertReset / DeassertReset swapped from their 689 * usual naming. We use the normal names to avoid confusion (so below 690 * they are swapped compared to the spec). 691 * 692 * Steps starting with MIPI refer to VBT sequences, note that for v2 693 * VBTs several steps which have a VBT in v2 are expected to be handled 694 * directly by the driver, by directly driving gpios for example. 695 * 696 * v2 video mode seq v3 video mode seq command mode seq 697 * - power on - MIPIPanelPowerOn - power on 698 * - wait t1+t2 - wait t1+t2 699 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 700 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 701 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 702 * - MIPITearOn 703 * - MIPIDisplayOn 704 * - turn on DPI - turn on DPI - set pipe to dsr mode 705 * - MIPIDisplayOn - MIPIDisplayOn 706 * - wait t5 - wait t5 707 * - backlight on - MIPIBacklightOn - backlight on 708 * ... ... ... issue mem cmds ... 709 * - backlight off - MIPIBacklightOff - backlight off 710 * - wait t6 - wait t6 711 * - MIPIDisplayOff 712 * - turn off DPI - turn off DPI - disable pipe dsr mode 713 * - MIPITearOff 714 * - MIPIDisplayOff - MIPIDisplayOff 715 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 716 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 717 * - wait t3 - wait t3 718 * - power off - MIPIPanelPowerOff - power off 719 * - wait t4 - wait t4 720 */ 721 722 /* 723 * DSI port enable has to be done before pipe and plane enable, so we do it in 724 * the pre_enable hook instead of the enable hook. 725 */ 726 static void intel_dsi_pre_enable(struct intel_atomic_state *state, 727 struct intel_encoder *encoder, 728 const struct intel_crtc_state *pipe_config, 729 const struct drm_connector_state *conn_state) 730 { 731 struct intel_display *display = to_intel_display(encoder); 732 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 733 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 734 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 735 enum pipe pipe = crtc->pipe; 736 enum port port; 737 bool glk_cold_boot = false; 738 739 drm_dbg_kms(display->drm, "\n"); 740 741 intel_dsi_wait_panel_power_cycle(intel_dsi); 742 743 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 744 745 /* 746 * The BIOS may leave the PLL in a wonky state where it doesn't 747 * lock. It needs to be fully powered down to fix it. 748 */ 749 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 750 bxt_dsi_pll_disable(encoder); 751 bxt_dsi_pll_enable(encoder, pipe_config); 752 } else { 753 vlv_dsi_pll_disable(encoder); 754 vlv_dsi_pll_enable(encoder, pipe_config); 755 } 756 757 if (IS_BROXTON(dev_priv)) { 758 /* Add MIPI IO reset programming for modeset */ 759 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); 760 761 /* Power up DSI regulator */ 762 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 763 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 764 } 765 766 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 767 /* Disable DPOunit clock gating, can stall pipe */ 768 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), 769 0, DPOUNIT_CLOCK_GATE_DISABLE); 770 } 771 772 if (!IS_GEMINILAKE(dev_priv)) 773 intel_dsi_prepare(encoder, pipe_config); 774 775 /* Give the panel time to power-on and then deassert its reset */ 776 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 777 msleep(intel_dsi->panel_on_delay); 778 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 779 780 if (IS_GEMINILAKE(dev_priv)) { 781 glk_cold_boot = glk_dsi_enable_io(encoder); 782 783 /* Prepare port in cold boot(s3/s4) scenario */ 784 if (glk_cold_boot) 785 intel_dsi_prepare(encoder, pipe_config); 786 } 787 788 /* Put device in ready state (LP-11) */ 789 intel_dsi_device_ready(encoder); 790 791 /* Prepare port in normal boot scenario */ 792 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) 793 intel_dsi_prepare(encoder, pipe_config); 794 795 /* Send initialization commands in LP mode */ 796 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 797 798 /* 799 * Enable port in pre-enable phase itself because as per hw team 800 * recommendation, port should be enabled before plane & pipe 801 */ 802 if (is_cmd_mode(intel_dsi)) { 803 for_each_dsi_port(port, intel_dsi->ports) 804 intel_de_write(display, 805 MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4); 806 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 807 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 808 } else { 809 msleep(20); /* XXX */ 810 for_each_dsi_port(port, intel_dsi->ports) 811 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 812 msleep(100); 813 814 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 815 816 intel_dsi_port_enable(encoder, pipe_config); 817 } 818 819 intel_backlight_enable(pipe_config, conn_state); 820 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 821 } 822 823 static void bxt_dsi_enable(struct intel_atomic_state *state, 824 struct intel_encoder *encoder, 825 const struct intel_crtc_state *crtc_state, 826 const struct drm_connector_state *conn_state) 827 { 828 intel_crtc_vblank_on(crtc_state); 829 } 830 831 /* 832 * DSI port disable has to be done after pipe and plane disable, so we do it in 833 * the post_disable hook. 834 */ 835 static void intel_dsi_disable(struct intel_atomic_state *state, 836 struct intel_encoder *encoder, 837 const struct intel_crtc_state *old_crtc_state, 838 const struct drm_connector_state *old_conn_state) 839 { 840 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 841 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 842 enum port port; 843 844 drm_dbg_kms(&i915->drm, "\n"); 845 846 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 847 intel_backlight_disable(old_conn_state); 848 849 /* 850 * According to the spec we should send SHUTDOWN before 851 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 852 * has shown that the v3 sequence works for v2 VBTs too 853 */ 854 if (is_vid_mode(intel_dsi)) { 855 /* Send Shutdown command to the panel in LP mode */ 856 for_each_dsi_port(port, intel_dsi->ports) 857 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 858 msleep(10); 859 } 860 } 861 862 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 863 { 864 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 865 866 if (IS_GEMINILAKE(dev_priv)) 867 glk_dsi_clear_device_ready(encoder); 868 else 869 vlv_dsi_clear_device_ready(encoder); 870 } 871 872 static void intel_dsi_post_disable(struct intel_atomic_state *state, 873 struct intel_encoder *encoder, 874 const struct intel_crtc_state *old_crtc_state, 875 const struct drm_connector_state *old_conn_state) 876 { 877 struct intel_display *display = to_intel_display(encoder); 878 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 879 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 880 enum port port; 881 882 drm_dbg_kms(display->drm, "\n"); 883 884 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 885 intel_crtc_vblank_off(old_crtc_state); 886 887 skl_scaler_disable(old_crtc_state); 888 } 889 890 if (is_vid_mode(intel_dsi)) { 891 for_each_dsi_port(port, intel_dsi->ports) 892 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 893 894 intel_dsi_port_disable(encoder); 895 usleep_range(2000, 5000); 896 } 897 898 intel_dsi_unprepare(encoder); 899 900 /* 901 * if disable packets are sent before sending shutdown packet then in 902 * some next enable sequence send turn on packet error is observed 903 */ 904 if (is_cmd_mode(intel_dsi)) 905 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 906 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 907 908 /* Transition to LP-00 */ 909 intel_dsi_clear_device_ready(encoder); 910 911 if (IS_BROXTON(dev_priv)) { 912 /* Power down DSI regulator to save power */ 913 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 914 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 915 HS_IO_CTRL_SELECT); 916 917 /* Add MIPI IO reset programming for modeset */ 918 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); 919 } 920 921 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 922 bxt_dsi_pll_disable(encoder); 923 } else { 924 vlv_dsi_pll_disable(encoder); 925 926 intel_de_rmw(display, DSPCLK_GATE_D(dev_priv), 927 DPOUNIT_CLOCK_GATE_DISABLE, 0); 928 } 929 930 /* Assert reset */ 931 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 932 933 msleep(intel_dsi->panel_off_delay); 934 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 935 936 intel_dsi->panel_power_off_time = ktime_get_boottime(); 937 } 938 939 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 940 enum pipe *pipe) 941 { 942 struct intel_display *display = to_intel_display(encoder); 943 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 944 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 945 intel_wakeref_t wakeref; 946 enum port port; 947 bool active = false; 948 949 drm_dbg_kms(display->drm, "\n"); 950 951 wakeref = intel_display_power_get_if_enabled(dev_priv, 952 encoder->power_domain); 953 if (!wakeref) 954 return false; 955 956 /* 957 * On Broxton the PLL needs to be enabled with a valid divider 958 * configuration, otherwise accessing DSI registers will hang the 959 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 960 */ 961 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 962 !bxt_dsi_pll_is_enabled(dev_priv)) 963 goto out_put_power; 964 965 /* XXX: this only works for one DSI output */ 966 for_each_dsi_port(port, intel_dsi->ports) { 967 i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port); 968 bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; 969 970 /* 971 * Due to some hardware limitations on VLV/CHV, the DPI enable 972 * bit in port C control register does not get set. As a 973 * workaround, check pipe B conf instead. 974 */ 975 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 976 port == PORT_C) 977 enabled = intel_de_read(display, 978 TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; 979 980 /* Try command mode if video mode not enabled */ 981 if (!enabled) { 982 u32 tmp = intel_de_read(display, 983 MIPI_DSI_FUNC_PRG(display, port)); 984 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 985 } 986 987 if (!enabled) 988 continue; 989 990 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) 991 continue; 992 993 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 994 u32 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 995 tmp &= BXT_PIPE_SELECT_MASK; 996 tmp >>= BXT_PIPE_SELECT_SHIFT; 997 998 if (drm_WARN_ON(display->drm, tmp > PIPE_C)) 999 continue; 1000 1001 *pipe = tmp; 1002 } else { 1003 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 1004 } 1005 1006 active = true; 1007 break; 1008 } 1009 1010 out_put_power: 1011 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1012 1013 return active; 1014 } 1015 1016 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1017 struct intel_crtc_state *pipe_config) 1018 { 1019 struct intel_display *display = to_intel_display(encoder); 1020 struct drm_display_mode *adjusted_mode = 1021 &pipe_config->hw.adjusted_mode; 1022 struct drm_display_mode *adjusted_mode_sw; 1023 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1024 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1025 unsigned int lane_count = intel_dsi->lane_count; 1026 unsigned int bpp, fmt; 1027 enum port port; 1028 u16 hactive, hfp, hsync, hbp, vfp, vsync; 1029 u16 hfp_sw, hsync_sw, hbp_sw; 1030 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1031 crtc_hblank_start_sw, crtc_hblank_end_sw; 1032 1033 /* FIXME: hw readout should not depend on SW state */ 1034 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1035 1036 /* 1037 * Atleast one port is active as encoder->get_config called only if 1038 * encoder->get_hw_state() returns true. 1039 */ 1040 for_each_dsi_port(port, intel_dsi->ports) { 1041 if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1042 break; 1043 } 1044 1045 fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK; 1046 bpp = mipi_dsi_pixel_format_to_bpp( 1047 pixel_format_from_register_bits(fmt)); 1048 1049 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1050 1051 /* Enable Frame time stamo based scanline reporting */ 1052 pipe_config->mode_flags |= 1053 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1054 1055 /* In terms of pixels */ 1056 adjusted_mode->crtc_hdisplay = 1057 intel_de_read(display, 1058 BXT_MIPI_TRANS_HACTIVE(port)); 1059 adjusted_mode->crtc_vdisplay = 1060 intel_de_read(display, 1061 BXT_MIPI_TRANS_VACTIVE(port)); 1062 adjusted_mode->crtc_vtotal = 1063 intel_de_read(display, 1064 BXT_MIPI_TRANS_VTOTAL(port)); 1065 1066 hactive = adjusted_mode->crtc_hdisplay; 1067 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); 1068 1069 /* 1070 * Meaningful for video mode non-burst sync pulse mode only, 1071 * can be zero for non-burst sync events and burst modes 1072 */ 1073 hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port)); 1074 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); 1075 1076 /* horizontal values are in terms of high speed byte clock */ 1077 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1078 intel_dsi->burst_mode_ratio); 1079 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1080 intel_dsi->burst_mode_ratio); 1081 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1082 intel_dsi->burst_mode_ratio); 1083 1084 if (intel_dsi->dual_link) { 1085 hfp *= 2; 1086 hsync *= 2; 1087 hbp *= 2; 1088 } 1089 1090 /* vertical values are in terms of lines */ 1091 vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); 1092 vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); 1093 1094 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1095 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1096 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1097 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1098 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1099 1100 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1101 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1102 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1103 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1104 1105 /* 1106 * In BXT DSI there is no regs programmed with few horizontal timings 1107 * in Pixels but txbyteclkhs.. So retrieval process adds some 1108 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1109 * Actually here for the given adjusted_mode, we are calculating the 1110 * value programmed to the port and then back to the horizontal timing 1111 * param in pixels. This is the expected value, including roundup errors 1112 * And if that is same as retrieved value from port, then 1113 * (HW state) adjusted_mode's horizontal timings are corrected to 1114 * match with SW state to nullify the errors. 1115 */ 1116 /* Calculating the value programmed to the Port register */ 1117 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1118 adjusted_mode_sw->crtc_hdisplay; 1119 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1120 adjusted_mode_sw->crtc_hsync_start; 1121 hbp_sw = adjusted_mode_sw->crtc_htotal - 1122 adjusted_mode_sw->crtc_hsync_end; 1123 1124 if (intel_dsi->dual_link) { 1125 hfp_sw /= 2; 1126 hsync_sw /= 2; 1127 hbp_sw /= 2; 1128 } 1129 1130 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1131 intel_dsi->burst_mode_ratio); 1132 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1133 intel_dsi->burst_mode_ratio); 1134 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1135 intel_dsi->burst_mode_ratio); 1136 1137 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1138 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1139 intel_dsi->burst_mode_ratio); 1140 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1141 intel_dsi->burst_mode_ratio); 1142 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1143 intel_dsi->burst_mode_ratio); 1144 1145 if (intel_dsi->dual_link) { 1146 hfp_sw *= 2; 1147 hsync_sw *= 2; 1148 hbp_sw *= 2; 1149 } 1150 1151 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1152 hsync_sw + hbp_sw; 1153 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1154 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1155 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1156 crtc_hblank_end_sw = crtc_htotal_sw; 1157 1158 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1159 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1160 1161 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1162 adjusted_mode->crtc_hsync_start = 1163 adjusted_mode_sw->crtc_hsync_start; 1164 1165 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1166 adjusted_mode->crtc_hsync_end = 1167 adjusted_mode_sw->crtc_hsync_end; 1168 1169 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1170 adjusted_mode->crtc_hblank_start = 1171 adjusted_mode_sw->crtc_hblank_start; 1172 1173 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1174 adjusted_mode->crtc_hblank_end = 1175 adjusted_mode_sw->crtc_hblank_end; 1176 } 1177 1178 static void intel_dsi_get_config(struct intel_encoder *encoder, 1179 struct intel_crtc_state *pipe_config) 1180 { 1181 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1182 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1183 u32 pclk; 1184 1185 drm_dbg_kms(&dev_priv->drm, "\n"); 1186 1187 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1188 1189 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1190 bxt_dsi_get_pipe_config(encoder, pipe_config); 1191 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1192 } else { 1193 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1194 } 1195 1196 pipe_config->port_clock = pclk; 1197 1198 /* FIXME definitely not right for burst/cmd mode/pixel overlap */ 1199 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1200 if (intel_dsi->dual_link) 1201 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1202 } 1203 1204 /* return txclkesc cycles in terms of divider and duration in us */ 1205 static u16 txclkesc(u32 divider, unsigned int us) 1206 { 1207 switch (divider) { 1208 case ESCAPE_CLOCK_DIVIDER_1: 1209 default: 1210 return 20 * us; 1211 case ESCAPE_CLOCK_DIVIDER_2: 1212 return 10 * us; 1213 case ESCAPE_CLOCK_DIVIDER_4: 1214 return 5 * us; 1215 } 1216 } 1217 1218 static void set_dsi_timings(struct intel_encoder *encoder, 1219 const struct drm_display_mode *adjusted_mode) 1220 { 1221 struct intel_display *display = to_intel_display(encoder); 1222 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1223 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1224 enum port port; 1225 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1226 unsigned int lane_count = intel_dsi->lane_count; 1227 1228 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1229 1230 hactive = adjusted_mode->crtc_hdisplay; 1231 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1232 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1233 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1234 1235 if (intel_dsi->dual_link) { 1236 hactive /= 2; 1237 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1238 hactive += intel_dsi->pixel_overlap; 1239 hfp /= 2; 1240 hsync /= 2; 1241 hbp /= 2; 1242 } 1243 1244 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1245 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1246 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1247 1248 /* horizontal values are in terms of high speed byte clock */ 1249 hactive = txbyteclkhs(hactive, bpp, lane_count, 1250 intel_dsi->burst_mode_ratio); 1251 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1252 hsync = txbyteclkhs(hsync, bpp, lane_count, 1253 intel_dsi->burst_mode_ratio); 1254 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1255 1256 for_each_dsi_port(port, intel_dsi->ports) { 1257 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1258 /* 1259 * Program hdisplay and vdisplay on MIPI transcoder. 1260 * This is different from calculated hactive and 1261 * vactive, as they are calculated per channel basis, 1262 * whereas these values should be based on resolution. 1263 */ 1264 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), 1265 adjusted_mode->crtc_hdisplay); 1266 intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), 1267 adjusted_mode->crtc_vdisplay); 1268 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), 1269 adjusted_mode->crtc_vtotal); 1270 } 1271 1272 intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), 1273 hactive); 1274 intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp); 1275 1276 /* meaningful for video mode non-burst sync pulse mode only, 1277 * can be zero for non-burst sync events and burst modes */ 1278 intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port), 1279 hsync); 1280 intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp); 1281 1282 /* vertical values are in terms of lines */ 1283 intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp); 1284 intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port), 1285 vsync); 1286 intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp); 1287 } 1288 } 1289 1290 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1291 { 1292 switch (fmt) { 1293 case MIPI_DSI_FMT_RGB888: 1294 return VID_MODE_FORMAT_RGB888; 1295 case MIPI_DSI_FMT_RGB666: 1296 return VID_MODE_FORMAT_RGB666; 1297 case MIPI_DSI_FMT_RGB666_PACKED: 1298 return VID_MODE_FORMAT_RGB666_PACKED; 1299 case MIPI_DSI_FMT_RGB565: 1300 return VID_MODE_FORMAT_RGB565; 1301 default: 1302 MISSING_CASE(fmt); 1303 return VID_MODE_FORMAT_RGB666; 1304 } 1305 } 1306 1307 static void intel_dsi_prepare(struct intel_encoder *encoder, 1308 const struct intel_crtc_state *pipe_config) 1309 { 1310 struct intel_display *display = to_intel_display(encoder); 1311 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1312 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1313 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1314 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1315 enum port port; 1316 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1317 u32 val, tmp; 1318 u16 mode_hdisplay; 1319 1320 drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); 1321 1322 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1323 1324 if (intel_dsi->dual_link) { 1325 mode_hdisplay /= 2; 1326 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1327 mode_hdisplay += intel_dsi->pixel_overlap; 1328 } 1329 1330 for_each_dsi_port(port, intel_dsi->ports) { 1331 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1332 /* 1333 * escape clock divider, 20MHz, shared for A and C. 1334 * device ready must be off when doing this! txclkesc? 1335 */ 1336 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); 1337 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1338 intel_de_write(display, MIPI_CTRL(display, PORT_A), 1339 tmp | ESCAPE_CLOCK_DIVIDER_1); 1340 1341 /* read request priority is per pipe */ 1342 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 1343 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1344 intel_de_write(display, MIPI_CTRL(display, port), 1345 tmp | READ_REQUEST_PRIORITY_HIGH); 1346 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1347 enum pipe pipe = crtc->pipe; 1348 1349 intel_de_rmw(display, MIPI_CTRL(display, port), 1350 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); 1351 } 1352 1353 /* XXX: why here, why like this? handling in irq handler?! */ 1354 intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff); 1355 intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff); 1356 1357 intel_de_write(display, MIPI_DPHY_PARAM(display, port), 1358 intel_dsi->dphy_reg); 1359 1360 intel_de_write(display, MIPI_DPI_RESOLUTION(display, port), 1361 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1362 } 1363 1364 set_dsi_timings(encoder, adjusted_mode); 1365 1366 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1367 if (is_cmd_mode(intel_dsi)) { 1368 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1369 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1370 } else { 1371 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1372 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1373 } 1374 1375 tmp = 0; 1376 if (intel_dsi->eotp_pkt == 0) 1377 tmp |= EOT_DISABLE; 1378 if (intel_dsi->clock_stop) 1379 tmp |= CLOCKSTOP; 1380 1381 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1382 tmp |= BXT_DPHY_DEFEATURE_EN; 1383 if (!is_cmd_mode(intel_dsi)) 1384 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1385 } 1386 1387 for_each_dsi_port(port, intel_dsi->ports) { 1388 intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val); 1389 1390 /* timeouts for recovery. one frame IIUC. if counter expires, 1391 * EOT and stop state. */ 1392 1393 /* 1394 * In burst mode, value greater than one DPI line Time in byte 1395 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1396 * said value is recommended. 1397 * 1398 * In non-burst mode, Value greater than one DPI frame time in 1399 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1400 * said value is recommended. 1401 * 1402 * In DBI only mode, value greater than one DBI frame time in 1403 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1404 * said value is recommended. 1405 */ 1406 1407 if (is_vid_mode(intel_dsi) && 1408 intel_dsi->video_mode == BURST_MODE) { 1409 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), 1410 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1411 } else { 1412 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), 1413 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1414 } 1415 intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port), 1416 intel_dsi->lp_rx_timeout); 1417 intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port), 1418 intel_dsi->turn_arnd_val); 1419 intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port), 1420 intel_dsi->rst_timer_val); 1421 1422 /* dphy stuff */ 1423 1424 /* in terms of low power clock */ 1425 intel_de_write(display, MIPI_INIT_COUNT(display, port), 1426 txclkesc(intel_dsi->escape_clk_div, 100)); 1427 1428 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1429 !intel_dsi->dual_link) { 1430 /* 1431 * BXT spec says write MIPI_INIT_COUNT for 1432 * both the ports, even if only one is 1433 * getting used. So write the other port 1434 * if not in dual link mode. 1435 */ 1436 intel_de_write(display, 1437 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), 1438 intel_dsi->init_count); 1439 } 1440 1441 /* recovery disables */ 1442 intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp); 1443 1444 /* in terms of low power clock */ 1445 intel_de_write(display, MIPI_INIT_COUNT(display, port), 1446 intel_dsi->init_count); 1447 1448 /* in terms of txbyteclkhs. actual high to low switch + 1449 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1450 * 1451 * XXX: write MIPI_STOP_STATE_STALL? 1452 */ 1453 intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port), 1454 intel_dsi->hs_to_lp_count); 1455 1456 /* XXX: low power clock equivalence in terms of byte clock. 1457 * the number of byte clocks occupied in one low power clock. 1458 * based on txbyteclkhs and txclkesc. 1459 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1460 * ) / 105.??? 1461 */ 1462 intel_de_write(display, MIPI_LP_BYTECLK(display, port), 1463 intel_dsi->lp_byte_clk); 1464 1465 if (IS_GEMINILAKE(dev_priv)) { 1466 intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port), 1467 intel_dsi->lp_byte_clk); 1468 /* Shadow of DPHY reg */ 1469 intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port), 1470 intel_dsi->dphy_reg); 1471 } 1472 1473 /* the bw essential for transmitting 16 long packets containing 1474 * 252 bytes meant for dcs write memory command is programmed in 1475 * this register in terms of byte clocks. based on dsi transfer 1476 * rate and the number of lanes configured the time taken to 1477 * transmit 16 long packets in a dsi stream varies. */ 1478 intel_de_write(display, MIPI_DBI_BW_CTRL(display, port), 1479 intel_dsi->bw_timer); 1480 1481 intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port), 1482 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1483 1484 if (is_vid_mode(intel_dsi)) { 1485 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; 1486 1487 /* 1488 * Some panels might have resolution which is not a 1489 * multiple of 64 like 1366 x 768. Enable RANDOM 1490 * resolution support for such panels by default. 1491 */ 1492 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION; 1493 1494 switch (intel_dsi->video_mode) { 1495 default: 1496 MISSING_CASE(intel_dsi->video_mode); 1497 fallthrough; 1498 case NON_BURST_SYNC_EVENTS: 1499 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS; 1500 break; 1501 case NON_BURST_SYNC_PULSE: 1502 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE; 1503 break; 1504 case BURST_MODE: 1505 fmt |= VIDEO_MODE_BURST; 1506 break; 1507 } 1508 1509 intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt); 1510 } 1511 } 1512 } 1513 1514 static void intel_dsi_unprepare(struct intel_encoder *encoder) 1515 { 1516 struct intel_display *display = to_intel_display(encoder); 1517 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1518 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1519 enum port port; 1520 1521 if (IS_GEMINILAKE(dev_priv)) 1522 return; 1523 1524 for_each_dsi_port(port, intel_dsi->ports) { 1525 /* Panel commands can be sent when clock is in LP11 */ 1526 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0); 1527 1528 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1529 bxt_dsi_reset_clocks(encoder, port); 1530 else 1531 vlv_dsi_reset_clocks(encoder, port); 1532 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); 1533 1534 intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0); 1535 1536 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1); 1537 } 1538 } 1539 1540 static const struct drm_encoder_funcs intel_dsi_funcs = { 1541 .destroy = intel_encoder_destroy, 1542 }; 1543 1544 static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector, 1545 struct drm_display_mode *mode) 1546 { 1547 struct drm_i915_private *i915 = to_i915(connector->dev); 1548 1549 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1550 enum drm_mode_status status; 1551 1552 status = intel_cpu_transcoder_mode_valid(i915, mode); 1553 if (status != MODE_OK) 1554 return status; 1555 } 1556 1557 return intel_dsi_mode_valid(connector, mode); 1558 } 1559 1560 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1561 .get_modes = intel_dsi_get_modes, 1562 .mode_valid = vlv_dsi_mode_valid, 1563 .atomic_check = intel_digital_connector_atomic_check, 1564 }; 1565 1566 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1567 .detect = intel_panel_detect, 1568 .late_register = intel_connector_register, 1569 .early_unregister = intel_connector_unregister, 1570 .destroy = intel_connector_destroy, 1571 .fill_modes = drm_helper_probe_single_connector_modes, 1572 .atomic_get_property = intel_digital_connector_atomic_get_property, 1573 .atomic_set_property = intel_digital_connector_atomic_set_property, 1574 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1575 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1576 }; 1577 1578 static void vlv_dsi_add_properties(struct intel_connector *connector) 1579 { 1580 const struct drm_display_mode *fixed_mode = 1581 intel_panel_preferred_fixed_mode(connector); 1582 1583 intel_attach_scaling_mode_property(&connector->base); 1584 1585 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1586 intel_dsi_get_panel_orientation(connector), 1587 fixed_mode->hdisplay, 1588 fixed_mode->vdisplay); 1589 } 1590 1591 #define NS_KHZ_RATIO 1000000 1592 1593 #define PREPARE_CNT_MAX 0x3F 1594 #define EXIT_ZERO_CNT_MAX 0x3F 1595 #define CLK_ZERO_CNT_MAX 0xFF 1596 #define TRAIL_CNT_MAX 0x1F 1597 1598 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1599 { 1600 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 1601 struct intel_connector *connector = intel_dsi->attached_connector; 1602 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1603 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1604 u32 ui_num, ui_den; 1605 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1606 u32 ths_prepare_ns, tclk_trail_ns; 1607 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1608 u32 lp_to_hs_switch, hs_to_lp_switch; 1609 u32 mul; 1610 1611 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1612 1613 switch (intel_dsi->lane_count) { 1614 case 1: 1615 case 2: 1616 extra_byte_count = 2; 1617 break; 1618 case 3: 1619 extra_byte_count = 4; 1620 break; 1621 case 4: 1622 default: 1623 extra_byte_count = 3; 1624 break; 1625 } 1626 1627 /* in Kbps */ 1628 ui_num = NS_KHZ_RATIO; 1629 ui_den = intel_dsi_bitrate(intel_dsi); 1630 1631 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1632 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1633 1634 /* 1635 * B060 1636 * LP byte clock = TLPX/ (8UI) 1637 */ 1638 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1639 1640 /* DDR clock period = 2 * UI 1641 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1642 * UI(nsec) = 10^6 / bitrate 1643 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1644 * DDR clock count = ns_value / DDR clock period 1645 * 1646 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1647 * HS byte clock count for other platform in HS ddr clock count 1648 */ 1649 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; 1650 ths_prepare_ns = max(mipi_config->ths_prepare, 1651 mipi_config->tclk_prepare); 1652 1653 /* prepare count */ 1654 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1655 1656 if (prepare_cnt > PREPARE_CNT_MAX) { 1657 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", 1658 prepare_cnt); 1659 prepare_cnt = PREPARE_CNT_MAX; 1660 } 1661 1662 /* exit zero count */ 1663 exit_zero_cnt = DIV_ROUND_UP( 1664 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1665 ui_num * mul 1666 ); 1667 1668 /* 1669 * Exit zero is unified val ths_zero and ths_exit 1670 * minimum value for ths_exit = 110ns 1671 * min (exit_zero_cnt * 2) = 110/UI 1672 * exit_zero_cnt = 55/UI 1673 */ 1674 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1675 exit_zero_cnt += 1; 1676 1677 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1678 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", 1679 exit_zero_cnt); 1680 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1681 } 1682 1683 /* clk zero count */ 1684 clk_zero_cnt = DIV_ROUND_UP( 1685 (tclk_prepare_clkzero - ths_prepare_ns) 1686 * ui_den, ui_num * mul); 1687 1688 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1689 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", 1690 clk_zero_cnt); 1691 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1692 } 1693 1694 /* trail count */ 1695 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1696 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1697 1698 if (trail_cnt > TRAIL_CNT_MAX) { 1699 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", 1700 trail_cnt); 1701 trail_cnt = TRAIL_CNT_MAX; 1702 } 1703 1704 /* B080 */ 1705 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1706 clk_zero_cnt << 8 | prepare_cnt; 1707 1708 /* 1709 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1710 * mul + 10UI + Extra Byte Count 1711 * 1712 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1713 * Extra Byte Count is calculated according to number of lanes. 1714 * High Low Switch Count is the Max of LP to HS and 1715 * HS to LP switch count 1716 * 1717 */ 1718 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1719 1720 /* B044 */ 1721 /* FIXME: 1722 * The comment above does not match with the code */ 1723 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1724 exit_zero_cnt * mul + 10, 8); 1725 1726 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1727 1728 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1729 intel_dsi->hs_to_lp_count += extra_byte_count; 1730 1731 /* B088 */ 1732 /* LP -> HS for clock lanes 1733 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1734 * extra byte count 1735 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1736 * 2(in UI) + extra byte count 1737 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1738 * 8 + extra byte count 1739 */ 1740 intel_dsi->clk_lp_to_hs_count = 1741 DIV_ROUND_UP( 1742 4 * tlpx_ui + prepare_cnt * 2 + 1743 clk_zero_cnt * 2, 1744 8); 1745 1746 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1747 1748 /* HS->LP for Clock Lanes 1749 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1750 * Extra byte count 1751 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1752 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1753 * Extra byte count 1754 */ 1755 intel_dsi->clk_hs_to_lp_count = 1756 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1757 8); 1758 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1759 1760 intel_dsi_log_params(intel_dsi); 1761 } 1762 1763 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi); 1764 1765 /* 1766 * Vtotal is wrong on the Asus TF103C leading to the last line of the display 1767 * being shown as the first line. The factory installed Android has a hardcoded 1768 * modeline, causing it to not suffer from this BIOS bug. 1769 * 1770 * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa 1771 * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa 1772 * 1773 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381 1774 */ 1775 static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi) 1776 { 1777 /* Cast away the const as we want to fixup the mode */ 1778 struct drm_display_mode *fixed_mode = (struct drm_display_mode *) 1779 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); 1780 1781 if (fixed_mode->vtotal == 820) 1782 fixed_mode->vtotal -= 4; 1783 } 1784 1785 /* 1786 * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems: 1787 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7 1788 * which under Linux become bus 0 - 6. And the MIPI sequence reference 1789 * to bus 3 is indented for I2C3 which is bus 2 under Linux. 1790 * 1791 * Note mipi_exec_i2c() cannot just subtract 1 from the bus 1792 * given in the I2C MIPI sequence element. Since on other 1793 * devices the I2C bus-numbers used in the MIPI sequences do 1794 * actually start at 0. 1795 * 1796 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is 1797 * especially a problem on the 8" 830 version which uses a 10:16 1798 * portrait screen where as the bogus size is 16:10. 1799 * 1800 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379 1801 */ 1802 static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi) 1803 { 1804 const struct drm_display_mode *fixed_mode = 1805 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); 1806 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info; 1807 1808 intel_dsi->i2c_bus_num = 2; 1809 1810 /* 1811 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830 1812 * uses a 1200x1920 portrait screen. 1813 */ 1814 if (fixed_mode->hdisplay == 1920) { 1815 info->width_mm = 216; 1816 info->height_mm = 135; 1817 } else { 1818 info->width_mm = 107; 1819 info->height_mm = 171; 1820 } 1821 } 1822 1823 /* 1824 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems: 1825 * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c() 1826 * to not work. Fix this by setting i2c_bus_num. 1827 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on. 1828 * Add a backlight off sequence mirroring the existing backlight on sequence. 1829 * 1830 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380 1831 */ 1832 static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi) 1833 { 1834 static const u8 backlight_off_sequence[16] = { 1835 /* Header Seq-id 7, length after header 11 bytes */ 1836 0x07, 0x0b, 0x00, 0x00, 0x00, 1837 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */ 1838 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00, 1839 /* MIPI_SEQ_ELEM_END */ 1840 0x00 1841 }; 1842 struct intel_connector *connector = intel_dsi->attached_connector; 1843 1844 intel_dsi->i2c_bus_num = 0; 1845 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence; 1846 } 1847 1848 static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = { 1849 { 1850 /* Asus Transformer Pad TF103C */ 1851 .matches = { 1852 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 1853 DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"), 1854 }, 1855 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup, 1856 }, 1857 { 1858 /* 1859 * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10" 1860 * Lenovo Yoga Tablet 2 use the same mainboard) 1861 */ 1862 .matches = { 1863 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."), 1864 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"), 1865 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"), 1866 /* Partial match on beginning of BIOS version */ 1867 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"), 1868 }, 1869 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup, 1870 }, 1871 { 1872 /* Lenovo Yoga Tab 3 Pro YT3-X90F */ 1873 .matches = { 1874 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), 1875 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"), 1876 }, 1877 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup, 1878 }, 1879 { } 1880 }; 1881 1882 void vlv_dsi_init(struct drm_i915_private *dev_priv) 1883 { 1884 struct intel_display *display = &dev_priv->display; 1885 struct intel_dsi *intel_dsi; 1886 struct intel_encoder *encoder; 1887 struct intel_connector *connector; 1888 struct drm_display_mode *current_mode; 1889 const struct dmi_system_id *dmi_id; 1890 enum port port; 1891 enum pipe pipe; 1892 1893 drm_dbg_kms(&dev_priv->drm, "\n"); 1894 1895 /* There is no detection method for MIPI so rely on VBT */ 1896 if (!intel_bios_is_dsi_present(display, &port)) 1897 return; 1898 1899 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1900 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE; 1901 else 1902 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE; 1903 1904 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1905 if (!intel_dsi) 1906 return; 1907 1908 connector = intel_connector_alloc(); 1909 if (!connector) { 1910 kfree(intel_dsi); 1911 return; 1912 } 1913 1914 encoder = &intel_dsi->base; 1915 intel_dsi->attached_connector = connector; 1916 1917 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs, 1918 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1919 1920 encoder->compute_config = intel_dsi_compute_config; 1921 encoder->pre_enable = intel_dsi_pre_enable; 1922 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1923 encoder->enable = bxt_dsi_enable; 1924 encoder->disable = intel_dsi_disable; 1925 encoder->post_disable = intel_dsi_post_disable; 1926 encoder->get_hw_state = intel_dsi_get_hw_state; 1927 encoder->get_config = intel_dsi_get_config; 1928 encoder->update_pipe = intel_backlight_update; 1929 encoder->shutdown = intel_dsi_shutdown; 1930 1931 connector->get_hw_state = intel_connector_get_hw_state; 1932 1933 encoder->port = port; 1934 encoder->type = INTEL_OUTPUT_DSI; 1935 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1936 encoder->cloneable = 0; 1937 1938 /* 1939 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1940 * port C. BXT isn't limited like this. 1941 */ 1942 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1943 encoder->pipe_mask = ~0; 1944 else if (port == PORT_A) 1945 encoder->pipe_mask = BIT(PIPE_A); 1946 else 1947 encoder->pipe_mask = BIT(PIPE_B); 1948 1949 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1950 1951 intel_bios_init_panel_late(display, &connector->panel, NULL, NULL); 1952 1953 if (connector->panel.vbt.dsi.config->dual_link) 1954 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1955 else 1956 intel_dsi->ports = BIT(port); 1957 1958 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 1959 connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 1960 1961 if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 1962 connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 1963 1964 /* Create a DSI host (and a device) for each port. */ 1965 for_each_dsi_port(port, intel_dsi->ports) { 1966 struct intel_dsi_host *host; 1967 1968 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1969 port); 1970 if (!host) 1971 goto err; 1972 1973 intel_dsi->dsi_hosts[port] = host; 1974 } 1975 1976 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1977 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1978 goto err; 1979 } 1980 1981 /* Use clock read-back from current hw-state for fastboot */ 1982 current_mode = intel_encoder_current_mode(encoder); 1983 if (current_mode) { 1984 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", 1985 intel_dsi->pclk, current_mode->clock); 1986 if (intel_fuzzy_clock_check(intel_dsi->pclk, 1987 current_mode->clock)) { 1988 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); 1989 intel_dsi->pclk = current_mode->clock; 1990 } 1991 1992 kfree(current_mode); 1993 } 1994 1995 vlv_dphy_param_init(intel_dsi); 1996 1997 intel_dsi_vbt_gpio_init(intel_dsi, 1998 intel_dsi_get_hw_state(encoder, &pipe)); 1999 2000 drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs, 2001 DRM_MODE_CONNECTOR_DSI); 2002 2003 drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs); 2004 2005 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 2006 2007 intel_connector_attach_encoder(connector, encoder); 2008 2009 mutex_lock(&dev_priv->drm.mode_config.mutex); 2010 intel_panel_add_vbt_lfp_fixed_mode(connector); 2011 mutex_unlock(&dev_priv->drm.mode_config.mutex); 2012 2013 if (!intel_panel_preferred_fixed_mode(connector)) { 2014 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); 2015 goto err_cleanup_connector; 2016 } 2017 2018 dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table); 2019 if (dmi_id) { 2020 vlv_dsi_dmi_quirk_func quirk_func = 2021 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data; 2022 2023 quirk_func(intel_dsi); 2024 } 2025 2026 intel_panel_init(connector, NULL); 2027 2028 intel_backlight_setup(connector, INVALID_PIPE); 2029 2030 vlv_dsi_add_properties(connector); 2031 2032 return; 2033 2034 err_cleanup_connector: 2035 drm_connector_cleanup(&connector->base); 2036 err: 2037 drm_encoder_cleanup(&encoder->base); 2038 kfree(intel_dsi); 2039 kfree(connector); 2040 } 2041